ltc1744 Linear Technology Corporation, ltc1744 Datasheet

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ltc1744

Manufacturer Part Number
ltc1744
Description
14-bit, 50msps Adc
Manufacturer
Linear Technology Corporation
Datasheet

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FEATURES
BLOCK DIAGRA
APPLICATIO S
, LTC and LT are registered trademarks of Linear Technology Corporation.
Sample Rate: 50Msps
77dB SNR and 87dB SFDR (3.2V Range)
73.5dB SNR and 90dB SFDR (2V Range)
No Missing Codes
Single 5V Supply
Power Dissipation: 1.2W
Selectable Input Ranges: 1V or 1.6V
150MHz Full Power Bandwidth S/H
Pin Compatible Family
25Msps: LTC1746 (14 Bit), LTC1745 (12 Bit)
50Msps: LTC1744 (14 Bit), LTC1743 (12 Bit)
65Msps: LTC1742 (14 Bit), LTC1741 (12 Bit)
80Msps: LTC1748 (14 Bit), LTC1747 (12 Bit)
48-Pin TSSOP Package
Telecommunications
Receivers
Base Stations
Spectrum Analysis
Imaging Systems
ANALOG INPUT
DIFFERENTIAL
4.7 F
1V
SENSE
A
A
V
IN
IN
CM
+
U
2.5V
SELECT
RANGE
REF
W
BUFFER
50Msps, 14-Bit ADC with a 1V Differential Input Range
CIRCUIT
S/H
DIFF AMP
REFLB
0.1 F
1 F
PIPELINED ADC
14-BIT
REFHA
4.7 F
DESCRIPTIO
The LTC
verter designed for digitizing high frequency, wide dynamic
range signals. Pin selectable input ranges of 1V and 1.6V
along with a resistor programmable mode allow the
LTC1744’s input range to be optimized for a wide variety
of applications.
The LTC1744 is perfect for demanding communications
applications with AC performance that includes 77dB
SNR and 87dB spurious free dynamic range. Ultralow jitter
of 0.3ps
excellent noise performance. DC specs include 4LSB
maximum INL and no missing codes over temperature.
The digital interface is compatible with 5V, 3V and 2V logic
systems. The ENC and ENC inputs may be driven differen-
tially from PECL, GTL and other low swing logic families or
from single-ended TTL or CMOS. The low noise, high gain
ENC and ENC inputs may also be driven by a sinusoidal
signal without degrading performance. A separate output
power supply can be operated from 0.5V to 5V, making it
easy to connect directly to any low voltage DSPs or FIFOs.
The TSSOP package with a flow-through pinout simplifies
the board layout.
REFLA
0.1 F
1 F
REFHB
RMS
®
1744 is a 50Msps, sampling 14-bit A/D con-
ENCODE INPUT
DIFFERENTIAL
CORRECTION
LOGIC AND
REGISTER
ENC
allows undersampling of IF frequencies with
SHIFT
CONTROL LOGIC
ENC
U
14
14-Bit, 50Msps ADC
MSBINV
LATCHES
OUTPUT
OE
GND
OGND
V
1744 BD
DD
OF
D13
D0
CLKOUT
OV
1 F
DD
0.1 F
1 F
LTC1744
0.1 F
0.5V TO 5V
1 F
5V
1
1744f

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ltc1744 Summary of contents

Page 1

... Pin selectable input ranges of 1V and 1.6V along with a resistor programmable mode allow the LTC1744’s input range to be optimized for a wide variety of applications. The LTC1744 is perfect for demanding communications applications with AC performance that includes 77dB SNR and 87dB spurious free dynamic range ...

Page 2

... Digital Output Voltage ................. – 0. OGND Voltage ..............................................– 0. Power Dissipation ............................................ 2000mW Operating Temperature Range LTC1744C ............................................... LTC1744I ............................................ – Storage Temperature Range ................. – 150 C Lead Temperature (Soldering, 10 sec).................. 300 VERTER CHARACTERISTICS temperature range, otherwise specifications are at T ...

Page 3

... Input Signal, First 5 Harmonics (3.2V Range 2.52MHz 5.2MHz (2V Range) IN1 IN2 f = 2.52MHz 5.2MHz (3.2V Range) IN1 IN2 SOURCE (Note 5) CONDITIONS OUT OUT 4.75V V 5.25V DD 1mA I 1mA OUT LTC1744 MIN TYP MAX UNITS 73.5 dBFS 75.5 77 dBFS 72.5 dBFS 75.5 dBFS 70 dBFS 71.5 dBFS ...

Page 4

... LTC1744 U U DIGITAL I PUTS A D DIGITAL OUTPUTS operating temperature range, otherwise specifications are at T SYMBOL PARAMETER V High Level Input Voltage IH V Low Level Input Voltage IL I Digital Input Current IN C Digital Input Capacitance IN V High Level Output Voltage OH V Low Level Output Voltage ...

Page 5

... FREQUENCY (MHz) 1744 G08 LTC1744 Nonaveraged, 8192 Point FFT, Input Frequency = 2.5MHz, –1dB, 2V Range 0 –10.0 –20.0 –30.0 –40.0 –50.0 –60.0 –70.0 –80.0 – ...

Page 6

... LTC1744 W U TYPICAL PERFOR A CE CHARACTERISTICS Averaged, 8192 Point FFT, Input Frequency = 2.5MHz, – 6dB, 3.2V Range 0 –10.0 –20.0 –30.0 –40.0 –50.0 –60.0 –70.0 –80.0 –90.0 –100.0 –110.0 –120 25.37 FREQUENCY (MHz) 1744 G11 Averaged, 8192 Point FFT, Input Frequency = 20MHz, – ...

Page 7

... SNR vs Input Frequency and Amplitude, 3.2V Range –1dBFS 75 – 6dBFS – 20dBFS 55 50 100 1 10 INPUT FREQUENCY (MHz) LTC1744 (Note 5) Averaged, 8192 Point FFT, Input Frequency = 70MHz, – 6dB, 2V Range 0 –10.0 –20.0 –30.0 –40.0 –50.0 –60.0 –70.0 –80.0 –90.0 –100.0 – ...

Page 8

... LTC1744 W U TYPICAL PERFOR A CE CHARACTERISTICS SFDR vs Input Frequency and Amplitude, 3.2V Range 120 – 20dBFS 110 100 – 6dBFS 90 80 –1dBFS 100 INPUT FREQUENCY (MHz) 1744 G33 2nd and 3rd Harmonic vs Input Frequency, 2V Range, –1dB – – ...

Page 9

... Bypass to ground with 0.1 F ceramic chip capacitor. D4-D6 (Pins 33 to 35): Digital Outputs. D7-D10 (Pins 39 to 42): Digital Outputs. D11-D13 (Pins 44 to 46): Digital Outputs. D13 is the MSB. OF (Pin 48): Over/Under Flow Output. High when an over or under flow has occurred. LTC1744 (Note ...

Page 10

... LTC1744 DIAGRA N ANALOG INPUT ENCODE t 6 DATA t 5 CLKOUT DATA CTIO AL BLOCK DIAGRA + DIFFERENTIAL CIRCUIT ANALOG INPUT – SENSE BUFFER RANGE SELECT V CM 2.5V REF 4 DATA (N – 5) DB13 TO DB0 ...

Page 11

... SNR JITTER CONVERTER OPERATION As shown in Figure 1, the LTC1744 is a CMOS pipelined multistep converter. The converter has four pipelined ADC stages; a sampled analog input will result in a digitized value five cycles later, see the Timing Diagram section. The analog input is differential for improved common mode noise immunity and to maximize the input range ...

Page 12

... SAMPLE/HOLD OPERATION AND INPUT DRIVE Sample Hold Operation Figure 2 shows an equivalent circuit for the LTC1744 CMOS differential sample-and-hold. The differential ana- log inputs are sampled directly onto sampling capacitors (C ) through CMOS transmission gates ...

Page 13

... Input Drive Impedance As with all high performance, high speed ADCs the dy- 1744 F02 namic performance of the LTC1744 can be influenced by the input drive circuitry, particularly the second and third harmonics. Source impedance and input reactance can influence SFDR. At the falling edge of encode the sample- and-hold circuit will connect the 7pF sampling capacitor to the input pin and start the sampling period ...

Page 14

... LTC1744 U U APPLICATIO S I FOR ATIO Input Drive Circuits Figure 3 shows the LTC1744 being driven transformer with a center tapped secondary. The second- ary center tap is DC biased with V CM signal at its optimum DC level. Figure 3 shows a 1:1 turns ratio transformer. Other turns ratios can be used if the source impedence seen by the ADC does not exceed 100 for each ADC input ...

Page 15

... BUFFER INTERNAL ADC 0.1 F HIGH REFERENCE REFHA 4.7 F DIFF AMP REFLA 0.1 F INTERNAL ADC LOW REFERENCE REFHB Figure 5. Equivalent Reference Circuit 5V 0.1 F 1744 F06a Figure 6b. 2.5V Range ADC with an External Reference LTC1744 1744 F05 V CM 2.5V 4.7 F LTC1744 4 6 1.25V SENSE LT1790-1. 1744 F06b 1744f 15 ...

Page 16

... W U Driving the Encode Inputs The noise performance of the LTC1744 can depend on the encode signal quality as much as on the analog input. The ENC/ENC inputs are intended to be driven differentially, primarily for noise immunity from common mode noise sources. Each input is biased through a 6k resistor bias ...

Page 17

... At sample rates slower than 50Msps the duty cycle can vary from 50% as long as each half cycle is at least 9.5ns. The lower limit of the LTC1744 sample rate is determined by droop of the sample-and-hold circuits. The pipelined architecture of this ADC relies on storing analog signals on small valued capacitors ...

Page 18

... U Lower OV from the digital outputs. Format and OGND, iso- The LTC1744 parallel digital output can be selected for DD offset binary or 2’s complement format. The format is selected with the MSBINV pin; high selects offset binary. Overflow Bit An overflow output bit indicates when the converter is overranged or underranged ...

Page 19

... ADC OGND (Pin 38). HEAT TRANSFER Most of the heat generated by the LTC1744 is transferred from the die through the package leads onto the printed circuit board. In particular, ground pins 12, 13, 36 and 37 are fused to the die attach pad. These pins have the lowest thermal resistance between the die and the outside envi- ronment ...

Page 20

... LTC1744 U U APPLICATIO S I FOR ATIO 1744f ...

Page 21

... U U APPLICATIO S I FOR ATIO W U Topside Silkscreen Topside Copper Layer Ground Plane, Layer 2 LTC1744 1744f 21 ...

Page 22

... LTC1744 U U APPLICATIO S I FOR ATIO Split Power Plane, Layer 3 Bottom Side Copper, Layer 4 1744f ...

Page 23

... BSC LTC1744 (.311 – .327) 1.20 (.0473) MAX 0.17 – 0.27 0.05 – 0.15 (.002 – .006) 7.9 – 8.3 -T- ...

Page 24

... SFDR at 1MHz f Pin Compatible with the LTC1744 Pin Compatible with the LTC1744 Pin Compatible with the LTC1744 Pin Compatible with the LTC1744 Pin Compatible with the LTC1744 Pin Compatible with the LTC1744 Pin Compatible with the LTC1744 www.linear.com , Low Power, Low Cost ...

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