LTC1873 Linear Technology, LTC1873 Datasheet
LTC1873
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LTC1873 Summary of contents
Page 1
... Burst Mode ing maximum efficiency over a wide range of load currents. The LTC1873 features an onboard reference trimmed to 1% and delivers better than 1.5% regulation at the converter outputs over all combinations of line, load and temperature. Each channel can be enabled independently; with both chan- nels disabled, the LTC1873 shuts down and supply current drops below 100 A ...
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... RUN/SS1 = RUN/SS2 = 0V (Note 6) Test Circuit 1 (Note 5) RUN/SS1 = RUN/SS2 = 0V (Note 6) Test Circuit 1 (Note 5) RUN/SS1 = RUN/SS2 = 0V Test Circuit FB2 Only (Note 7) RUN/ ORDER PART NUMBER 28 I MAX2 27 BOOST2 LTC1873EG 26 BG2 25 TG2 24 SW2 23 PGND 22 FAULT 21 RUN/SS2 20 COMP2 19 FB2 ...
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... PULLUP Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The LTC1873 is guaranteed to meet performance specifications from Specifications over the – operating temperature range are assured by design, characterization and correlation with statistical process controls ...
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... LTC1873 W U TYPICAL PERFOR A CE CHARACTERISTICS Efficiency vs Load Current 100 3.3V OUT V = 2.5V OUT 1.6V OUT LOAD CURRENT (A) 1873 G01 Supply Current vs Temperature 2.6 TEST CIRCUIT 0pF 2 2 2.0 1.8 1.6 1.4 BOOST1, BOOST2 1.2 1.0 – 50 – 100 125 TEMPERATURE ( C) ...
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... RUN/SS1 to SGND will disable controller 1 and turn off IN both of its external MOSFET switches. Pulling both RUN/SS pins down will shut down the entire LTC1873, dropping the quiescent supply current below capacitor from RUN/SS1 to SGND will control the turn-on time and rate of rise of the controller 1 output voltage at power-up ...
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... V should be connected to a low noise power supply voltage between 3V and 7V and should be bypassed to SGND with at least capacitor in close proximity to the LTC1873. FB2 (Pin 19): Controller 2 Feedback Input. FB2 should be connected through a resistor divider network to V set the ouput voltage ...
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... U U APPLICATIO S I FOR ATIO OVERVIEW The LTC1873 is a dual, step-down (buck), voltage mode feedback switching regulator controller designed to be used in a synchronous switching architecture with two external N-channel MOSFETs per channel intended to operate from a low voltage input supply (7V maximum) and provide a high power, high efficiency, precisely regu- lated output voltage ...
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... GND Float Float Float * 11111 is defined by Intel to signify “no CPU.” The LTC1873 will generate the output voltage shown when this codes is selected. allows regulated output voltages as low as 800mV without external level shifting amplifiers. The LTC1873’s synchronous switching logic transitions automatically into Burst Mode operation, maximizing effi- ciency with light loads ...
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... PCB real estate premium. Fast Transient Response The LTC1873 uses a fast 25MHz GBW op amp as an error amplifier. This allows the compensation network to be designed with several poles and zeros in a more flexible configuration than with a typical g ...
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... U U APPLICATIO S I FOR ATIO Switching Architecture Each half of the LTC1873 is designed to operate as a synchronous buck converter (Figure 1). Each channel includes two high power MOSFET gate drivers to control external N-channel MOSFETs QT and QB. These drivers have 0.5 output impedances and can carry well over an amp of continuous current with peak currents slew large MOSFET gates quickly ...
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... SHUTDOWN/SOFT-START Each half of the LTC1873 has a RUN/SS pin. The RUN/SS pins perform two functions: when pulled to ground, each shuts down its half of the LTC1873, and each acts as a conventional soft-start pin, enforcing a maximum duty cycle limit proportional to the voltage at RUN/SS. An internal 3.5 A current source pull-up is connected to each RUN/SS pin, allowing a soft-start ramp to be generated with a single external capacitor to ground ...
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... LTC1873 U U APPLICATIO S I FOR ATIO Each RUN/SS pin shuts down its half of the LTC1873 when it falls below about 0.5V (Figure 4). Between 0.5V and about 1V, that half is active, but the maximum duty cycle is limited to 10%. The maximum duty cycle limit increases linearly between 1V and 2.5V, reaching its final value of 90% when RUN/SS is above 2 ...
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... Continuous Bar) pin to ground. Discontinuous Mode To minimize the efficiency loss due to reverse current flow at light loads, the LTC1873 switches to a second mode of operation: discontinuous mode (Figure 5b). In discontinu- ous mode, the LTC1873 detects when the inductor current approaches zero and turns off QB for the remainder of the switch cycle ...
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... U Burst Mode Operation Discontinuous mode removes a loss term due to resistive drop in QB, but the LTC1873 is still switching QT and QB on and off once a cycle. Each time an external MOSFET is turned on, the internal driver must charge its gate to V Each time it is turned off, that charge is lost to ground. At ...
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... LTC1873 as a primary regulator and a small LDO as a backup regulator to keep SRAM alive when the main power is off. When the LTC1873 is shut down (by pulling RUN/SS to ground), both QT and QB turn off and the output goes into a high impedance state, allowing the smaller regulator to support the output volt- age ...
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... SS pins low simultaneously or cycle the power. VID Considerations Some applications change the VID codes at channel 1 on the fly. This is possible with the LTC1873, but care must be taken to avoid tripping the overvoltage fault circuit. Stepping the voltage upwards abruptly is safe, but step- ...
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... big deal since the source attached to PGND; the LTC1873 just switches the BG pin between PGND and V . Driving QT is another matter. The source connected to SW which rises to V on. To keep QT on, the LTC1873 must get TG one MOSFET V above does this by utilizing a floating driver GS(ON) CC ...
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... ESR tantalum or electrolytic capacitors in parallel, or with a large mono- lithic ceramic capacitor. The two sides of the LTC1873 run off a single master clock and are wired 180 out of phase with each other to significantly reduce the total capacitance/ESR needed at the input ...
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... LTC1873 applications, but they deserve a special caution here. Generic tantalum capacitors have a destruc- tive failure mechanism when they are subjected to large RMS currents (like those seen at the input of a LTC1873 current and resistive losses, but this approximate value is adequate for input capacitor calculation purposes ...
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... The output bypass capacitor has quite different require- ments from the input capacitor. The ripple current at the output of a buck regulator like the LTC1873 is much lower than at the input, due to the fact that the inductor current is constantly flowing at the output whenever the LTC1873 is operating in continuous mode ...
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... So far, the AC response of the loop is pretty well out of the user’s control. The modulator is a fundamental piece of the LTC1873 design, and the external L and C are usually chosen based on the regulation and load current require- ments without considering the AC loop response. The feedback amplifier, on the other hand, gives us a handle with which to adjust the AC response ...
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... To measure the modulator gain OUT and phase directly, wire up a breadboard with an LTC1873 and the actual MOSFETs, inductor, and input and output 1873 F11a capacitors that the final design will use. This breadboard ...
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... Type 2 Loop: K Tan Type 3 Loop: K Tan LTC1873 (this converts GAIN absolute BOOST GKR – REF V – V OUT REF BOOST – ...
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... DS(ON) to 150% of the LIM The FCB pin can be used in conjunction with a secondary winding on one side of the LTC1873 to generate a third regulated voltage output. This output can be directly regulated at the FCB pin. In theory, a fourth output could be added, either unregulated or with additional external circuitry at the FCB pin. ...
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... If the LTC1873 is in discontinuous or Burst Mode operation and the auxiliary output voltage drops, the FCB pin will trip and the LTC1873 will resume continuous operation regardless of the load on the main output. The FCB pin removes the requirement that power must be drawn from the inductor primary in order to extract power from the auxiliary windings ...
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... Minimize ringing at the SW node so that the discontinuous comparator leaves as little residual current in the inductor as possible when QB turns off. It helps to connect the SW pin of the LTC1873 as close to the drain possible snubber network can also be added from SW to PGND. REGULATION OVER COMPONENT TOLERANCE/ ...
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... Optimizing Loop Compensation Loop compensation has a fundamental impact on tran- sient recovery time, the time it takes the LTC1873 to recover after the output voltage has dropped due to output capacitor ESR. Optimizing loop compensation entails maintaining the highest possible loop bandwidth while ensuring loop stability ...
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... V CAP V OUT Selection section describes in detail how to design an optimized feedback loop, appropriate for most LTC1873 systems. Voltage Positioning If the load transients consist primarily of load steps from near zero load to full load and back, the transient response can be traded off against DC regulation performance by using a technique known as “ ...
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... This resistance can be a low value resistor, a length of PCB trace, or even the parasitic resistance of the inductor if an appropriate filter is used. If the LTC1873 senses the output voltage upstream from the resistance (Figure 16c), the output voltage will move with load as I • R ...
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... W U Changing the Output Voltage on the Fly The voltage at side 1 of the LTC1873 can be changed on the fly by changing the VID code while the output is enabled, but care must be taken to avoid tripping the overvoltage fault circuit. Stepping the voltage upwards abruptly is safe, ...
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... DWG # 05-08-1640 – 8 0.65 (0.0256) BSC 0.25 – 0.38 (0.010 – 0.015) LTC1873 10.07 – 10.33* (0.397 – 0.407 7.65 – 7.90 (0.301 – 0.311 1.73 – 1.99 (0.068 – 0.078) 0.05 – 0.21 (0.002 – 0.008) ...
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... F MBR0530T 470 BOOST1 1 F TG1 SW1 BG1 LTC1873 BOOST2 TG2 SW2 BG2 FAULT FAULT VID4:2 VID4:2 PGND COMMENTS SO-8 with Current Limit Constant Frequency, Standby 5V and 3.3V LDOs, 3.5V V 550kHz, 25MHz GBW Voltage Mode, V Adds 4-Bit Mobile Pentium II VID to All1.19V Referenced Switching Regulators Adds 5-Bit Desktop VID to All 0 ...