LTC2225 LINER [Linear Technology], LTC2225 Datasheet
LTC2225
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LTC2225 Summary of contents
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... The LTC 2225 is a 12-bit 10Msps, low power 3V A/D converter designed for digitizing high frequency, wide dynamic range signals. The LTC2225 is perfect for de- manding imaging and communications applications with AC performance that includes 71.3dB SNR and 90dB SFDR for signals well beyond the Nyquist frequency. ...
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... Analog Input Voltage (Note 3) ..... –0. Digital Input Voltage .................... –0. Digital Output Voltage ................ –0.3V to (OV Power Dissipation ............................................ 1500mW Operating Temperature Range LTC2225C ............................................... 0°C to 70°C LTC2225I .............................................–40°C to 85°C Storage Temperature Range ..................–65°C to 125° VERTER CHARACTERISTICS ...
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... Input 70MHz Input 5MHz Input 70MHz Input 5MHz Input 70MHz Input f = 4.3MHz 4.6MHz IN1 IN2 (Note 4) CONDITIONS OUT 2.7V < V < 3.4V DD –1mA < I < 1mA OUT LTC2225 MIN TYP MAX UNITS ±0.5V to ±1V ● V ● 1 1.5 1.9 V ● 0.5 1 µA ● –1 1 µ ...
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... LTC2225 U U DIGITAL I PUTS A D DIGITAL OUTPUTS full operating temperature range, otherwise specifications are at T SYMBOL PARAMETER LOGIC INPUTS (CLK, OE, SHDN) V High Level Input Voltage IH V Low Level Input Voltage IL I Input Current IN C Input Capacitance IN LOGIC OUTPUTS Hi-Z Output Capacitance ...
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... DD DD differential drive. without latchup. Note 9: Recommended operating conditions. with differential P-P Typical DNL, 2V Range 1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 1024 2048 3072 CODE LTC2225 MIN TYP MAX ● ● 500 ● 500 ● 500 ● 500 0 ● ...
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... LTC2225 W U TYPICAL PERFOR A CE CHARACTERISTICS 8192 Point FFT 70.1MHz, IN –1dB, 2V Range 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 FREQUENCY (MHz) 2225 G04 SNR vs Input Frequency, –1dB, 2V Range ...
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... V and turns the clock duty cycle stabilizer on. 2/3 V 2’s complement output format and turns the clock duty cycle stabilizer on. V format and turns the clock duty cycle stabilizer off. and DD LTC2225 vs Sample Rate, 5MHz Sine = 1.8V VDD ...
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... LTC2225 CTIO S SENSE (Pin 30): Reference Programming Pin. Connecting selects the internal reference and a ±0.5V SENSE selects the internal reference and a ±1V input range input range. An external reference greater than 0.5V and less than 1V applied to SENSE selects an input range of ± ...
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... RMS value of a full scale input signal )/V1) Input Bandwidth The input bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB for a full scale input signal. LTC2225 – – 2225 TD01 2225fa 9 ...
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... JITTER IN JITTER CONVERTER OPERATION As shown in Figure 1, the LTC2225 is a CMOS pipelined multistep converter. The converter has six pipelined ADC stages; a sampled analog input will result in a digitized value five cycles later (see the Timing Diagram section). For optimal AC performance the analog inputs should be driven differentially ...
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... Poor matching will result in higher even order harmonics, especially the second. Input Drive Circuits Figure 3 shows the LTC2225 being driven transformer with a center tapped secondary. The second- ary center tap is DC biased with V signal at its optimum DC level. Terminating on the trans- ...
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... Figure 5. Single-Ended Drive Reference Operation Figure 6 shows the LTC2225 reference circuitry consisting of a 1.5V bandgap reference, a difference amplifier and switching and control circuit. The internal voltage refer- ence can be configured for two pin selectable input ranges of 2V (±1V differential (±0.5V differential). Tying the SENSE pin to V selects the 2V range ...
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... A differential clock can also be used along with a low-jitter CMOS converter before the CLK pin (see Figure 8). The noise performance of the LTC2225 can depend on the clock signal quality as much as on the analog input. Any noise present on the clock signal will result in additional aperture jitter that will be RMS summed with the inherent ADC aperture jitter ...
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... As with all high speed/high resolution converters, the digital output loading can affect the performance. The digital outputs of the LTC2225 should drive a minimal capacitive load to avoid possible interaction between the digital outputs and sensitive input circuitry. The output should be buffered with a device such as an ALVCH16373 CMOS latch ...
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... Hi-Z state. Grounding and Bypassing The LTC2225 requires a printed circuit board with a clean, unbroken ground plane. A multilayer board with an inter- nal ground plane is recommended. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible ...
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... LTC2225 U U APPLICATIO S I FOR ATIO 2225fa ...
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... U U APPLICATIO S I FOR ATIO Silkscreen Top W U Inner Layer 2 GND LTC2225 Topside 2225fa 17 ...
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... LTC2225 U U APPLICATIO S I FOR ATIO Inner Layer 3 Power Silkscreen Bottom Bottomside 2225fa ...
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... UH Package 32-Lead Plastic QFN (5mm × 5mm) (Reference LTC DWG # 05-08-1693) 0.70 ±0.05 PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC 0.75 ± 0.05 0.00 – 0.05 3.45 ± 0.10 (4-SIDES) 0.200 REF LTC2225 BOTTOM VIEW—EXPOSED PAD PIN 1 NOTCH R = 0.30 TYP R = 0.115 OR 0.35 × 45° CHAMFER TYP 31 32 0.40 ± 0. (UH32) QFN 1004 0.25 ± ...
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... ADC, Lowest Noise LTC2208 16-Bit, 130Msps, 3.3V ADC, LVDS Outputs LTC2220-1 12-Bit, 185Msps, 3.3V ADC, LVDS Outputs LTC2224 12-Bit, 135Msps, 3.3V ADC, High IF Sampling LTC2225 12-Bit, 10Msps, 3V ADC, Lowest Power LTC2226 12-Bit, 25Msps, 3V ADC, Lowest Power LTC2227 12-Bit, 40Msps, 3V ADC, Lowest Power LTC2228 ...