LTC2231 Linear Technology, LTC2231 Datasheet
LTC2231
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LTC2231 Summary of contents
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... V DD 10-BIT CORRECTION OUTPUT PIPELINED LOGIC DRIVERS ADC CORE 22301 TA01 Electrical Specifications Subject to Change LTC2230/LTC2231 10-Bit,170Msps/ 135Msps ADCs U ® 2230 and LTC2231 are 170Msps/135Msps, sam- . RMS + – and ENC inputs may be driven differentially or SFDR vs Input Frequency • ...
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... Analog Input Voltage (Note 3) ..... –0. Digital Input Voltage .................... –0. Digital Output Voltage ............... –0.3V to (OV Power Dissipation ............................................ 1500mW Operating Temperature Range LTC2230C, LTC2231C ............................. 0°C to 70°C LTC2230I, LTC2231I ...........................–40°C to 85°C Storage Temperature Range ..................–65°C to 125° VERTER CHARACTERISTICS ...
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... Input (2V Range) 70MHz Input (1V Range) 70MHz Input (2V Range 138MHz, IN1 f = 140MHz IN2 LTC2230/LTC2231 MIN TYP ● < 3.5V ±0.5 to ±1 ● 1 1.6 – ● < V –1 DD ● – 0.15 80 775 LTC2230 LTC2231 MIN TYP MAX MIN TYP 59.5 59.5 61.2 61.2 59.5 59.5 60 61.1 60 61.1 59.4 59.4 61.0 61.0 59.0 59.0 60.6 60 ...
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... LTC2230/LTC2231 TER AL REFERE CE CHARACTERISTICS PARAMETER V Output Voltage CM V Output Tempco CM V Line Regulation CM V Output Resistance CM U DIGITAL I PUTS A D DIGITAL OUTPUTS full operating temperature range, otherwise specifications are at T SYMBOL PARAMETER + – ENCODE INPUTS (ENC , ENC ) V Differential Input Voltage ...
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... MAX 3.1 3.3 3.5 3.1 3.3 3 3.3 3.6 3 3.3 3.6 264 290 196 216 1050 1160 828 915 0.5 3.3 3.6 0.5 3.3 3.6 264 290 196 216 890 660 LTC2230 LTC2231 MIN TYP MAX MIN TYP MAX 1 170 1 135 2.8 2.94 500 3.5 3.7 500 2 2.94 500 2 3.7 500 2.8 2.94 500 3.5 3.7 500 2 2.94 500 2 3.7 500 1.3 2 ...
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... LTC2230: SNR vs Input Frequency, –1dB, 1V Range 500 600 0 100 200 300 INPUT FREQUENCY (MHz) 2230 G03 = 3.3V 170MHz (LTC2230) or 135MHz (LTC2231), DD SAMPLE + – /ENC = 2V sine wave, input range = 1V P-P = 5pF. LOAD LTC2230: Noise Histogram 140000 131059 120000 100000 80000 60000 40000 ...
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... G09 vs Sample Rate, OVDD LVDS OUTPUTS 3.3V DD CMOS OUTPUTS 1. 100 120 140 160 180 200 SAMPLE RATE (Msps) 2230 G12 LTC2230/LTC2231 LTC2230: SFDR (HD4+) vs Input Frequency, –1dB, 1V Range 400 500 0 100 200 ...
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... LTC2230/LTC2231 TYPICAL PERFOR A CE CHARACTERISTICS LTC2230: 8192 Point FFT 30MHz, –1dB, 2V Range IN 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 FREQUENCY (MHz) LTC2230: 8192 Point FFT 70MHz, –1dB, 1V Range IN 0 –10 –20 – ...
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... LTC2231: SNR vs Input Frequency, –1dB, 2V Range 200 300 400 100 INPUT FREQUENCY (MHz) LTC2231: SFDR (HD2 and HD3) vs Input Frequency, –1dB, 1V Range 100 200 300 400 INPUT FREQUENCY (MHz) DataSheet4U.com W ...
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... VDD 5MHz Sine Wave Input, –1dB 220 210 200 2V RANGE 190 180 170 160 150 120 140 160 SAMPLE RATE (Msps) 2231 G10 LTC2231: SFDR vs Input Level 70MHz, 2V Range IN 100 90 dBFS dBc –50 –40 –30 – ...
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... FREQUENCY (MHz) 2231 G20 LTC2230/LTC2231 LTC2231: 8192 Point FFT 70MHz, –1dB, 2V Range IN 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 – ...
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... LTC2230/LTC2231 CTIO S (CMOS Mode (Pins 1, 2): Positive Differential Analog Input. IN – A (Pins 3, 4): Negative Differential Analog Input. IN REFHA (Pins 5, 6): ADC High Reference. Bypass to Pins 7, 8 with 0.1µF ceramic chip capacitor, to Pins 11, 12 with a 2.2µF ceramic capacitor and to ground with 1µF ceramic capacitor ...
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... Encode Complement Input. Conversion starts on the negative edge. Bypass to ground with 0.1µF ceramic for single-ended ENCODE signal. DataSheet4U.com LTC2230/LTC2231 SHDN (Pin 19): Shutdown Mode Selection Pin. Connect- ing SHDN to GND and OE to GND results in normal operation with the outputs enabled. Connecting SHDN to ...
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... LTC2230/LTC2231 CTIO S SENSE (Pin 59): Reference Programming Pin. Connecting SENSE to V selects the internal reference and a ±0.5V CM input range. V selects the internal reference and a ±1V DD input range. An external reference greater than 0.5V and less than 1V applied to SENSE selects an input range of . ± ...
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... L – ENC + ENC – 6 DA0-DA9, OFA – 5 DB0-DB9, OFB t C CLOCKOUTB CLOCKOUTA LTC2230/LTC2231 – – – 1 22201 TD02 – – – 2 22201 TD03 – – – – ...
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... AC input. The signal to noise ratio due to the jitter alone will be: SNR CONVERTER OPERATION As shown in Figure 1, the LTC2230/LTC2231 is a CMOS pipelined multistep converter. The converter has five pipelined ADC stages; a sampled analog input will result in a digitized value five cycles later (see the Timing Diagram section) ...
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... SAMPLE/HOLD OPERATION AND INPUT DRIVE Sample/Hold Operation Figure 2 shows an equivalent circuit for the LTC2230/ LTC2231 CMOS differential sample-and-hold. The analog inputs are connected to the sampling capacitors (C through NMOS transistors. The capacitors shown at- tached to each input (C PARASITIC other capacitance associated with each input ...
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... Poor matching will result in higher even order harmonics, especially the second. Input Drive Circuits Figure 3 shows the LTC2230/LTC2231 being driven transformer with a center tapped secondary. The secondary center tap is DC biased with V ADC input signal at its optimum DC level. Figure 3 shows a 1:1 turns ratio transformer ...
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... A pins IN IN Figure 9 shows the LTC2230/LTC2231 reference circuitry consisting of a 1.6V bandgap reference, a difference amplifier and switching and control circuit. The internal voltage reference can be configured for two pin selectable input ranges of 2V (±1V differential (±0.5V differ- ential) ...
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... Each half cycle must have at least 2.8ns (LTC2230) or 3.5ns (LTC2231) for the ADC internal circuitry to have enough settling time for proper operation. Achieving a precise 50% duty cycle is easy with differential sinusoidal drive using a transformer or using symmetric differential logic such as PECL or LVDS ...
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... MODE pin should be connected to 1/3V or 2/3V DD The lower limit of the LTC2230/LTC2231 sample rate is determined by droop of the sample-and-hold circuits. The pipelined architecture of this ADC relies on storing analog signals on small valued capacitors. Junction leakage will discharge the capacitors. The specified minimum operat- ing frequency for the LTC2230/LTC2231 is 1Msps ...
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... D 3.5mA OGND Figure 13b. Digital Output in LVDS Mode Data Format The LTC2230/LTC2231 parallel digital output can be se- lected for offset binary or 2’s complement format. The format is selected with the MODE pin. Connecting MODE to GND or 1/3V selects straight binary output format. DD Connecting MODE to 2/3V ment output format ...
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... DD noise pickup. DataSheet4U.com HEAT TRANSFER Most of the heat generated by the LTC2230/LTC2231 is transferred from the die through the bottom-side exposed pad and package leads onto the printed circuit board. For good electrical and thermal performance, the exposed pad should be soldered to a large grounded pad on the PC board. ...
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... LTC2230/LTC2231 U U APPLICATIO S I FOR ATIO DataSheet4U.com DataSheet4U.com 22301p ...
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... U U APPLICATIO S I FOR ATIO Layer 1 Component Side DataSheet4U.com W U Silkscreen Top DataSheet4U.com LTC2230/LTC2231 Layer 2 GND Plane 22301p 25 ...
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... LTC2230/LTC2231 U U APPLICATIO S I FOR ATIO DataSheet4U.com Layer 3 Power Plane DataSheet4U.com Layer 4 Bottom Side 22301p ...
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... Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. LTC2230/LTC2231 NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION WNJR-5 2 ...
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... LTC2230/LTC2231 RELATED PARTS PART NUMBER DESCRIPTION LTC1747 12-Bit, 80Msps ADC LTC1748 14-Bit, 80Msps ADC LTC1749 12-Bit, 80Msps Wideband ADC LTC1750 14-Bit, 80Msps Wideband ADC LTC2220 12-Bit, 170Msps ADC LTC2221 12-Bit, 135Msps ADC LTC2222 12-Bit, 105Mspss ADC LT5514 Ultralow Distortion IF Amplifier/ADC Driver with Digitally Controlled Gain DataSheet4U ...