LTC2233 Linear Technology, LTC2233 Datasheet
LTC2233
Related parts for LTC2233
LTC2233 Summary of contents
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... LTC2233 are 105Msps/80Msps, sam- pling 10-bit A/D converters designed for digitizing high frequency, wide dynamic range signals. The LTC2232/ LTC2233 are perfect for demanding communications applications with AC performance that includes 61dB SNR and 75dB spurious free dynamic range for signals up to 200MHz ...
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... Analog Input Voltage (Note 3) ..... –0. Digital Input Voltage .................... –0. Digital Output Voltage ............... –0.3V to (OV Power Dissipation ............................................ 1500mW Operating Temperature Range LTC2232C, LTC2233C ............................. 0°C to 70°C LTC2232I, LTC2233I ...........................–40°C to 85°C Storage Temperature Range ..................–65°C to 125° VERTER CHARACTERISTICS ...
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... Input (2V Range) 70MHz Input (1V Range) 70MHz Input (2V Range 138MHz 140MHz IN1 IN2 LTC2232/LTC2233 www.DataSheet4U.com MIN TYP MAX ±0.5 to ±1 ● ● 1 1.6 1.9 ● 0.5 1.6 2.1 ● –1 ● –1 10 775 0 0.15 80 LTC2232 LTC2233 MIN TYP MAX MIN TYP MAX 59.8 59.9 60.4 61.3 60.4 61.3 59.8 59.8 61.2 61.3 59.8 59.8 61.2 61.2 59.6 59.7 61.1 61 ...
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... LTC2232/LTC2233 TER AL REFERE CE CHARACTERISTICS PARAMETER V Output Voltage CM V Output Tempco CM V Line Regulation CM V Output Resistance DIGITAL I PUTS A D DIGITAL OUTPUTS full operating temperature range, otherwise specifications are at T SYMBOL PARAMETER + – ENCODE INPUTS (ENC , ENC ) V Differential Input Voltage ...
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... Note 3: When these pin voltages are taken below GND or above V be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above V DD Note 3.3V 105MHz (LTC2232) or 80MHz (LTC2233), DD SAMPLE + – differential ENC /ENC ...
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... LTC2232/LTC2233 W U TYPICAL PERFOR A CE CHARACTERISTICS LTC2232: INL, 2V Range 1.0 0.8 0.6 0.4 0.2 0 – 0.2 – 0.4 – 0.6 – 0.8 – 1.0 0 256 512 768 1024 OUTPUT CODE 2232 G01 LTC2232: SNR vs Input Frequency, –1dB, 1V Range 100 200 300 400 500 600 INPUT FREQUENCY (MHz) ...
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... FREQUENCY (MHz) 2232 G16 LTC2232/LTC2233 www.DataSheet4U.com LTC2232 Sample Rate, OVDD 5MHz Sine Wave Input, –1dB 1. 100 120 ...
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... LTC2232/LTC2233 W U TYPICAL PERFOR A CE CHARACTERISTICS LTC2232: 8192 Point FFT 70MHz, –1dB, 1V Range IN 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 FREQUENCY (MHz) 2232 G19 LTC2232: 8192 Point FFT 250MHz, –1dB, 2V Range ...
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... INPUT FREQUENCY (MHz) 2232 G03 LTC2233: SFDR (HD2 and HD3) vs Input Frequency, –1dB, 1V Range 100 200 300 400 500 600 INPUT FREQUENCY (MHz) 2232 G06 ...
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... Sample Rate, 1V Range 30MHz, –1dB IN 85 SFDR SNR 100 SAMPLE RATE (Msps) 2233 G10 LTC2233: SFDR vs Input Level 70MHz, 2V Range dBFS 70 60 dBc –50 –30 –20 –10 0 –40 INPUT LEVEL (dBFS) ...
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... FREQUENCY (MHz) 2233 G23 LTC2233: 8192 Point 2-Tone FFT 138MHz and 140MHz, –7dB IN Each, 1V Range 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 ...
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... LTC2232/LTC2233 CTIO (Pin 1): Positive Differential Analog Input – (Pin 2): Negative Differential Analog Input. IN REFHA (Pins 3, 4): ADC High Reference. Bypass to Pins 5, 6 with 0.1µF ceramic chip capacitor, to Pins 9, 10 with a 2.2µF ceramic capacitor and to ground with a 1µF ceramic capacitor ...
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... Timing Diagram – – – LTC2232/LTC2233 www.DataSheet4U.com FOURTH PIPELINED FIFTH PIPELINED ADC STAGE ADC STAGE SHIFT REGISTER AND CORRECTION • CONTROL OUTPUT • LOGIC DRIVERS • 22323 F01 OGND SHDN ...
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... LTC2232/LTC2233 U U APPLICATIO S I FOR ATIO DYNAMIC PERFORMANCE Signal-to-Noise Plus Distortion Ratio The signal-to-noise plus distortion ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the ADC output. The output is band limited to frequencies above DC to below half the sampling frequency ...
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... U U APPLICATIO S I FOR ATIO CONVERTER OPERATION As shown in Figure 1, the LTC2232/LTC2233 is a CMOS pipelined multistep converter. The converter has five pipelined ADC stages; a sampled analog input will result in a digitized value five cycles later (see the Timing Diagram section). For optimal AC performance the analog inputs should be driven differentially ...
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... Poor matching will result in higher even order harmonics, especially the second. Input Drive Circuits Figure 3 shows the LTC2232/LTC2233 being driven transformer with a center tapped secondary. The secondary center tap is DC biased with V ADC input signal at its optimum DC level. Terminating on ...
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... Figure 8 the series inductors are impedance matching elements that maximize the ADC bandwidth. Reference Operation Figure 9 shows the LTC2232/LTC2233 reference circuitry consisting of a 1.6V bandgap reference, a difference amplifier and switching and control circuit. The internal voltage reference can be configured for two pin selectable ...
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... A IN LTC2232/ LTC2233 12pF 25Ω – 0.1µF Figure 5. Single-Ended Drive V CM 2.2µF 0.1µ LTC2232/ LTC2233 0.1µF 25Ω T1 0.1µF 25Ω – MA/COM ETC1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE Frequencies Between 250MHz and 500MHz 22323 F05 22323 F07 22323fa ...
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... V CM 2.2µ LTC2232/ LTC2233 2pF TIE TIE – RANGE = 2 • 0.5V < V 22323 F08 22323 F10 LTC2232/LTC2233 www.DataSheet4U.com LTC2232/LTC2233 4Ω V 1.6V BANDGAP CM 1.6V REFERENCE 2.2µF 1V 0.5V RANGE DETECT AND CONTROL FOR 2V RANGE; SENSE FOR 1V RANGE; FOR SENSE REFLB < 1V BUFFER SENSE INTERNAL ADC 0.1µ ...
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... For the ADC to operate properly, the encode signal should have a 50% (±5%) duty cycle. Each half cycle must have at least 4.5ns (LTC2232) or 5.9ns (LTC2233) for the ADC internal cir- cuitry to have enough settling time for proper operation. DD ...
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... U U APPLICATIO S I FOR ATIO The lower limit of the LTC2232/LTC2233 sample rate is determined by droop of the sample-and-hold circuits. The pipelined architecture of this ADC relies on storing analog signals on small valued capacitors. Junction leakage will discharge the capacitors. The specified minimum operat- ing frequency for the LTC2232/LTC2233 is 1Msps. ...
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... LTC2232/LTC2233 U U APPLICATIO S I FOR ATIO Data Format The LTC2232/LTC2233 parallel digital output can be se- lected for offset binary or 2’s complement format. The format is selected with the MODE pin. Connecting MODE to GND or 1/3V selects offset binary output format. DD Connecting MODE to 2/ ...
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... HEAT TRANSFER Most of the heat generated by the LTC2232/LTC2233 is transferred from the die through the bottom-side exposed pad and package leads onto the printed circuit board. For good electrical and thermal performance, the exposed pad should be soldered to a large grounded pad on the PC board ...
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... LTC2232/LTC2233 U U APPLICATIO S I FOR ATIO Clock Sources for Undersampling Undersampling raises the bar on the clock source and the higher the input frequency, the greater the sensitivity to clock jitter or phase noise. A clock source that degrades SNR of a full-scale signal by 1dB at 70MHz will degrade SNR by 3dB at 140MHz, and 4 ...
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... PWR GND U1 R1 LTC2222 24.9Ω 12pF LTC2223 24.9Ω 12pF LTC2232 24.9Ω 12pF LTC2233 24.9Ω 12pF LTC2222 12.4Ω 8.2pF LTC2223 12.4Ω 8.2pF LTC2232 12.4Ω 8.2pF LTC2233 12.4Ω 8.2pF ...
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... LTC2232/LTC2233 U U APPLICATIO S I FOR ATIO Layer 1 Component Side Layer 3 Power Plane Silkscreen Top www.DataSheet4U.com Layer 2 GND Plane Layer 4 Bottom Side 22323fa ...
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... Plastic QFN (7mm × 7mm) (Reference LTC DWG # 05-08-1704) 0.70 ±0.05 5.15 ±0.05 6.10 ±0.05 7.50 ±0.05 (4 SIDES) PACKAGE OUTLINE 0.25 ±0.05 0.75 ± 0.05 5.15 ± 0.10 (4-SIDES) 0.200 REF 0.00 – 0.05 LTC2232/LTC2233 www.DataSheet4U.com R = 0.115 TYP 47 48 PIN 1 CHAMFER (UK48) QFN 0903 0.25 ± 0.05 0.50 BSC BOTTOM VIEW—EXPOSED PAD 0.40 ± 0.10 ...
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... ADC, High IF Sampling LTC2223 12-Bit, 80Msps, 3.3V ADC, High IF Sampling LTC2224 12-Bit, 135Msps, 3.3V ADC, High IF Sampling LTC2232 10-Bit, 105Msps, 3.3V ADC, High IF Sampling LTC2233 10-Bit, 80Msps, 3.3V ADC, High IF Sampling LTC2234 10-Bit, 135Msps, 3.3V ADC, High IF Sampling LTC2255 14-Bit, 125Msps, 3V ADC, Lowest Power LTC2284 ...