LTC2410 Linear Technology, LTC2410 Datasheet
LTC2410
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LTC2410 Summary of contents
Page 1
... INL and 0.16ppm RMS noise. It uses delta-sigma technology and provides single cycle settling time for multiplexed applications. Through a single pin, the LTC2410 can be configured for better than 110dB input differential mode rejection at 50Hz or 60Hz 2 can be driven by an external oscillator for a user defined rejection frequency ...
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... GND .................................... – 0. Digital Input Voltage to GND ........ – 0. Digital Output Voltage to GND ..... – 0. Operating Temperature Range LTC2410C ............................................... LTC2410I ............................................ – Storage Temperature Range ................. – 150 C Lead Temperature (Soldering, 10 sec).................. 300 C ELECTRICAL CHARACTERISTICS temperature range, otherwise specifications are at T ...
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... A CONDITIONS + Voltage – Voltage + Voltage – Voltage + GND CC – GND REF = 5V CC – REF = GND CC LTC2410 MIN TYP MAX UNITS 130 140 dB 140 dB 140 dB 110 140 dB 110 140 dB 130 140 dB 100 dB 110 dB 110 dB MIN TYP MAX UNITS GND – ...
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... LTC2410 U U DIGITAL I PUTS A D DIGITAL OUTPUTS operating temperature range, otherwise specifications are at T SYMBOL PARAMETER V High Level Input Voltage IH CS Low Level Input Voltage IL CS High Level Input Voltage IH SCK V Low Level Input Voltage IL SCK I Digital Input Current ...
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... Note 11: The external oscillator is connected to the F oscillator frequency, f Note 12: The converter uses the internal oscillator Note 13: The output noise includes the contribution of the internal calibration operations. = 153600Hz 2% Note 14: Guaranteed by design and test correlation. LTC2410 MIN TYP MAX 2.56 2000 0.25 390 0.25 390 130 ...
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... LTC2410 CTIO S GND (Pins 10, 15, 16): Ground. Multiple ground pins internally connected for optimum ground current flow and V decoupling. Connect each one of CC these pins to a ground plane through a low impedance connection. V (Pin 2): Positive Supply Voltage. Bypass to GND ...
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... U APPLICATIO S I FOR ATIO CONVERTER OPERATION Converter Operation Cycle The LTC2410 is a low power, delta-sigma analog-to- digital converter with an easy to use 3-wire serial interface. Its operation is made up of three states. The converter operating cycle begins with the conversion, followed by the low power sleep state and ends with the data output (see Figure 1) ...
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... The POR signal clears all internal registers. Following the POR signal, the LTC2410 starts a normal conversion cycle and follows the succession of states described above. The first conversion result following POR is accurate within the specifications of the device if the power supply voltage is restored within the operating range (2 ...
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... V This error has a very strong temperature dependency. Output Data Format The LTC2410 serial output data stream is 32 bits long. The first 3 bits represent status information indicating the sign and conversion state. The next 24 bits are the conversion result, MSB first ...
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... V IN **The differential reference voltage Frequency Rejection Selection (F The LTC2410 internal oscillator provides better than 110dB normal mode rejection at the line frequency and all its harmonics for 50Hz 2% or 60Hz 2%. For 60Hz rejec- tion – pins is maintained ...
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... U U APPLICATIO S I FOR ATIO synchronized with an outside source, the LTC2410 can operate with an external conversion clock. The converter automatically detects the presence of an external clock signal at the F pin and turns off the internal oscillator. The O frequency f of the external signal must be at least EOSC 2560Hz (1Hz notch frequency detected ...
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... SDO pin on the falling edge of the serial clock. In the Internal SCK mode of operation, the SCK pin is an output and the LTC2410 creates its own serial clock by dividing the internal conversion clock the External SCK mode of operation, the SCK pin is used as input. The ...
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... GND BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 26 EOC SIG MSB DATA OUTPUT Figure 5. External Serial Clock, Single Cycle Operation LTC2410 exceeds 2.2V. The level 50Hz REJECTION = EXTERNAL OSCILLATOR = 60Hz REJECTION 3-WIRE SPI INTERFACE TEST EOC BIT 5 BIT 0 LSB ...
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... In order to select the internal serial clock timing mode, the serial clock pin (SCK) must be floating (Hi-Z) or pulled HIGH prior to the falling edge of CS. The device will not 2. LTC2410 3 + REFERENCE 13 REF SCK VOLTAGE 4 – 0. REF ...
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... REF 6 11 – 10, 15, 16 GND BIT 30 BIT 29 BIT 28 BIT 27 BIT 26 SIG MSB DATA OUTPUT Figure 8. Internal Serial Clock, Single Cycle Operation LTC2410 50Hz REJECTION = EXTERNAL OSCILLATOR = 60Hz REJECTION 3-WIRE SPI INTERFACE BIT 26 BIT 5 BIT 0 LSB ...
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... SCK pin or by never pulling CS HIGH when SCK is LOW. Whenever SCK is LOW, the LTC2410’s internal pull-up at pin SCK is disabled. Normally, SCK is not externally driven if the device is in the internal SCK timing mode. However, certain applications may require an external driver on SCK ...
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... TO 0.5V REF REF 6 11 – 10, 15, 16 GND BIT 29 BIT 28 BIT 27 BIT 26 SIG MSB DATA OUTPUT Figure 10. Internal Serial Clock, Continuous Operation LTC2410 50Hz REJECTION = EXTERNAL OSCILLATOR = 60Hz REJECTION 3-WIRE SPI INTERFACE BIT 5 BIT 0 LSB 24 CONVERSION 17 2410 F10 ...
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... PCB surface. The internal serial clock mode is selected every time the voltage on the CS pin crosses an internal threshold volt- age. An internal weak pull-up at the SCK pin is active while 2. LTC2410 3 + REFERENCE 13 REF SCK VOLTAGE 4 – REF 0. ...
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... CMOS levels [V (V – 0.4V)]. CC During the conversion period, the undershoot and/or overshoot of a fast digital signal connected to the LTC2410 pins may severely disturb the analog to digital conversion process. Undershoot and overshoot can occur because of 10000 100000 the impedance mismatch at the converter pin when the ...
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... F the differential input and reference connections. Driving the Input and Reference The input and reference pins of the LTC2410 converter are directly connected to a network of sampling capacitors. Depending upon the relation between the differential input voltage and the differential reference voltage, these ca- pacitors are switching between these four pins transfering small amounts of charge in the process ...
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... EOSC The effect of this input dynamic current can be analyzed using the test circuit of Figure 16. The C includes the LTC2410 pin capacitance (5pF typical) plus the capacitance of the test fixture used to obtain the results shown in Figures 17 and 18. A careful implementation can bring the total input capacitance (C ...
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... C are unavoidably present as parasitics IN of input multiplexers, wires, connectors or sensors, the LTC2410 can maintain its exceptional accuracy while operating with relative large values of source resistance as shown in Figures 17 and 18. These measured results may be slightly different from the first order approximation ...
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... V typical and 1 V maximum offset voltage 0 Reference Current In a similar fashion, the LTC2410 samples the differential reference pins REF charge to and from the external driving circuits thus producing a dynamic reference current. This current does not change the converter offset but it may degrade the gain ...
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... LTC2410 U U APPLICATIO S I FOR ATIO + – REF and REF pins and external capacitance C nected to these pins are shown in Figures 22, 23, 24 and 25. In addition to this gain error, the converter INL perfor- mance is degraded by the reference source impedance. When F = LOW (internal oscillator and 60Hz notch), every ...
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... A 100 source resistance will create a 0.05 V typical and 0.5 V maxi- mum full-scale error. Output Data Rate When using its internal oscillator, the LTC2410 can pro- duce up to 7.5 readings per second with a notch frequency of 60Hz (F = LOW) and 6.25 readings per second with a ...
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... Due to the complex filtering and calibration algorithms utilized, the converter input bandwidth is not modeled very accurately by a first order filter with the pole located at the 3dB frequency. When the internal oscillator is used, the shape of the LTC2410 input bandwidth is shown in Fig- ure 35 for F = LOW and F = HIGH. When an external ...
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... REF INCM 10 –0.5V • V < V < 0.5 • V REF IN REF F = EXTERNAL OSCILLATOR 100 OUTPUT DATA RATE (READINGS/SEC) 1LSB) vs Output Data Rate and Reference Voltage MAX LTC2410 22 RESOLUTION = LOG (V /INL ) 2 REF MAX ...
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... LTC2410 operating with an internal oscillator and a 50Hz notch setting are shown in Figure 41 superimposed over the theoretical calculated curve result of these remarkable normal mode specifica- tions, minimal (if any) antialias filtering is required in front of the LTC2410. If passive RC components are placed The S = 256 • ...
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... F38 MEASURED DATA CALCULATED DATA 105 120 135 150 165 180 195 210 225 240 INPUT FREQUENCY (Hz) MEASURED DATA CALCULATED DATA INPUT FREQUENCY (Hz) LTC2410 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 250f ...
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... In Figure 42, the LTC2410 uses the internal oscillator with the notch set at 60Hz (F and in Figure 43 it uses the internal oscillator with the ...
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... To prevent the converters from autostarting a new con- version at the end of data output read fewer SCK clock signals are applied to the LTC2410 instead of 32 (the 32nd falling edge would start a conversion). The exact timing and frequency for the SCK signal is not critical since it is only shifting out the data. In this case, two LTC2410’ ...
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... LTC2400 family is of great benefit. For those applications that cannot be fulfilled by the LTC2410 alone, compensating for error in external ampli- fication can be done effectively due to the “no latency” feature of the LTC2410. No latency operation allows samples of the amplifier offset and gain to be interleaved with weighing measurements ...
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... APPLICATIO S I FOR ATIO techniques is used to produce a precision divide operation on the reference signal. Another option is the use of a reference within the 5V input range of the LTC2410 and developing excitation via fixed gain, or LTC1043 based voltage multiplication, along with remote feedback in the excitation amplifiers, as shown in Figures 34 and 35. ...
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... For single variable element bridges, the nonlinearity of the half bridge output can be eliminated completely; if the refer- ence arm of the bridge is used as the reference to the ADC, as shown in Figure 49. The LTC2410 can accept inputs up to 1/2 V REF least 2x the highest value of the variable resistor. ...
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... 175 6 LTC1050S8 + 2 – 4.98k 46.4k 46.4k 4.99k + 175 LTC2410 0 REF 4 – REF 20k LTC2410 20k 6 – IN GND 10, 15, 16 2410 F48 35 ...
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... Figure 50. Remote Half Bridge Sensing with Noise Suppression on Reference Figure 53 shows the use of an LTC2410 with a differential multiplexer. This is an inexpensive multiplexer that will contribute some error due to leakage if used directly with the output from the bridge resistors are inserted as a protection mechanism from overvoltage ...
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... F FILM 12 200 14 –10V LTC2410 10V LT1236 0 0 LTC2410 3 + REF 4 – REF – IN GND 10, 15 *FLYING CAPACITORS ARE 1 F FILM (MKP OR EQUIVALENT SEE LTC1043 DATA SHEET FOR DETAILS ON UNUSED HALF OF U1 ...
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... LT1236 0 LTC2410 3 + REF 4 – REF – RN1 GND 10k 10, 15, 16 RN1 IS CADDOCK T914 10K-010-02 2410 F52 REF – REF LTC2410 + IN – IN GND 2410 F53 ...
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... SS high. This places the LTC2410’s serial interface in a high impedance state and initiates another conversion. Figure 54. Connecting the LTC2410 to a 68HC11 MCU Using the SPI Serial Interface The performance of the LTC2410 can be verified using the demonstration board DC291A, see Figure 56 for the schematic. This circuit uses the computer’ ...
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... This memory location holds the LTC2410's bits DIN2 EQU $01 This memory location holds the LTC2410's bits DIN3 EQU $02 This memory location holds the LTC2410's bits DIN4 EQU $03 This memory location holds the LTC2410's bits ********************** * Start GETDATA Routine * ...
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... PORTD,Y %00100000 This sets the SS* output bit to a logic high, * de-selecting the LTC2410 PULA Restore the A register PULY Restore the Y register PULX Restore the X register RTS Figure 55. This is an Example of 68HC11 Code That Captures the LTC2410’s Conversion Results Over the SPI Serial Interface Shown in Figure 54 LTC2410 41 ...
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... REF – REF SCK SDO – GND IN 5 LTC2410CGN 15 GND 10 GND GND GND GND GND Figure 56. 24-Bit A/D Demo Board Schematic Figure 57. Display Graphic D1 BAV74LT1 OUT IN GND + C4 4 100 F ...
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... BSC W LTC2410 0.189 – 0.196* (4.801 – 4.978) 0.009 (0.229 0.229 – 0.244 0.150 – 0.157** (5.817 – 6.198) (3.810 – ...
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... LTC2410 U W PCB LAYOUT A D FIL RELATED PARTS PART NUMBER DESCRIPTION LT1019 Precision Bandgap Reference, 2.5V, 5V LT1025 Micropower Therocouple Cold Junction Compensator LTC1043 Dual Precision Instrumentation Switched Capacitor Building Block LTC1050 Precision Chopper Stabilized Op Amp LT1236A-5 Precision Bandgap Reference, 5V LT1460 Micropower Series Reference ...