M25P40-VMN6T NUMONYX, M25P40-VMN6T Datasheet
M25P40-VMN6T
Specifications of M25P40-VMN6T
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M25P40-VMN6T Summary of contents
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... JEDEC Standard two-Byte Signature (2013h) – RES Instruction, One-Byte, Signature (12h), for backward compatibility Packages – ECOPACK® (RoHS compliant) June 2006 4 Mbit, low voltage, Serial Flash memory with 50MHz SPI bus interface Rev 10 M25P40 SO8 (MN) 150 mil width VFQFPN8 (MP) (MLP8) 1/51 www.st.com 1 ...
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... Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.1 Write Enable (WREN 6.2 Write Disable (WRDI 6.3 Read Identification (RDID 6.4 Read Status Register (RDSR 6.4.1 6.4.2 6.4.3 6.4.4 6.5 Write Status Register (WRSR 2/51 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 BP2, BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 M25P40 ...
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... M25P40 6.6 Read Data Bytes (READ 6.7 Read Data Bytes at Higher Speed (FAST_READ 6.8 Page Program (PP 6.9 Sector Erase (SE 6.10 Bulk Erase (BE 6.11 Deep Power-down (DP 6.12 Release from Deep Power-down and Read Electronic Signature (RES Power-up and Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9 Maximum rating ...
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... Table 21. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 22. VFQFPN8 (MLP8) 8-lead Very thin Fine Pitch Quad Flat Package No lead, 6x5mm, Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 23. Ordering Information Scheme Table 24. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4/51 M25P40 ...
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... M25P40 List of figures Figure 1. Logic Diagram Figure 2. SO and VFQFPN Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. Bus Master and memory devices on the SPI Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 4. SPI Modes Supported Figure 5. Hold Condition Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 6. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 7. Write Enable (WREN) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 8. Write Disable (WRDI) Instruction Sequence Figure 9 ...
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... Summary description 1 Summary description The M25P40 Mbit (512K x 8) Serial Flash Memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus. The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction. The memory is organized as 8 sectors, each containing 256 pages. Each page is 256 bytes wide ...
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... Figure 2. SO and VFQFPN Connections 1. There is an exposed die paddle on the underside of the MLP8 package. This is pulled, internally and must not be allowed to be connected to any other voltage or signal line on the PCB. 2. See Section 11: Package mechanical Table 1. Signal Names HOLD M25P40 HOLD AI04091B for package dimensions, and how to identify pin-1 ...
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... To start the Hold condition, the device must be selected, with Chip Select (S) driven Low. 2.6 Write Protect (W) The main purpose of this input signal is to freeze the size of the area of memory that is protected against program or erase instructions (as specified by the values in the BP2, BP1 and BP0 bits of the Status Register). 8/51 M25P40 ...
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... M25P40 3 SPI modes These devices can be driven by a microcontroller with its SPI peripheral running in either of the two following modes: CPOL=0, CPHA=0 CPOL=1, CPHA=1 For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data is available from the falling edge of Serial Clock (C). ...
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... SPI modes Figure 4. SPI Modes Supported CPOL CPHA 10/51 MSB M25P40 MSB AI01438B ...
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... M25P40 4 Operating features 4.1 Page Programming To program one data byte, two instructions are required: Write Enable (WREN), which is one byte, and a Page Program (PP) sequence, which consists of four bytes plus data. This is followed by the internal Program cycle (of duration t To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be programmed at a time (changing bits from 1 to 0), provided that they lie in consecutive addresses on the same page of memory ...
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... The environments where non-volatile memory devices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the M25P40 features the following data protection mechanisms: Power On Reset and an internal timer (t changes while the power supply is outside the operating specification. ...
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... M25P40 Table 2. Protected Area Sizes Status Register Content BP2 BP1 BP0 Bit Bit Bit The device is ready to accept a Bulk Erase instruction if, and only if, all Block Protect (BP2, BP1, BP0) are 0. 4.7 Hold Condition The Hold (HOLD) signal is used to pause any serial communications with the device without resetting the clocking sequence ...
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... Operating features Figure 5. Hold Condition Activation C HOLD 14/51 Hold Condition (standard use) M25P40 Hold Condition (non-standard use) AI02029D ...
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... M25P40 5 Memory organization The memory is organized as: 524,288 bytes (8 bits each) 8 sectors (512 Kbits, 65536 bytes each) 2048 pages (256 bytes each). Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector or Bulk Erasable (bits are erased from but not Page Erasable. ...
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... Memory organization Figure 6. Block Diagram HOLD W Control Logic Address Register and Counter 16/51 High Voltage Generator I/O Shift Register 256 Byte Data Buffer 00000h 256 Bytes (Page Size) X Decoder M25P40 Status Register 7FFFFh Size of the read-only memory area 000FFh AI04986 ...
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... M25P40 6 Instructions All instructions, addresses and data are shifted in and out of the device, most significant bit first. Serial Data Input (D) is sampled on the first rising edge of Serial Clock (C) after Chip Select (S) is driven Low. Then, the one-byte instruction code must be shifted in to the device, most significant bit first, on Serial Data Input (D), each bit being latched on the rising edges of Serial Clock (C) ...
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... Write Enable Latch (WEL) bit Instruction D High Impedance Q Address Dummy Code Bytes Bytes 06h 0 0 04h 0 0 9Fh 0 0 05h 0 0 01h 0 0 03h 3 0 0Bh 3 1 02h 3 0 D8h 3 0 C7h 0 0 B9h ABh AI02281E M25P40 Data Bytes 256 ...
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... M25P40 6.2 Write Disable (WRDI) The Write Disable (WRDI) instruction The Write Disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the instruction code, and then driving Chip Select (S) High. The Write Enable Latch (WEL) bit is reset under the following conditions: ...
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... Table 5. Read Identification (RDID) Data-Out Sequence Manufacturer Identification 20h Figure 9. Read Identification (RDID) Instruction Sequence and Data-Out Sequence High Impedance Q 20/51 Figure 9. Memory Type 20h Instruction Manufacturer Identification MSB M25P40 Device Identification Memory Capacity 13h Device Identification MSB AI06809b ...
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... M25P40 6.4 Read Status Register (RDSR) The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status Register may be read at any time, even while a Program, Erase or Write Status Register cycle is in progress. When one of these cycles is in progress recommended to check the Write In Progress (WIP) bit before sending a new instruction to the device ...
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... Instructions Figure 10. Read Status Register (RDSR) Instruction Sequence and Data-Out Sequence High Impedance Q 22/ Instruction Status Register Out MSB Status Register Out MSB M25P40 7 AI02031E ...
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... M25P40 6.5 Write Status Register (WRSR) The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded and executed, the device sets the Write Enable Latch (WEL) ...
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... Memory Content (1) Protected Area Unprotected Area Protected against Ready to accept Page Page Program, Program and Sector Sector Erase and Erase instructions Bulk Erase Protected against Ready to accept Page Page Program, Program and Sector Sector Erase and Erase instructions Bulk Erase Table 7. M25P40 (1) ...
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... M25P40 6.6 Read Data Bytes (READ) The device is first selected by driving Chip Select (S) Low. The instruction code for the Read Data Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that ...
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... Figure 13. Read Data Bytes at Higher Speed (FAST_READ) Instruction Sequence and Data-Out Sequence Address bits A23 to A19 are Don’t Care. 26/51 Figure 13 Instruction 24 BIT ADDRESS High Impedance Dummy Byte DATA OUT MSB , during the falling edge of Serial Clock (C DATA OUT MSB M25P40 MSB AI04006 ...
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... M25P40 6.8 Page Program (PP) The Page Program (PP) instruction allows bytes to be programmed in the memory (changing bits from 1 to 0). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). ...
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... Instructions Figure 14. Page Program (PP) Instruction Sequence MSB 1. Address bits A23 to A19 are Don’t Care. 28/ Instruction 24-Bit Address MSB Data Byte 2 Data Byte MSB Data Byte MSB Data Byte 256 MSB M25P40 AI04082B ...
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... M25P40 6.9 Sector Erase (SE) The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL) ...
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... Write Enable Latch (WEL) bit is reset. The Bulk Erase (BE) instruction is executed only if all Block Protect (BP2, BP1, BP0) bits are 0. The Bulk Erase (BE) instruction is ignored if one, or more, sectors are protected. Figure 16. Bulk Erase (BE) Instruction Sequence 30/51 Figure 16 Instruction initiated. While the AI03752D M25P40 ...
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... M25P40 6.11 Deep Power-down (DP) Executing the Deep Power-down (DP) instruction is the only way to put the device in the lowest consumption mode (the Deep Power-down mode). It can also be used as an extra software protection mechanism, while the device is not in active use, since in this mode, the device ignores all Write, Program and Erase instructions ...
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... Executing this instruction takes the device out of the Deep Power-down mode. The instruction can also be used to read, on Serial Data Output (Q), the 8-bit Electronic Signature, whose value for the M25P40 is 12h. Except while an Erase, Program or Write Status Register cycle is in progress, the Release ...
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... Figure 18. Release from Deep Power-down and Read Electronic Signature (RES) Instruction Sequence and Data-Out Sequence Instruction D High Impedance Q 1. The value of the 8-bit Electronic Signature, for the M25P40, is 12h. Figure 19. Release from Deep Power-down (RES) Instruction Sequence High Impedance Dummy Bytes ...
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... Power On Reset CC , all operations are disabled and the device does not respond WI VSL – all operations are disabled, and WI threshold. However, the WI is still below V CC (min), the device can be CC delay is not yet fully elapsed. M25P40 is less CC (min). CC supply. CC ...
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... M25P40 Figure 20. Power-up Timing (max (min) Reset State of the Device V WI Table 8. Power-Up Timing and VWI Threshold Symbol ( (min low VSL CC (1) t Time delay to Write instruction PUW Write Inhibit Voltage (Device grade 6) ( Write Inhibit Voltage (Device grade 3) 1. These parameters are characterized only. ...
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... Storage Temperature STG V Input and Output Voltage (with respect to Ground Supply Voltage CC V Electrostatic Discharge Voltage (Human Body model) ESD 1. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 , R2=500 ). 36/51 Parameter (1) M25P40 Min. Max. Unit –65 150 °C –0.6 4.0 V –0.6 4.0 V –2000 2000 ...
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... M25P40 10 DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the Measurement Conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters ...
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... IH V Output Low Voltage OL V Output High Voltage OH 38/51 Test Condition (in addition to Parameter those 0.1V 40MHz and 50MHz open C = 0.1V 20MHz open Min. Table 10 0.9 0.9 –0.5 0.3V 0. 1.6mA = –100 A V –0.2 CC M25P40 Max. Unit ± 2 µA ± 2 µA 50 µA 10 µ +0 0 ...
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... M25P40 Table 14. DC Characteristics (Device Grade 3) Symbol I Input Leakage Current LI I Output Leakage Current LO I Standby Current CC1 I Deep Power-down Current CC2 I Operating Current (READ) CC3 I Operating Current (PP) CC4 I Operating Current (WRSR) CC5 I Operating Current (SE) CC6 I Operating Current (BE) CC7 V Input Low Voltage ...
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... Sector Erase Cycle Time Bulk Erase Cycle Time Parameter Input Levels 0.8V CC 0.2V CC Table 10 and Table 17 (1) (2) Min. Typ. Max 1.5 0.4+ n*1.1/256 1 4.5 10 Min. Max 0. 0. Input and Output Timing Reference Levels 0.7V CC 0.5V CC 0.3V CC AI07455 M25P40 (2) Unit Unit ...
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... M25P40 Table 18. AC Characteristics (25MHz Operation, Device Grade Symbol Alt ( CLH ( CLL (2) t CLCH (2) t CHCL t t SLCH CSS t CHSL t t DVCH DSU t t CHDX DH t CHSH t SHCH t t SHSL CSH ( SHQZ DIS t t CLQV CLQX HO t HLCH t CHHH t HHCH t CHHL ...
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... It is 30µs in devices produced with the “X” process technology. Details of how to find the process letter on the device marking are given in the Application note AN1995. 42/51 Test conditions specified in Table 10 Parameter (4) (peak to peak) (4) (peak to peak) C M25P40 (1) and Table 17 Min. Typ. Max. Unit D.C. 40 MHz D ...
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... M25P40 Table 20. AC Characteristics (50MHz Operation, Device Grade 6) 50MHz available only in products with Process Technology code X Symbol Alt ( CLH ( CLL (3) t CLCH (3) t CHCL t t SLCH CSS t CHSL t t DVCH DSU t t CHDX DH t CHSH t SHCH t t SHSL CSH ( SHQZ DIS ...
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... DC and AC parameters Figure 22. Serial Input Timing S tCHSL C tDVCH D Q Figure 23. Write Protect Setup and Hold Timing during WRSR when SRWD=1 W tWHSL 44/51 tSLCH tCHDX MSB IN High Impedance High Impedance tSHSL tCHSH tSHCH tCHCL tCLCH LSB IN tSHWL M25P40 AI07439 ...
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... M25P40 Figure 24. Hold Timing HOLD Figure 25. Output Timing S C tCLQV tCLQX tCLQX Q ADDR. D LSB IN tHLCH tCHHL tCHHH tHLQZ tCH tCLQV tQLQH tQHQL DC and AC parameters tHHCH tHHQX AI02032 tCL tSHQZ LSB OUT AI01449e 45/51 ...
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... GAUGE PLANE SO-A inches Typ Min 0.004 0.049 0.011 0.007 0.193 0.189 0.236 0.228 0.154 0.150 0.050 – 0.010 0° 0.016 0.041 M25P40 Max 0.069 0.010 0.019 0.009 0.004 0.197 0.244 0.157 – 0.020 8° 0.050 ...
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... M25P40 Figure 27. VFQFPN8 (MLP8) 8-lead Very thin Fine Pitch Quad Flat Package No lead, 6x5mm, Package Outline Drawing is not to scale. 2. The circle in the top view of the package indicates the position of pin 1. Table 22. VFQFPN8 (MLP8) 8-lead Very thin Fine Pitch Quad Flat Package No lead, ...
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... ST Sales Office. The category of second-Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. 48/51 M25P40 – (2) . M25P40 ...
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... M25P40 13 Revision history Table 24. Document Revision History Date Revision 12-Apr-2001 25-May-2001 11-Sep-2001 16-Jan-2002 12-Sep-2002 13-Dec-2002 12-Jun-2003 24-Nov-2003 12-Mar-2004 05-Aug-2004 03-Jan-2005 01-Aug-2005 1.0 Document written 1.1 Serial Paged Flash Memory renamed as Serial Flash Memory Changes to text: Signal Description/Chip Select; Hold Condition/1st para; ...
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... Table 20: AC Characteristics (50MHz 6). added. Titles of Figure 27 and Table 22 11, Table 16 and Table longer in Table 14: DC CC3 3). shows preliminary data. Table 11: Data parameter for Device Grade 3 added to WI Threshold. Figure 26 and Table Scheme. Table 18 and Table 19. Figure 26 M25P40 modified and 21). and ...
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... M25P40 Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...