M36L0R7050 ST Microelectronics, M36L0R7050 Datasheet
M36L0R7050
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M36L0R7050 Summary of contents
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... PPF ELECTRONIC SIGNATURE – Manufacturer Code: 20h – Device Code (Top Flash Configuration) M36L0R7050T0: 88C4h – Device Code (Bottom Flash Configuration) M36L0R7050B0: 88C5h PACKAGE – Compliant with Lead-Free Soldering Processes – Lead-Free Versions FLASH MEMORY SYNCHRONOUS / ASYNCHRONOUS READ – ...
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... M36L0R7050T0, M36L0R7050B0 TABLE OF CONTENTS FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 FLASH MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. Package PSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 3. TFBGA Connections (Top view through package SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Address Inputs (A0-A22 Data Input/Output (DQ0-DQ15 Flash Chip Enable (E ).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 F Flash Output Enable (G ) ...
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... PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 7. Stacked TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch, Bottom View Outline15 Table 10. Stacked TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch, Package Data PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 11. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 12. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 M36L0R7050T0, M36L0R7050B0 3/18 ...
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... M36L0R7050T0, M36L0R7050B0 SUMMARY DESCRIPTION The M36L0R7050T0 and M36L0R7050B0 com- bine two memory devices in a Multi-Chip Package: a 128-Mbit, Multiple Bank Flash memory, the M30L0R7000T0 or M30L0R7000B0, and a 32- Mbit PseudoSRAM, the M69AR048B. Recom- mended operating conditions do not allow more than one memory to be active at the same time. ...
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... DQ8 DQ2 DQ10 DQ5 DQ0 DQ1 DQ3 DQ12 G F DQ9 DQ11 DQ4 DDP DDQ V DDF M36L0R7050T0, M36L0R7050B0 A21 A11 K F A22 A12 A13 A20 A10 A15 A8 A14 A16 DQ13 WAIT F NC ...
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... M36L0R7050T0, M36L0R7050B0 SIGNAL DESCRIPTIONS See Figure 2., Logic Diagram Names, for a brief overview of the signals connect this device. Address Inputs (A0-A22). Addresses are common inputs for the Flash Memory and the PSRAM components. The other lines (A21-A22) are inputs for the Flash Memory components only. ...
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... See provides the power Load sufficient to carry the required V and erase currents. . DDF M36L0R7050T0, M36L0R7050B0 Program Supply Voltage kept in a low voltage range ( seen as a control input. In this case a volt- gives an absolute protec- PPLKF is in the range of V ...
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... M36L0R7050T0, M36L0R7050B0 FUNCTIONAL DESCRIPTION The PSRAM and Flash memory components have separate power supplies but share the same grounds. They are distinguished by three Chip En- able inputs: E for the Flash memory and for the PSRAM. P Recommended operating conditions do not allow more than one device to be active at a time. The Figure 4 ...
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... M36L0R7050T0, M36L0R7050B0 DQ15-DQ0 Flash Data Out Flash Data In Flash Data Out Upper Byte Lower Byte ...
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... PSRAM DEVICE The M36L0R7050T0 and M36L0R7050B0 contain a 32 Mbit PSRAM. This device can be placed in a number of sleep and partial sleep modes (see ble 3.). For detailed information on how to use the Table 3. Power-Down Configuration Data Mode Deep Power-Down (default) ...
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... European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU. plied. Exposure to Absolute Maximum Rating con- ditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality docu- ments. Parameter PPFH M36L0R7050T0, M36L0R7050B0 Value Min Max –25 85 –25 85 – ...
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... M36L0R7050T0, M36L0R7050B0 DC AND AC PARAMETERS This section summarizes the operating measure- ment conditions, and the DC and AC characteris- tics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement Table 5. Operating and AC Measurement Conditions Parameter ...
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... I V Supply Current (Read) PP2 PPF (1) V Supply Current (Standby) I PPF PP3 Note: 1. Sampled only, not 100% tested Dual Operation current is the sum of read and program or erase currents. DDF M36L0R7050T0, M36L0R7050B0 Test Condition Min DDQ OUT DDQ ...
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... M36L0R7050T0, M36L0R7050B0 Table 8. Flash Memory DC Characteristics - Voltages Symbol Parameter V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage Program Voltage-Logic PP1 PPF V V Program Voltage Factory PPH PPF V Program or Erase Lockout PPLK V V Lock Voltage ...
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... SE 0.400 FE1 millimeters Min Max 1.200 0.200 0.300 0.400 7.900 8.100 0.100 9.900 10.100 – – M36L0R7050T0, M36L0R7050B0 e b ddd A2 A1 BGA-Z42 inches Typ Min 0.0079 0.0335 0.0138 0.0118 0.3150 0.3110 0.2205 0.3937 0.3898 0.2835 0.3465 0.0315 – 0.0472 ...
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... M36L0R7050T0, M36L0R7050B0 PART NUMBERING Table 11. Ordering Information Scheme Example: Device Type M36 = Multi-Chip Package (Multiple Flash + RAM) Flash 1 Architecture L = Multilevel, Multiple Bank, Burst mode Flash 2 Architecture Die Operating Voltage 1.7 to 1.95V DDF1 DDP DDQ Flash 1 Density 7 = 128 Mbit Flash 2 Density ...
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... Document status changed from Target Specification to Preliminary Data. TFBGA88 package fully compliant with the ST ECOPACK specification. Document status promoted from Preliminary Data to full Datasheet. 04-Dec-2004 1.0 Flash memory and PSRAM data updated to the version 1.0 of the M30L0R7000x0 datasheet and to the version 4.0 of the M69AR048B datasheet. M36L0R7050T0, M36L0R7050B0 Revision Details 17/18 ...
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... M36L0R7050T0, M36L0R7050B0 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice ...