m41t256y STMicroelectronics, m41t256y Datasheet
m41t256y
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m41t256y Summary of contents
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... Features ■ 5V operating voltage ■ Serial interface supports extended I addressing (400kHz) ■ Automatic switchover and deselect circuitry ■ Power-fail deselect voltages: – M41T256Y 4 5.5V 4.2V < V < 4.5V PFD PFD ■ Counters for tenths/hundredths of seconds, seconds, minutes, hours, day, date, month, and year ■ ...
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Contents 1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Addresses and data are transferred serially via a two line, bi-directional I built-in address register is incremented automatically after each WRITE or READ data byte. The M41T256Y has a built-in power sense circuit which detects power failures and automatically switches to the battery supply when a power failure occurs. The energy needed to sustain the SRAM and clock operations can be supplied by a lithium button-cell supply when a power failure occurs ...
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... Logic diagram SCL SDA TP 1. For 44-pin SNAPHAT (MT) package only. Table 1. Signal names FT RST SCL SDA RST M41T256Y AI04754b Frequency test (open drain) Reset output (open drain) Serial clock input Serial data input/output Supply voltage Ground Tamper input 7/30 ...
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... RST M41T256Y SCL SDA ...
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... Operating modes The M41T256Y clock operates as a slave device on the serial bus. Access is obtained by implementing a start condition followed by the correct slave address (D0h). The 256K bytes contained in the device can then be accessed sequentially in the following order: 0-7FEF = General purpose RAM 7FF0-7FF6 = Reserved ...
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Start data transfer A change in the state of the data line, from high to low, while the clock is high, defines the START condition. 2.1.3 Stop data transfer A change in the state of the data line, from ...
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Figure 4. Serial bus data transfer sequence (SCL) CLOCK (SDA) DATA START CONDITION Figure 5. Acknowledgement sequence START SCL FROM MASTER DATA OUTPUT BY TRANSMITTER DATA OUTPUT BY RECEIVER DATA LINE STABLE DATA VALID CHANGE OF DATA ALLOWED 1 2 ...
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... The data byte which was addressed will be transmitted and the master receiver will send an acknowledge bit to the slave transmitter. The address pointer is only incremented on reception of an acknowledge clock. The M41T256Y slave transmitter will now place the data byte at address An+1 on the bus, the 12/30 tHD:STA ...
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... Address pointer will wrap around from maximum address to minimum address if consecutive READ or WRITE cycles are performed. An alternate READ mode may also be implemented whereby the master reads the M41T256Y slave without first writing to the (volatile) address pointer. The first address that is read is the last one stored in the pointer (see Figure 7. ...
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Figure 8. Read mode sequence BUS ACTIVITY: MASTER SDA LINE S BUS ACTIVITY: SLAVE ADDRESS DATA n+X Figure 9. Alternate read mode sequence BUS ACTIVITY: MASTER SDA LINE S BUS ACTIVITY: SLAVE ADDRESS DATA n+X 14/30 BYTE BYTE S ADDRESS ...
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... Write mode In this mode the master transmitter transmits to the M41T256Y slave receiver. Bus protocol is shown in Figure 10 on page '0' (R/W=0) is placed on the bus and indicates to the addressed device that byte addresses A(0) and A(1) will follow and written to the on-chip address pointer (MSB of address byte A( “ ...
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... Sleep mode In order to minimize the battery current draw while in storage, the M41T256Y provides the user with a battery “sleep mode,” which disconnects the RAM memory array from the external Lithium battery normally used to provide non-volatile operation in the absence This can significantly extend the lifetime of the battery, when non-volatile operation is CC not needed ...
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Clock operation Year, month, and date are contained in the last three registers of the TIMEKEEPER register map (see Table 3 on page day (day of week). Finally, there are the registers containing the seconds, minutes, and hours, respectively. ...
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... Power-on reset The M41T256Y continuously monitors V point, the RST pulls low (open drain) and remains low on power-up for t passes V (max). The RST pin is an open drain output and an appropriate pull-up resistor PFD should be chosen to control rise time ...
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... Tamper indication circuit The M41T256Y provides an independent input pin, the tamper pin (TP) which can be used to monitor a signal which can result in the setting of the tamper bit (TB) if the tamper enable bit (TEB) is set to a '1.' The tamper pin is triggered by being connected to V This switch is normally open in the application, allowing the pin to be “floating” (internally latched to V when TEB is set) ...
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... Figure 12. Clock calibration NORMAL POSITIVE CALIBRATION NEGATIVE CALIBRATION Two methods are available for ascertaining how much calibration a given M41T256Y may require. 20/ – –0.036 ppm ± –10 ...
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... Data should be considered suspect and verified as correct. A fresh battery should be installed. The battery may be replaced while V The M41T256Y only monitors the battery when a nominal V applications which require extensive durations in the battery back-up mode should be powered-up periodically (at least once every few months) in order for this technique to be beneficial ...
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... These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 5. ...
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... LP 1. Effective capacitance measured with power supply at 5V; sampled only, not 100% tested 25° 1MHz. 3. Outputs deselected. conditions. Designers should check that the operating conditions Parameter ) L 0.8V CC 0.2V CC (1) and (2) Parameter Table 6: M41T256Y 4.5 to 5.5V –25 to 70°C 100pF 50ns 0. 0. ...
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... Resonant frequency 0 R Series resistance S C Load capacitance L 1. Load capacitors are integrated within the M41T256Y. Circuit board layout considerations for the 32.768kHz crystal of minimum trace lengths and isolation from RF generating signals should be taken into account. 24/30 (1) Test condition T = 25° 0V ...
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Figure 14. Power down/up mode AC waveforms PFD (max) V PFD (min INPUTS RECOGNIZED RST OUTPUTS VALID (PER CONTROL INPUT) Table 10. Power down/up AC characteristics Symbol ( (max ...
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Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner ...
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Figure 16. SH – 4-pin SNAPHAT housing for 120mAh battery & crystal outline Note: Drawing is not to scale. Table 12. SH – 4-pin SNAPHAT housing for 120mAh battery & crystal, mechanical data Symb Typ ...
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Part numbering Table 13. Ordering information scheme Example: Device type M41T Supply voltage and write protect voltage 256Y = V = 4.5 to 5.5V 4.2 to 4.5V CC PFD Package ( SOH44 Temperature range 7 ...
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Revision history Table 15. Document revision history Date Version February 2002 26-Apr-02 31-May-02 03-Jul-02 12-Jul-02 29-Jul-02 20-Dec-02 04-Jan-03 26-Mar-03 15-Jun-04 16-Apr-2007 09-Nov-2007 1.0 First Issue 1.1 Addition of “Tamper Event Time-Stamp” text Add Sleep Mode, 44-pin with SNAPHAT package ...
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... Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...