m41t94 STMicroelectronics, m41t94 Datasheet
m41t94
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m41t94 Summary of contents
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... SOIC ■ 28-lead SOIC package provides direct connection for a SNAPHAT top which contains the battery and crystal ■ RoHS compliant – Lead-free second level interconnect November 2007 2.70V 4.50V Rev 5 M41T94 16 1 SO16 (MQ) SNAPHAT (SH) battery & crystal 28 1 SOH28 (MH) 1/41 www.st.com 1 ...
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Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Description The M41T94 is a serial real-time clock with 44 bytes of NVRAM and a RESET output. A built-in 32,768Hz oscillator (external crystal controlled) and 8 bytes of the SRAM (see Table 4 on page 19) are used for the clock/calendar function and are configured in binary coded decimal (BCD) format. ...
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... For SO16 package only. Figure 2. 16-pin SOIC connections XO RST WDI RSTIN1 RSTIN2 V BAT BAT RST IRQ/FT/OUT M41T94 SQW SDO V SS AI03683 IRQ/FT/OUT 4 13 THS M41T94 5 12 SDI 6 11 SQW 7 10 SCL 8 9 SDO AI03684 7/41 ...
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... Watchdog input Oscillator input Oscillator output Battery supply voltage Supply voltage Ground SQW M41T94 WDI 8 21 RSTIN1 9 20 RSTIN2 AI03685 IRQ/FT/OUT NC NC ...
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... CPOL (clock polarity) and CPHA (clock phase) are bits that may be set in the SPI control register of the MCU. REAL TIME CLOCK CALENDAR 44 BYTES USER RAM RTC w/ALARM & CALIBRATION WATCHDOG SQUARE WAVE COMPARE 2.5V COMPARE 2.5V POR COMPARE V PFD = 4.4V (2.65V if THS = M41T94 IRQ/FT/OUT WDF SQW BL RST (1) AI04785 XXXXX XXXXX E AI03686 (1) 9/41 ...
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Table 2. Function table Mode E Disable reset H WRITE L READ L 1. SDO remains at High Z until eight bits of data are ready to be shifted out during a READ. Figure 6. Data and clock timing CPOL ...
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... Figure 8 on page on the rising edge of the clock input. The output data on the SDO pin changes state after the falling edge of the clock input. The M41T94 can be driven by a microcontroller with its SPI peripheral running in either of the two following modes: ● ...
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... Operation The M41T94 clock operates as a slave device on the SPI serial bus. Each memory device is accessed by a simple serial interface that is SPI bus compatible. The bus signals are SCL, SDI and SDO (see the Chip Enable input (E) is held low. All instructions, addresses and data are shifted serially in and out of the chip ...
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... The SCL input, which is generated by the microcontroller, is active only during address and data transfer to any device on the SPI bus (see The M41T94 can be driven by a microcontroller with its SPI peripheral running in either of the two following modes: ● ...
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Figure 8. Output timing requirements E SCL tCLQV tCLQX MSB OUT SDO ADDR. LSB IN SDI 14/41 tCH tCL LSB OUT tQLQH tQHQL tEHQZ AI04634 ...
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Table 3. AC characteristics Symbol f Serial clock input frequency SCL (2) t Clock high CH (3) t Clock transition (fall time) CHCL t Serial clock input high to input data transition CHDX t Serial clock input high to chip ...
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... With valid V applied, the M41T94 can be accessed as described above with READ or CC WRITE cycles. Should the supply voltage decay, the M41T94 will automatically deselect, write protecting itself when V page 32). At this time, the reset pin (RST) is driven active and will remain active until V returns to nominal levels ...
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Figure 9. Read mode sequence SCL W/R BIT 7 BIT ADDRESS SDI MSB SDO HIGH IMPEDANCE Figure 10. Write mode sequence SCL 7 BIT ADDR W/R ...
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... For more information, see Application Note AN1572. 4.2 Clock registers The M41T94 offers 20 internal registers which contain clock, Alarm, Watchdog, Flag, Square Wave and Control data (see locations which contain external (user accessible) and internal copies of the data (usually referred to as BiPORT except that they are updated periodically by the simultaneous transfer of the incremented internal copy ...
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Table 4. Clock register map Addr 00h 0.1 seconds 01h ST 10 seconds 02h 0 10 minutes 03h CEB CB 10 Hours 04h 05h date 06h 07h 10 ...
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... AFE are set. The ABE and AFE bits are reset during power-up, therefore an Alarm generated during power-up will only set AF. The user can read the Flag register at system boot-up to determine if an Alarm was generated while the M41T94 was in the deselect mode during power-up. ...
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Figure 11. Alarm interrupt reset waveforms 0Eh ACTIVE FLAG IRQ/FT/OUT Figure 12. Back-up mode alarm waveforms PFD V SO ABE, AFE Bits in Interrupt Register AF bit in Flags Register IRQ/FT/OUT 0Fh HIGH-Z 10h HIGH-Z AI03664 tREC ...
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... Watchdog register = 3 seconds). Note: Accuracy of timer is within ± the selected resolution. If the processor does not reset the timer within the specified period, the M41T94 sets the WDF (Watchdog Flag) and generates a watchdog interrupt or a microprocessor reset. WDF is reset by reading the Flags register (0Fh). ...
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... The RST pin is an open drain output and an appropriate pull-up resistor should be chosen to control rise time. 4.7 Reset inputs (RSTIN1 & RSTIN2) The M41T94 provides two independent inputs which can generate an output reset. The duration and function of these resets is identical to a reset generated by a power cycle. Table 7 on page 24 function. Pulses shorter than t ...
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... Programmable (see 4.8 Calibrating the clock The M41T94 is driven by a quartz-controlled oscillator with a nominal frequency of 32,768Hz. Uncalibrated clock accuracy will not exceed ±35 ppm (parts per million) oscillator frequency error at 25°C, which equates to about ±1.53 minutes per month. When the Calibration circuit is properly employed, accuracy improves to better than ±2 ppm at 25°C. ...
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... Two methods are available for ascertaining how much calibration a given M41T94 may require. The first involves setting the clock, letting it run for a month and comparing known accurate reference and recording deviation over a fixed period of time ...
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Figure 14. Crystal accuracy across temperature Frequency (ppm –20 –40 –60 –80 –100 –120 –140 –160 –40 –30 Figure 15. Calibration waveform NORMAL POSITIVE CALIBRATION NEGATIVE CALIBRATION 4.9 Century bit Bits D7 and D6 of clock register 03h ...
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... The IRQ/FT/OUT pin is an open drain which requires an external pull-up resistor. 4.11 Battery low warning The M41T94 automatically performs battery voltage monitoring upon power-up and at factory-programmed time intervals of approximately 24 hours. The battery low (BL) bit, bit D4 of Flags register 0Fh, will be asserted if the battery voltage is found to be less than approximately 2 ...
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Initial power-on defaults Upon initial application of power to the device, the following register bits are set to a '0' state: Watchdog register, TR, FT, AFE, ABE, and SQWE. The following bits are set to a '1' state: ST, ...
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... These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 10. ...
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... Low-pass filter input time constant (SDA and SCL Effective capacitance measured with power supply at 5V; sampled only, not 100% tested 25° 1MHz. 3. Outputs are deselected. 30/41 Parameter ) L 0.8V CC 0.2V CC (1)(2) Parameter (1) M41T94 2.7 to 5.5V –40 to 85°C 100pF 50ns 0.2 to 0.8V CC 0.3 to 0.7V CC 0.7V CC 0.3V CC AI02568 Min Max ...
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... C Load capacitance L 1. Load capacitors are integrated within the M41T94. Circuit board layout considerations for the 32.768 kHz crystal of minimum trace lengths and isolation from RF generating signals should be taken into account. These characteristics are externally supplied. 2. STMicroelectronics recommends the KDS DT-38: 1TA/1TC252E127, Tuning Fork Type (thru-hole) or the DMX-26S: 1TJS125FH2A212, (SMD) quartz crystal for industrial temperature operations ...
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Figure 17. Power down/up mode AC waveforms PFD (max) V PFD (min INPUTS RST OUTPUTS (PER CONTROL INPUT) Table 15. Power down/up AC characteristics Symbol ( (max PFD (3) t ...
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Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner ...
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Figure 18. SO16 – 16-lead plastic small outline package outline 1. Drawing is not to scale. Table 16. SO16 – 16-lead Plastic small outline package mechanical data Symbol 34/41 ...
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Figure 19. SOH28 – 28-lead plastic small outline, battery SNAPHAT, package outline SOH-A 1. Drawing is not to scale. Table 17. SOH28 – 28-lead plastic small outline, battery SNAPHAT, package mechanical data millimeters Symbol Typ ...
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Figure 20. SH – 4-pin SNAPHAT housing for 48mAh battery & crystal, package outline 1. Drawing is not to scale. Table 18. SH – 4-pin SNAPHAT housing for 48mAh battery & crystal, package mechanical data Symbol Typ ...
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Figure 21. SH – 4-pin SNAPHAT housing for 120mAh battery & crystal, package outline 1. Drawing is not to scale. Table 19. SH – 4-pin SNAPHAT housing for 120mAh battery & crystal, package mech. data millimeters Symbol Typ Min A ...
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Part numbering Table 20. Ordering information scheme Example: Device type M41T Supply voltage and write protect voltage 2.7 to 5.5V CC THS = V ; 4.20V CC THS = V ; 2.55V SS Package MQ ...
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References The crystal supplier KDS as cited in supplied) on page 31 Table 14: Crystal electrical characteristics (externally can be contacted at kouhou@kdsj.co.jp or http://www.kdsj.co.jp. 39/41 ...
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Revision history Table 22. Document revision history Date Revision April 2002 25-Apr-02 03-Jul-02 06-Nov-02 26-Mar-03 28-Apr-03 15-Jun-04 29-Aug-2006 09-Nov-2007 40/41 1.0 First edition Adjust graphic (Figure 4 on page 1.1 Table 20 on page 38); adjust characteristics Table 14 ...
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... Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...