MAX3624 Maxim Integrated Products, MAX3624 Datasheet
MAX3624
Manufacturer Part Number
MAX3624
Description
Precision Clock Generator
Manufacturer
Maxim Integrated Products
Datasheet
1.MAX3624.pdf
(12 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MAX3624UTJ+
Manufacturer:
MICROSEMI/美高森美
Quantity:
20 000
www.datasheet4u.com
The MAX3624 is a low-jitter precision clock generator
optimized for network application. The device inte-
grates a crystal oscillator and a phase-locked loop
(PLL) clock multiplier to generate high-frequency clock
outputs for Ethernet, Fibre Channel, SONET/SDH, and
other networking applications.
Maxim’s proprietary PLL design features ultra-low jitter
(0.36ps
tion, minimizing design risk for network equipment.
The MAX3624 has three LVPECL outputs and one
LVCMOS output. Selectable output dividers and a
selectable feedback divider allow a range of output
frequencies.
19-0977; Rev 0; 8/07
Pin Configuration and Typical Application Circuit appear at
end of data sheet.
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Ethernet Networking Equipment
Fibre Channel Storage Area Network
SONET/SDH Network
RMS
REF_IN
) and excellent power-supply noise rejec-
X_OUT
27pF
33pF
X_IN
________________________________________________________________ Maxim Integrated Products
General Description
OSCILLATOR
Low-Jitter, Precision Clock Generator
CRYSTAL
LVCMOS
DIVIDERS:
M = 16, 24, 25, 32
NA = 1, 2, 3, 4, 5, 6, 8, 10, 12
NB = 1, 2, 3, 4, 5, 6, 8, 10, 12
IN_SEL
0
1
Applications
FB_SEL[1:0]
SELA[1:0]
SELB[1:0]
BYPASS
PFD
RESET LOGIC/POR
FB_SEL[1:0]
DIVIDER
FILTER
RESET
MR
M
620MHz TO 648MHz
VCO
o Crystal Oscillator Interface: 19.375MHz to 27MHz
o CMOS Input: 19MHz to 40.5MHz
o Output Frequencies
o Low Jitter
o Excellent Power-Supply Noise Rejection
o No External Loop Filter Capacitor Required
+ Denotes a lead-free package.
*EP = Exposed pad.
MAX3624UTJ+
MAX3624
RESET
Ethernet: 62.5MHz, 125MHz, 156.25MHz,
Fibre Channel: 106.25MHz, 159.375MHz,
SONET/SDH: 77.76MHz, 155.52MHz, 311.04MHz
0.14ps
0.36ps
PART
312.5MHz
212.5MHz, 318.5MHz
BYPASS
0
1
with Four Outputs
RMS
RMS
SELA[1:0]
SELB[1:0]
DIVIDER
DIVIDER
RESET
RESET
TEMP RANGE PIN-PACKAGE
(1.875MHz to 20MHz)
(12kHz to 20MHz)
NA
NB
0°C to +85°C
Ordering Information
LVCMOS
BUFFER
LVPECL
BUFFER
LVPECL
BUFFER
LVPECL
BUFFER
32 TQFN-EP*
Block Diagram
QAC_OE
QA_C
QA_OE
QA
QA
QB1_OE
QB1
QB1
QB0_OE
QB0
QB0
Features
T3255-3
CODE
PKG
1
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