mc100e210 ON Semiconductor, mc100e210 Datasheet

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mc100e210

Manufacturer Part Number
mc100e210
Description
5v Ecl Dual 1 4, 1 5 Differential Fanout Buffer
Manufacturer
ON Semiconductor
Datasheet

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MC100E210
5V ECL Dual 1:4, 1:5
Differential Fanout Buffer
fanout buffer designed with clock distribution in mind. The device
features two fanout buffers, a 1:4 and a 1:5 buffer, on a single chip. The
device features fully differential clock paths to minimize both device and
system skew. The dual buffer allows for the fanout of two signals through
a single chip, thus reducing the skew between the two fundamental
signals from a part−to−part skew down to an output−to−output skew. This
capability reduces the skew by a factor of 4 as compared to using two
LVE111’s to accomplish the same task.
pair, and the greatest TPD delay time results from terminating all the
output pairs. This shift is about 10−20 pS in TPD. The skew between
any two output pairs within a device is typically about 25 nS. If other
output pairs are not terminated, the lowest TPD delay time results
from both output pairs and the skew is typically 25 nS. When all
outputs are terminated, the greatest TPD (delay time) occurs and all
outputs display about the same 10−20 pS increase in TPD, so the
relative skew between any two output pairs remains about 25 nS.
Application Note AN1406/D.
device only. For single-ended input conditions, the unused differential
input is connected to V
rebias AC coupled inputs. When used, decouple V
0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When
not used, V
October, 2003 − Rev. 2
The MC100E210 is a low voltage, low skew dual differential ECL
The lowest TPD delay time results from terminating only one output
For more information on using PECL, designers should refer to
The V
NECL Mode Operating Range: V
For Additional Information, see Application Note AND8003/D
Oxygen Index: 28 to 34
Dual Differential Fanout Buffers
200 ps Part−to−Part Skew
50 ps Typical Output−to−Output Skew
Low Voltage ECL/PECL Compatible
The 100 Series Contains Temperature Compensation
28−lead PLCC Packaging
PECL Mode Operating Range: V
Internal Input 75 KW Pulldown Resistors
Q Output will Default LOW with Inputs Open or at V
ESD Protection: Human Body Model; >2 KV,
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Moisture Sensitivity Level 1
Flammability Rating: UL 94 V−0 @ 0.125 in,
Transistor Count = 179 devices
Semiconductor Components Industries, LLC, 2003
BB
BB
pin, an internally generated voltage supply, is available to this
should be left open.
Machine Model; >200 V
BB
as a switching reference voltage. V
CC
CC
= 0 V with V
= 4.2 V to 5.7 V with V
EE
BB
= −4.2 V to −5.7 V
and V
EE
BB
CC
may also
1
EE
via a
= 0 V
*For additional information, see Application Note
†For information on tape and reel specifications,
MC100E210FN
MC100E210FNR2
AND8002/D
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Device
FN SUFFIX
ORDERING INFORMATION
CASE 776
PLCC−28
A
WL = Wafer Lot
YY = Year
WW = Work Week
http://onsemi.com
= Assembly Location
PLCC−28 500 Tape & Reel
Package
PLCC−28
Publication Order Number:
MC100E210FN
MARKING
DIAGRAM
AWLYYWW
37 Units / Rail
MC100E210/D
Shipping
1 28

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mc100e210 Summary of contents

Page 1

... MC100E210 5V ECL Dual 1:4, 1:5 Differential Fanout Buffer The MC100E210 is a low voltage, low skew dual differential ECL fanout buffer designed with clock distribution in mind. The device features two fanout buffers, a 1:4 and a 1:5 buffer single chip. The device features fully differential clock paths to minimize both device and system skew ...

Page 2

... Thermal Resistance (Junction−to−Ambient Thermal Resistance (Junction−to−Case PECL Operating Range EE NECL Operating Range T Wave Solder sol 1. Maximum Ratings are those values beyond which device damage may occur. MC100E210 Qa3 17 Qa3 Qb0 16 CLKa 15 V CCO CLKa ...

Page 3

... Input and output parameters vary 1:1 with V 6. Outputs are terminated through resistor min varies 1:1 with V , max varies 1:1 with V IHCMR EE MC100E210 = 5 0.0 V (Note 2) EE −40 C Min Typ Max ...

Page 4

... The within−device skew is defined as the worst case difference between any two similar delay paths within a single device. 12. V (min) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. The V PP for the E210 as a differential input as low will still produce full ECL levels at the output. MC100E210 = 0 0 −5.0 V (Note 8) EE ...

Page 5

... AN1650 − Using Wire−OR Ties in ECLinPS Designs AN1672 − The ECL Translator Guide AND8001 − Odd Number Counters Design AND8002 − Marking and Date Codes AND8020 − Termination of ECL Logic Devices MC100E210 − 2 ...

Page 6

... PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). MC100E210 PACKAGE DIMENSIONS PLCC−28 FN SUFFIX PLASTIC PLCC PACKAGE CASE 776−02 ISSUE E ...

Page 7

... Notes MC100E210 http://onsemi.com 7 ...

Page 8

... USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Phone: 81−3−5773−3850 http://onsemi.com 8 ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. MC100E210/D ...

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