MC100EL34 ON Semiconductor, MC100EL34 Datasheet

MC100EL34

Manufacturer Part Number

MC100EL34

Description

2 /4 /8 Clock Generation Chip

Manufacturer

ON Semiconductor

Datasheet

1.MC100EL34.pdf (8 pages)

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MC10EL34, MC100EL34

5V ECL ÷2, ÷4, ÷8 Clock

Generation Chip

Description

designed explicitly for low skew clock generation applications. The

internal dividers are synchronous to each other, therefore, the common

output edges are all precisely aligned. The V

generated voltage supply, is available to this device only. For

single-ended input conditions, the unused differential input is

connected to V

rebias AC coupled inputs. When used, decouple V

0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA.

When not used, V

dividers will only be enabled/disabled when the internal clock is

already in the LOW state. This avoids any chance of generating a runt

clock pulse on the internal clock when the device is enabled/disabled

as can happen with an asynchronous control. An internal runt pulse

could lead to losing synchronization between the internal divider

stages. The internal enable flip−flop is clocked on the falling edge of

the input clock, therefore, all associated specification limits are

referenced to the negative edge of the clock input.

master reset (MR) input allows for the synchronization of the internal

dividers, as well as multiple EL34s in a system.

Features

•

*For additional information on our Pb−Free strategy and soldering details, please

November, 2006 − Rev. 10

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

The MC10/100EL34 is a low skew ÷2, ÷4, ÷8 clock generation chip

The common enable (EN) is synchronous so that the internal

Upon startup, the internal flip-flops will attain a random state; the

The 100 Series contains temperature compensation.

50 ps Output-to-Output Skew

Synchronous Enable/Disable

Master Reset for Synchronization

PECL Mode Operating Range:

NECL Mode Operating Range:

Internal Input 75 kW Pulldown Resistors on CLK(s), EN, and MR

Pb−Free Packages are Available*

= 4.2 V to 5.7 V with V

= 0 V with V

as a switching reference voltage. V

should be left open.

= −4.2 V to −5.7 V

= 0 V

pin, an internally

and V

may also

via a

See detailed ordering and shipping information in the package

dimensions section on page 7 of this data sheet.

*For additional marking information, refer to

Application Note AND8002/D.

AWLYWW

10EL34G

ORDERING INFORMATION

MARKING DIAGRAMS*

http://onsemi.com

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

CASE 751B

D SUFFIX

SO−16

Publication Order Number:

100EL34G

AWLYWW

MC10EL34/D

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