MC100EP016A ON Semiconductor, MC100EP016A Datasheet
MC100EP016A
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MC100EP016A Summary of contents
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... MC100EP016A 3.3 V ECL 8−Bit Synchronous Binary Up Counter The MC100EP016A is a high−speed synchronous, presettable, cascadeable 8−bit binary counter. Architecture and operation are the same as the ECLinPS family MC100E016 with higher operating speed. The counter features internal feedback to TC gated by the TCLD (Terminal Count Load) pin. When TCLD is LOW (or left open, in ...
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... Load Terminal Count Reset MC100EP016A PIN DESCRIPTION PIN 16 P5 P0−P7 Q0−Q7 14 CE CLK*, CLK COUT TCLD* 10 COUT COUT, COUT ...
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... Figure 2. 8-BIT Binary Counter Logic Diagram ATTRIBUTES Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Moisture Sensitivity (Note 1) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. MC100EP016A Q 0 Q0M CE MASTER SLAVE Q0M Q 0 ...
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... Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. MC100EP016A Condition 1 Condition 2 ...
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... Input and output parameters vary 1:1 with V 6. All loading with 50 ohms to V −2.0 volts min varies 1:1 with IHCMR EE IHCMR input signal. MC100EP016A (Note −40 C Min Typ Max Min 130 ...
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... Reset Recovery Time RR t Minimum Pulse Width CLK PW Minimum Pulse Width Output Rise/Fall Times r f 20% − 80% 8. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 ohms to V MC100EP016A 3 3 −40 C Min Typ Max Min 1.3 1.5 1.2 ...
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... Programmable Divider The EP016A has been designed with a control pin which makes it ideal for use as an 8-bit programmable divider. The MC100EP016A Applications Information to a high state disabling the count operation of the more significant counters and placing them back into hold modes. ...
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... TC output can feed the clock input of a toggle flip flop to create a signal divided as desired with a 50% duty cycle. Load 1001 0000 CLK PE TC Figure 5. Divide by 113 EP016A Programmable Divider Waveforms MC100EP016A (continued Table 1. Preset Values for Various Divide Ratios Divide de Ratio ...
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... OR tied the cascaded count operation would not operate properly. Because in the cascaded form the PE feedback is external and requires external gating, the maximum frequency of operation will be significantly less than the same operation in a single device. MC100EP016A (continued ...
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... Odd Number Counters Design AND8002 − Marking and Date Codes AND8009 − ECLinPS Plus Spice I/O Model Kit AND8020 − Termination of ECL Logic Devices For an updated list of Application Notes, please see our website at http://onsemi.com. MC100EP016A Q D Receiver Device − ...
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... DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. MC100EP016A PACKAGE DIMENSIONS LQFP FA SUFFIX 32−LEAD PLASTIC PACKAGE CASE 873A−02 ISSUE B 4X ...
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... USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Phone: 81−3−5773−3850 http://onsemi.com 12 ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. MC100EP016A/D ...