MC100EP14D ON Semiconductor, MC100EP14D Datasheet

MC100EP14D

Manufacturer Part Number

MC100EP14D

Description

3.3V / 5V 1:5 Differential ECL/PECL/HSTL Clock Driver

Manufacturer

ON Semiconductor

Datasheet

1.MC100EP14D.pdf (8 pages)

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MC100EP14

3.3V / 5V 1:5 Differential

ECL/PECL/HSTL Clock Driver

clock distribution in mind, accepting two clock sources into an input

multiplexer. The ECL/PECL input signals can be either differential or

single−ended (if the V

the LVEP14 is operating under PECL conditions.

design, layout, and processing minimize skew within a device and from

device to device.

any differential output need to be terminated even if only one output is

being used. If an output pair is unused, both outputs may be left open

(unterminated) without affecting skew.

disabled in the LOW state. This avoids a runt clock pulse when the

device is enabled/disabled as can happen with an asynchronous

control. The internal flip flop is clocked on the falling edge of the input

clock, therefore all associated specification limits are referenced to the

negative edge of the clock input.

from a positive V

used for high performance clock distribution in 5.0 V systems.

Designers can take advantage of the EP14’s performance to distribute

low skew clocks across the backplane or the board.

*For additional information on our Pb−Free strategy and soldering details, please

June, 2004 − Rev. 3

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

The MC100EP14 is a low skew 1−to−5 differential driver, designed with

The EP14 specifically guarantees low output−to−output skew. Optimal

To ensure that the tight skew specification is realized, both sides of

The common enable (EN) is synchronous, outputs are enabled/

The MC100EP14, as with most other ECL devices, can be operated

400 ps Typical Propagation Delay

100 ps Device−to−Device Skew

25 ps Within Device Skew

Maximum Frequency > 2 GHz Typical

The 100 Series Contains Temperature Compensation

PECL and HSTL Mode:

NECL Mode:

Open Input Default State

These are Pb−Free Devices

Semiconductor Components Industries, LLC, 2004

= 3.0 V to 5.5 V with V

= 0 V with V

supply in PECL mode. This allows the EP14 to be

= −3.0 V to −5.5 V

output is used). HSTL inputs can be used when

= 0 V

See detailed ordering and shipping information in the package

dimensions section on page 6 of this data sheet.

*For additional marking information, refer to

Application Note AND8002/D.

ORDERING INFORMATION

MARKING DIAGRAM*

http://onsemi.com

CASE 948E

= Assembly Location

= Wafer Lot

= Year

= Work Week

DT SUFFIX

TSSOP−20

ALYW

EP14

100

Publication Order Number:

MC100EP14/D

Related parts for MC100EP14D

MC100EP14D Summary of contents

Page 1

... CC EE Open Input Default State These are Pb−Free Devices *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Semiconductor Components Industries, LLC, 2004 June, 2004 − Rev. 3 http://onsemi.com TSSOP−20 ...

Page 2

Warning: All V to Power Supply to guarantee proper operation. Figure 1. TSSOP−20 (Top View) and Logic Diagram Table 1. PIN DESCRIPTION Pin Function CLK0*, CLK0** ECL/PECL/HSTL CLK Input CLK1*, ...

Page 3

Table 3. ATTRIBUTES Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see ...

Page 4

Table 5. 100EP DC CHARACTERISTICS, PECL Symbol Characteristic I Power Supply Current EE V Output HIGH Voltage (Note Output LOW Voltage (Note Input HIGH Voltage (Single−Ended Input LOW Voltage (Single−Ended ...

Page 5

Table 7. 100EP DC CHARACTERISTICS, NECL Symbol Characteristic I Power Supply Current EE V Output HIGH Voltage (Note Output LOW Voltage (Note Input HIGH Voltage (Single−Ended Input LOW Voltage (Single−Ended ...

Page 6

... Figure 3. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) ORDERING INFORMATION Device MC100EP14DT MC100EP14DTR2 †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. MC100EP14 5.0 V 3.3 V É ...

Page 7

MC100EP14 Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPSt I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS ...

Page 8

... G H DETAIL E N. American Technical Support: 800−282−9855 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Phone: 81−3−5773−3850 http://onsemi.com 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. ...

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