MC100LVEP14 ON Semiconductor, MC100LVEP14 Datasheet

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MC100LVEP14

Manufacturer Part Number
MC100LVEP14
Description
Low-Voltage 1:5 Differential LVECL/LVPECL/LVEPECL/HSTL Clock Driver
Manufacturer
ON Semiconductor
Datasheet

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MC100LVEP14
Low-Voltage 1:5 Differential
LVECL/LVPECL/LVEPECL/HSTL
Clock Driver
with clock distribution in mind, accepting two clock sources into an input
multiplexer. The LVECL/LVPECL input signals can be either differential
or single–ended (if the V BB output is used). HSTL inputs can be used
when the LVEP14 is operating under LVPECL conditions.
Optimal design, layout, and processing minimize skew within a device and
from lot to lot.
any differential output need to be terminated identically into 50
if only one side is being used. When fewer than all five pairs are used,
identically terminate all the output pairs on the same package side
whether used or unused. If no outputs on a single side are used, then
leave these outputs open (unterminated). This will maintain minimum
output skew. Failure to do this will result in a 10–20ps loss of skew
margin (propagation delay) in the output(s) in use.
disabled in the LOW state. This avoids a runt clock pulse when the
device is enabled/disabled as can happen with an asynchronous
control. The internal flip flop is clocked on the falling edge of the input
clock, therefore all associated specification limits are referenced to the
negative edge of the clock input.
operated from a positive V CC supply in LVPECL mode. This allows
the LVEP14 to be used for high performance clock distribution in
+3.3V or +2.5V systems. Single ended input operation is limited to a
V CC
Designers can take advantage of the LVEP14’s performance to
distribute low skew clocks across the backplane or the board. For more
information, refer to Application Note AN1406/D.
May, 2000 – Rev. 1
The MC100LVEP14 is a low skew 1–to–5 differential driver, designed
The LVEP14 specifically guarantees low output–to–output skew.
To ensure that the tight skew specification is realized, both sides of
The common enable (EN) is synchronous, outputs are enabled/
The MC100LVEP14, as with most other LVECL devices, can be
For Additional Information, See Application Note AND8003/D
100ps Part–to–Part Skew
25ps Output–to–Output Skew
Differential Design
400ps Typical Propagation Delay
High Bandwidth to 1.5 Ghz Typical
LVPECL and HSTL mode: +2.375V to +3.8V V CC with V EE = 0V
LVECL mode: 0V V CC with V EE = –2.375V to –3.8V
75k Internal Pulldown CLKs, Pull up & Pulldown CLKs
ESD Protection: >2KV HBM; >100V MM
Moisture Sensitivity Level 2
Flammability Rating: UL–94 code V–0 @ 1/8”, Oxygen Index 28 to 34
Transistor Count = 357 devices
Semiconductor Components Industries, LLC, 2000
3.0V in LVPECL mode, or V EE
–3.0V in LVECL mode.
1
W
even
*For additional information, see Application Note
MC100LVEP14DT
MC100LVEP14DTR2 TSSOP
AND8002/D
Device
ALYW
VP14
100
ORDERING INFORMATION
MARKING DIAGRAM*
http://onsemi.com
20
CASE 948E
TSSOP–20
DT SUFFIX
Package
TSSOP
Publication Order Number:
VP = LVEP
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
1
2500 Tape & Reel
MC100LVEP14/D
75 Units/Tray
Shipping

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MC100LVEP14 Summary of contents

Page 1

... Low-Voltage 1:5 Differential LVECL/LVPECL/LVEPECL/HSTL Clock Driver The MC100LVEP14 is a low skew 1–to–5 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The LVECL/LVPECL input signals can be either differential or single–ended (if the V BB output is used). HSTL inputs can be used when the LVEP14 is operating under LVPECL conditions. The LVEP14 specifically guarantees low output– ...

Page 2

... MC100LVEP14 VCC EN VCC CLK1 CLK1 VBB CLK0 CLK0 CLK_SEL VEE Figure 1. 20–Lead TSSOP and Logic Diagram (Top View) Warning: All V CC and V EE pins must be externally connected to Power Supply to guarantee proper operation ...

Page 3

... Symbol Characteristic V IH Input HIGH Voltage V IL Input LOW Voltage X V Input Crossover Voltage I CC Power Supply Current (Note 6 2.375V to 3.8V 0V, all other pins floating. MC100LVEP14 Parameter Continuous Surge { Still Air 500lfpm (Note 5.) – Min Typ Max ...

Page 4

... Part–to–Part Skew (Diff) t JITTER Cycle–to–Cycle Jitter V PP Minimum Input Swing Output Rise/Fall Time (20%–80%) 16. F max guaranteed for functionality only. 17. Skew is measured between outputs under identical transitions. MC100LVEP14 0.5V 0V) (Note 11.) – Min Typ Max Min Typ ...

Page 5

... L PIN 1 IDENT 1 0.15 (0.006 –V– 0.100 (0.004) –T– SEATING PLANE MC100LVEP14 PACKAGE DIMENSIONS TSSOP–20 DT SUFFIX CASE 948E–02 ISSUE A NOTES Í Í Í Í Í Í Í Í –U– ...

Page 6

... Notes MC100LVEP14 http://onsemi.com 6 ...

Page 7

... Notes MC100LVEP14 http://onsemi.com 7 ...

Page 8

... Email: ONlit–asia@hibbertco.com JAPAN: ON Semiconductor, Japan Customer Focus Center 4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–8549 Phone: 81–3–5740–2745 Email: r14525@onsemi.com ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative. http://onsemi.com 8 MC100LVEP14/D ...

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