MC10EP52DT ON Semiconductor, MC10EP52DT Datasheet

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MC10EP52DT

Manufacturer Part Number
MC10EP52DT
Description
Flip Flops 3.3V/5V ECL D-Type
Manufacturer
ON Semiconductor
Datasheet
1.MC10EP52DT.pdf (12 pages)

Specifications of MC10EP52DT

Product Category
Flip Flops
Number Of Circuits
1
Logic Family
10
Logic Type
D-Type Flip-Flop
Polarity
Inverting/Non-Inverting
Input Type
Differential
Output Type
Differential
Propagation Delay Time
0.38 ns
High Level Output Current
- 50 mA
Low Level Output Current
50 mA
Supply Voltage - Max
- 5.5 V, 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
TSSOP-8
Minimum Operating Temperature
- 40 C
Number Of Input Lines
1
Number Of Output Lines
1
Factory Pack Quantity
100
Supply Voltage - Min
- 3 V
MC10EP52, MC100EP52
3.3V / 5V ECL Differential
Data and Clock D Flip-Flop
Description
flip−flop. The device is pin and functionally equivalent to the EL52
device.
LOW and is transferred to the slave, and thus the outputs, upon a
positive transition of the clock. The differential clock inputs of the
EP52 allow the device to also be used as a negative edge triggered
device.
conditions (pulled down to V
stable.
Features
•
•
•
•
•
•
•
•
© Semiconductor Components Industries, LLC, 2008
August, 2008 − Rev. 7
The MC10EP/100EP52 is a differential data, differential clock D
Data enters the master portion of the flip−flop when the clock is
The EP52 employs input clamping circuitry so that under open input
The 100 Series contains temperature compensation.
330 ps Typical Propagation Delay
Maximum Frequency u 4 GHz Typical
PECL Mode: V
NECL Mode: V
Open Input Default State
Safety Clamp on Inputs
Q Output Will Default LOW with Inputs Open or at V
Pb−Free Packages are Available
CC
CC
= 3.0 V to 5.5 V with V
= 0 V with V
EE
) the outputs of the device will remain
EE
= −3.0 V to −5.5 V
EE
= 0 V
EE
1
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
CASE 506AA
CASE 948R
MN SUFFIX
DT SUFFIX
CASE 751
D SUFFIX
TSSOP−8
8
*For additional marking information, refer to
SOIC−8
8
H
K
5T
3O
(Note: Microdot may be in either location)
DFN8
Application Note AND8002/D.
1
1
ORDERING INFORMATION
= MC10
= MC100 L
= MC10
= MC100 W = Work Week
http://onsemi.com
A
Y
M = Date Code
G
8
1
8
1
Publication Order Number:
= Assembly Location
= Wafer Lot
= Year
= Pb−Free Package
HEP52
ALYWG
ALYW
1
HP52
G
G
DIAGRAMS*
MARKING
4
8
1
MC10EP52/D
8
1
KEP52
ALYW
ALYWG
KP52
1
G
G
4

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MC10EP52DT Summary of contents

Page 1

MC10EP52, MC100EP52 3.3V / 5V ECL Differential Data and Clock D Flip-Flop Description The MC10EP/100EP52 is a differential data, differential clock D flip−flop. The device is pin and functionally equivalent to the EL52 device. Data enters the master portion of the ...

Page 2

Flip-Flop CLK 3 CLK 4 Figure 1. 8−Lead Pinout (Top View) and Logic Diagram Table 3. ATTRIBUTES Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Moisture Sensitivity, Indefinite Time Out of Drypack ...

Page 3

Table 4. MAXIMUM RATINGS Symbol Parameter V PECL Mode Power Supply CC V NECL Mode Power Supply EE V PECL Mode Input Voltage I NECL Mode Input Voltage I Output Current out I V Sink/Source Operating Temperature ...

Page 4

Table 6. 10EP DC CHARACTERISTICS, PECL Symbol Characteristic I Power Supply Current EE V Output HIGH Voltage (Note Output LOW Voltage (Note Input HIGH Voltage (Single−Ended Input LOW Voltage (Single−Ended ...

Page 5

Table 8. 100EP DC CHARACTERISTICS, PECL Symbol Characteristic I Power Supply Current EE V Output HIGH Voltage (Note 13 Output LOW Voltage (Note 13 Input HIGH Voltage (Single−Ended Input LOW Voltage (Single−Ended ...

Page 6

Table 10. 100EP DC CHARACTERISTICS, NECL Symbol Characteristic I Power Supply Current EE V Output HIGH Voltage (Note 19 Output LOW Voltage (Note 19 Input HIGH Voltage (Single−Ended Input LOW Voltage (Single−Ended ...

Page 7

V 0.8 3.3 V 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0.0 0.5 1.0 1.5 FREQUENCY (MHz) Figure Driver Device Figure 3. Typical ...

Page 8

... ORDERING INFORMATION Device MC10EP52D MC10EP52DG MC10EP52DR2 MC10EP52DR2G MC10EP52DT MC10EP52DTG MC10EP52DTR2 MC10EP52DTR2G MC10EP52MNR4 MC10EP52MNR4G MC100EP52D MC100EP52DG MC100EP52DR2 MC100EP52DR2G MC100EP52DT MC100EP52DTG MC100EP52DTR2 MC100EP52DTR2G MC100EP52MNR4 MC100EP52MNR4G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D ...

Page 9

Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPSt I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ...

Page 10

... C SEATING PLANE −Z− 0.25 (0.010 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE 0.10 (0.004) ...

Page 11

K 8x REF 0.10 (0.004) 0.15 (0.006 L −U− PIN 1 IDENT 0.15 (0.006 −V− C 0.10 (0.004) D −T− G SEATING PLANE PACKAGE DIMENSIONS TSSOP−8 ...

Page 12

... Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303− ...

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