MC10EP57 ON Semiconductor, MC10EP57 Datasheet

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MC10EP57

Manufacturer Part Number
MC10EP57
Description
3.3V / 5V ECL 4:1 Differential Multiplexer
Manufacturer
ON Semiconductor
Datasheet

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MC10EP57DTG
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MC10EP57, MC100EP57
3.3V / 5V ECL 4:1
Differential Multiplexer
Description
leaving the SEL1 line open (pulled LOW via the input pulldown
resistors) the device can also be used as a differential 2:1 multiplexer
with SEL0 input selecting between D0 and D1. The fully differential
architecture of the EP57 makes it ideal for use in low skew
applications such as clock distribution.
applied to the select inputs will select the same numbered data input
(i.e., 00 selects D0).
generated voltage supply, is available to this device only. For
single−ended input conditions, the unused differential input is
connected to V
rebias AC coupled inputs. When used, decouple V
0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA.
When not used, V
Features
© Semiconductor Components Industries, LLC, 2006
December, 2006 − Rev. 12
The MC10/100EP57 is a fully differential 4:1 multiplexer. By
The SEL1 is the most significant select line. The binary number
Multiple V
The 100 Series contains temperature compensation.
V
V
375 ps Typical Propagation Delays
Maximum Frequency > 2 GHz Typical
PECL Mode Operating Range:
NECL Mode Operating Range:
Open Input Default State
Safety Clamp on Inputs
Q Output will default LOW with inputs open or at V
V
Useful as Either 4:1 or 2:1 Multiplexer
These are Pb−Free Devices
CC
CC
BB
= 3.0 V to 5.5 V with V
= 0 V with V
Outputs
BB
BB
outputs are provided. The V
BB
as a switching reference voltage. V
EE
should be left open.
= −3.0 V to −5.5 V
EE
= 0 V
BB
pin, an internally
BB
and V
EE
BB
may also
1
CC
via a
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
*For additional marking information, refer to
(Note: Microdot may be in either location)
Application Note AND8002/D.
CASE 948E
MN SUFFIX
CASE 485E
DT SUFFIX
TSSOP−20
QFN−20
ORDERING INFORMATION
xxx
A
L
Y
W
G
http://onsemi.com
= MC10 or 100
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
Publication Order Number:
1
DIAGRAM*
MARKING
20
ALYWG
XXXX
EP57
MC10EP57/D
ALYWG
XXXX
EP57
G
G

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MC10EP57 Summary of contents

Page 1

... MC10EP57, MC100EP57 3. ECL 4:1 Differential Multiplexer Description The MC10/100EP57 is a fully differential 4:1 multiplexer. By leaving the SEL1 line open (pulled LOW via the input pulldown resistors) the device can also be used as a differential 2:1 multiplexer with SEL0 input selecting between D0 and D1. The fully differential architecture of the EP57 makes it ideal for use in low skew applications such as clock distribution ...

Page 2

V SEL1 Warning: All V to Power Supply to guarantee proper operation. Figure 1. 20−Lead Package (Top View) and Logic Diagram NOTE: The Exposed Pad (EP) on ...

Page 3

Table 3. ATTRIBUTES Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see ...

Page 4

Table 5. 10EP DC CHARACTERISTICS, PECL Symbol Characteristic I Power Supply Current EE V Output HIGH Voltage (Note Output LOW Voltage (Note Input HIGH Voltage (Single−Ended Input LOW Voltage (Single−Ended ...

Page 5

Table 7. 10EP DC CHARACTERISTICS, NECL Symbol Characteristic I Power Supply Current EE VOH Output HIGH Voltage (Note 9) V Output LOW Voltage (Note Input HIGH Voltage (Single−Ended Input LOW Voltage (Single−Ended Output ...

Page 6

Table 9. 100EP DC CHARACTERISTICS, PECL Symbol Characteristic I Power Supply Current EE V Output HIGH Voltage (Note 15 Output LOW Voltage (Note 15 Input HIGH Voltage (Single−Ended Input LOW Voltage (Single−Ended ...

Page 7

Table 11. AC CHARACTERISTICS V Symbol Characteristic f Maximum Frequency (Figure 2) max t , Propagation Delay to PLH t Output Differential PHL COM_SEL, SEL Device to Device Skew (Note 21) SKEW t CLOCK Random Jitter ...

Page 8

... Figure 3. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) ORDERING INFORMATION Device MC10EP57DT MC10EP57DTG MC10EP57DTR2 MC10EP57DTR2G MC10EP57MNG MC10EP57MNTXG MC100EP57DT MC100EP57DTG MC100EP57DTR2 MC100EP57DTR2G MC100EP57MNG MC100EP57MNTXG †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D ...

Page 9

Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPSt I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ...

Page 10

... 0.100 (0.004) −T− SEATING PLANE 16X 0.36 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. PACKAGE DIMENSIONS TSSOP−20 CASE 948E−02 ISSUE ...

Page 11

... G 0.50 BSC 0.020 BSC H 1.38 1.43 0.054 0.056 J 0.20 REF 0.008 REF K 0.00 0.05 0.000 0.002 L 0.35 0.45 0.014 0.018 M 2.00 BSC 0.079 BSC N 2.00 BSC 0.079 BSC P 1.38 1.43 0.054 0.056 R 0.60 0.80 0.024 0.031 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative MC10EP57/D ...

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