MC14012B ON Semiconductor, MC14012B Datasheet

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MC14012B

Manufacturer Part Number
MC14012B
Description
B-Suffix Series CMOS Gates
Manufacturer
ON Semiconductor
Datasheet

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MC14012B
B-Suffix Series CMOS Gates
enhancement mode devices in a single monolithic structure
(Complementary MOS). Their primary use is where low power
dissipation and/or high noise immunity is desired.
2. Maximum Ratings are those values beyond which damage to the device
3. Temperature Derating:
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, V
to the range V
either V
MAXIMUM RATINGS
April, 2000 – Rev. 3
Symbol
V
The B Series logic gates are constructed with P and N channel
I
This device contains protection circuitry to guard against damage due to high
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
Schottky TTL Load Over the Rated Temperature Range.
Suffix Devices
Supply Voltage Range = 3.0 Vdc to 18 Vdc
All Outputs Buffered
Capable of Driving Two Low–power TTL Loads or One Low–power
Double Diode Protection on All Inputs
Pin–for–Pin Replacements for Corresponding CD4000 Series B
in
in
Semiconductor Components Industries, LLC, 2000
may occur.
Plastic “P and D/DW” Packages: – 7.0 mW/ _ C From 65 _ C To 125 _ C
V
T
P
, V
, I
T
T
stg
DD
D
A
L
out
out
SS
or V
DC Supply Voltage Range
Input or Output Voltage Range
Input or Output Current
Power Dissipation,
Ambient Temperature Range
Storage Temperature Range
Lead Temperature
SS
DD
(DC or Transient)
(DC or Transient) per Pin
per Package (Note 3.)
(8–Second Soldering)
v
). Unused outputs must be left open.
(V
in
Parameter
or V
(Voltages Referenced to V
out
)
v
V
DD
.
in
and V
– 0.5 to V
– 0.5 to +18.0
SS
– 55 to +125
– 65 to +150
out
) (Note 2.)
Value
500
260
should be constrained
10
DD
+ 0.5
1
Unit
mW
mA
V
V
C
C
C
1. For ordering information on the EIAJ version of
MC14012BCP
MC14012BD
MC14012BDR2
MC14012BF
MC14012BFEL
the SOIC packages, please contact your local
ON Semiconductor representative.
Device
A
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
ORDERING INFORMATION
http://onsemi.com
CASE 751A
SOEIAJ–14
= Assembly Location
CASE 646
CASE 965
D SUFFIX
P SUFFIX
F SUFFIX
SOIC–14
PDIP–14
SOEIAJ–14
SOEIAJ–14
Package
SOIC–14
SOIC–14
PDIP–14
Publication Order Number:
14
2500/Tape & Reel
14
14
1
1
1
DIAGRAMS
MC14012BCP
MARKING
See Note 1.
See Note 1.
MC14012B
AWLYYWW
AWLYWW
AWLYWW
Shipping
2000/Box
MC14012B/D
14012B
55/Rail

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MC14012B Summary of contents

Page 1

... MC14012BD MC14012BDR2 MC14012BF MC14012BFEL 1. For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative. 1 http://onsemi.com MARKING DIAGRAMS 14 PDIP–14 MC14012BCP P SUFFIX AWLYYWW CASE 646 1 14 SOIC–14 14012B D SUFFIX AWLYWW CASE 751A 1 14 SOEIAJ–14 ...

Page 2

... To calculate total supply current at loads other than 50 pF (50 pF – 50) Vfk where (per package pF package. MC14012B MC14012B Dual 4–Input NAND Gate V DD OUT ...

Page 3

... INPUT OUTPUT C L OUTPUT INVERTING OUTPUT NON–INVERTING . CIRCUIT SCHEMATIC MC14012B One of Two Gates Shown SAME AS ABOVE * Inverter omitted http://onsemi.com 3 Î Î Î Î Î Î Î Î Î Î Î ...

Page 4

... V , DRAIN–TO–SOURCE VOLTAGE (Vdc) DS Figure Vdc GS These typical curves are not guarantees, but are design aids. Caution: The maximum rating for output current per pin. MC14012B P–CHANNEL DRAIN CURRENT (SOURCE) – 10 – 9.0 – 8.0 – 7 – – 6.0 – ...

Page 5

... Vdc out (a) Inverting Function MC14012B 10 8.0 6.0 4.0 2 2.0 4.0 Figure NOISE MARGIN The DC noise margin is defined as the input voltage range from an ideal “1” or “0” input level which does not produce output state change(s). The typical and guaranteed limit ...

Page 6

... K D SEATING 14 PL PLANE 0.25 (0.010 MC14012B PACKAGE DIMENSIONS P SUFFIX PLASTIC DIP PACKAGE CASE 646–06 ISSUE M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN B 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. ...

Page 7

... PACKAGE DIMENSIONS PLASTIC EIAJ SOIC PACKAGE VIEW 0.13 (0.005) M 0.10 (0.004) MC14012B F SUFFIX CASE 965–01 ISSUE O NOTES DETAIL P c http://onsemi.com 7 DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. CONTROLLING DIMENSION: MILLIMETER. ...

Page 8

... Email: ONlit–asia@hibbertco.com JAPAN: ON Semiconductor, Japan Customer Focus Center 4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031 Phone: 81–3–5740–2745 Email: r14525@onsemi.com ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative. http://onsemi.com 8 MC14012B/D ...

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