MC56F836 Freescale Semiconductor, Inc, MC56F836 Datasheet
MC56F836
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MC56F836 Summary of contents
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... Data Sheet Preliminary Technical Data 56F8300 16-bit Digital Signal Controllers MC56F8365 Rev. 7 01/2007 freescale.com ...
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Version History Rev 0 Pre-release, Alpha customers only Rev 1.0 Initial Public Release Rev 2.0 Added output voltage maximum value and note to clarify in expectancy note, since life expectancy is dependent on customer usage and must be determined by ...
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General Description Note: Features in italics are NOT available in the 56F8165 device. • MIPS at 60MHz core frequency • DSP and MCU functionality in a unified, C-efficient architecture • 512KB Program Flash • 4KB Program ...
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Part 1: Overview 1.1. 56F8365/56F8165 Features . . . . . . . . . . . ...
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Part 1 Overview 1.1 56F8365/56F8165 Features 1.1.1 Core • Efficient 16-bit 56800E family controller engine with dual Harvard architecture • Million Instructions Per Second (MIPS) at 60MHz core frequency Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC) • ...
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Memory Note: Features in italics are NOT available in the 56F8165 device. • Harvard architecture permits as many as three simultaneous accesses to program and data memory • Flash security protection feature • On-chip memory, including a low-cost, high-volume ...
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Two dedicated external interrupt pins • 49 General Purpose I/O (GPIO) pins; 28 pins dedicated to GPIO • External reset input pin for hardware reset • External reset output pin for system reset • Integrated low-voltage interrupt module • ...
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Program and Data Flash memory areas. Both Program and Data Flash memories can be independently bulk erased or erased in pages. Program Flash page erase size is 1KB. Boot and Data Flash page erase size is ...
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PWM frequency. Edge-aligned and center-aligned synchronous pulse width control (0% to 100% modulation) is supported. The device is capable of controlling most motor types: ACIM (AC Induction Motors); both BDC and BLDC (Brush and ...
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Architecture Block Diagram Note: Features in italics are NOT available in the 56F8165 device and are shaded in the following figures. The 56F8365/56F8165 architecture is shown in 56800E system buses communicate with internal memories and the IPBus Bridge. internal ...
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JTAG / EOnCE CHIP TAP Controller TAP Linking Module External JTAG Port NOT available on the 56F8165 device. * EMI not functional in this package; since only part of the address/data bus is bonded out, use as GPIO pins ...
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CLKGEN (OSC/PLL) Timer A 4 Quadrature Decoder 0 4 Timer D Timer B 4 Quadrature Decoder 1 SPI1 4 SPI0 2 SCI0 2 SCI1 NOT available on the 56F8165 device. 12 To/From IPBus Bridge GPIOA GPIOB GPIOC ch3i GPIOD ch3i ...
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Name pdb_m[15:0] Program data bus for instruction word fetches or read operations. cdbw[15:0] Primary core data bus used for program memory writes. (Only these 16 bits of the cdbw[31:0] bus are used for writes to program memory.) pab[20:0] Program memory ...
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... Distribution Table 1-3 Chip Documentation Description Logic State True False True False are defined by individual product specifications. 56F8365 Technical Data, Rev. 7 Centers, or online Order Number DSP56800EERM MC56F8300UM MC56F83xxBLUM MC56F8365 MC56F8365E MC56F8165E Signal State 1 Voltage Asserted Deasserted Asserted ...
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Part 2 Signal/Connection Descriptions 2.1 Introduction The input and output signals of the 56F8365 and 56F8165 are organized into functional groups, as detailed in Table 2-1 and as illustrated in present on a pin. Table 2-1 Functional Group Pin Allocations ...
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Power Power V DDA_OSC_PLL V Power DDA_ADC Ground V Ground SSA_ADC OCR_DIS Other CAP Supply V 1 & Ports CLKMODE PLL EXTAL and Clock * External A8 - A13 (GPIOA0 - 5) Address Bus ...
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Power V Power DDA_ADC V Power DDA_OSC_PLL Ground V Ground SSA_ADC OCR_DIS Other CAP Supply V 1 & Ports CLKMODE PLL and Clock A8 - A13 (GPIOA0 - 5) * External Address GPIOB0-4 (A16 ...
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Signal Pins After reset, each pin is configured for its primary function (listed first). Any alternate functionality must be programmed. EMI is not functional in this package; since only part of the address/data bus is bonded out, use as ...
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Table 2-2 Signal and Package Information for the 128-Pin LQFP (Continued) Signal Pin No. Type Name V 95 Supply SSA_ADC OCR_DIS 71 Input Supply CAP V 2 122 CAP CAP CAP ...
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Table 2-2 Signal and Package Information for the 128-Pin LQFP (Continued) Signal Pin No. Type Name CLKO 6 Output A8 15 Output (GPIOA0) Schmitt Input Output (GPIOA1) A10 17 (GPIOA2) A11 18 (GPIOA3) A12 19 (GPIOA4) A13 20 ...
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Table 2-2 Signal and Package Information for the 128-Pin LQFP (Continued) Signal Pin No. Type Name GPIOB4 31 Schmitt Input/ Output (A20) Output (prescaler_ Output clock Input/ Output (GPIOF0) Input/ Output D8 23 (GPIOF1 (GPIOF2) D10 ...
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Table 2-2 Signal and Package Information for the 128-Pin LQFP (Continued) Signal Pin No. Type Name GPIOD0 42 Input/ Output (CS2) Output (CAN2_TX) Open Drain Output GPIOD1 43 Schmitt Input/ Output (CS3) Output (CAN2_RX) Schmitt Input 22 State During Signal ...
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Table 2-2 Signal and Package Information for the 128-Pin LQFP (Continued) Signal Pin No. Type Name GPIOD2 44 Input/ Output (CS4) Output GPIOD3 45 (CS5) GPIOD4 46 (CS6) GPIOD5 47 (CS7) TXD0 7 Output (GPIOE0) Input/ Output RXD0 8 Input ...
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Table 2-2 Signal and Package Information for the 128-Pin LQFP (Continued) Signal Pin No. Type Name RXD1 41 Input (GPIOD7) Input/ Output TCK 115 Schmitt Input TMS 116 Schmitt Input TDI 117 Schmitt Input TDO 118 Output 24 State During ...
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Table 2-2 Signal and Package Information for the 128-Pin LQFP (Continued) Signal Pin No. Type Name TRST 114 Schmitt Input PHASEA0 127 Schmitt Input (TA0) Schmitt Input/ Output (GPIOC4) Schmitt Input/ Output PHASEB0 128 Schmitt Input (TA1) Schmitt Input/ Output ...
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Table 2-2 Signal and Package Information for the 128-Pin LQFP (Continued) Signal Pin No. Type Name INDEX0 1 Schmitt Input (TA2) Schmitt Input/ Output (GPIOC6) Schmitt Input/ Output HOME0 2 Schmitt Input (TA3) Schmitt Input/ Output (GPIOC7) Schmitt Input/ Output ...
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Table 2-2 Signal and Package Information for the 128-Pin LQFP (Continued) Signal Pin No. Type Name MOSI0 126 Input/ Output (GPIOE5) Input/ Output MISO0 125 Input/ Output (GPIOE6) Input/ Output SS0 123 Input (GPIOE7) Input/ Output Freescale Semiconductor Preliminary State ...
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Table 2-2 Signal and Package Information for the 128-Pin LQFP (Continued) Signal Pin No. Type Name PHASEA1 9 Schmitt Input (TB0) Schmitt Input/ Output (SCLK1) Schmitt Input/ Output (GPIOC0) Schmitt Input/ Output PHASEB1 10 Schmitt Input (TB1) Schmitt Input/ Output ...
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Table 2-2 Signal and Package Information for the 128-Pin LQFP (Continued) Signal Pin No. Type Name INDEX1 11 Schmitt Input (TB2) Schmitt Input/ Output (MISO1) Schmitt Input/ Output (GPIOC2) Schmitt Input/ Output HOME1 12 Schmitt Input (TB3) Schmitt Input/ Output ...
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Table 2-2 Signal and Package Information for the 128-Pin LQFP (Continued) Signal Pin No. Type Name PWMA0 58 Output PWMA1 60 PWMA2 61 PWMA3 63 PWMA4 64 PWMA5 66 ISA0 104 Schmitt Input (GPIOC8) Schmitt Input/ ISA1 105 Output (GPIOC9) ...
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Table 2-2 Signal and Package Information for the 128-Pin LQFP (Continued) Signal Pin No. Type Name ISB0 48 Schmitt Input (GPIOD10) Schmitt Input/ ISB1 50 Output (GPIOD11) ISB2 51 (GPIOD12) FAULTB0 54 Schmitt Input FAULTB1 55 FAULTB2 56 FAULTB3 57 ...
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Table 2-2 Signal and Package Information for the 128-Pin LQFP (Continued) Signal Pin No. Type Name ANB0 96 Input ANB1 97 ANB2 98 ANB3 99 ANB4 100 Input ANB5 101 ANB6 102 ANB7 103 TEMP_ 88 Output SENSE CAN_RX 121 ...
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Table 2-2 Signal and Package Information for the 128-Pin LQFP (Continued) Signal Pin No. Type Name TD0 107 Schmitt Input/ Output (GPIOE10) Schmitt Input/ TD1 108 Output (GPIOE11) TD2 109 (GPIOE12) TD3 110 (GPIOE13) IRQA 52 Schmitt Input IRQB 53 ...
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Table 2-2 Signal and Package Information for the 128-Pin LQFP (Continued) Signal Pin No. Type Name EXTBOOT Internal Schmitt Ground Input EMI_MODE Internal Schmitt Ground Input 34 State During Signal Description Reset Input, External Boot —This input is tied to ...
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Part 3 On-Chip Clock Synthesis (OCCS) 3.1 Introduction Refer to the OCCS chapter of the 56F8300 Peripheral User Manual for a full description of the OCCS. The material contained here identifies the specific features of the OCCS design. specific OCCS ...
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The crystal and associated components should be mounted as near as possible to the EXTAL and XTAL pins to minimize output distortion and start-up stabilization time. Crystal Frequency = 4 - 8MHz (optimized for 8MHz) EXTAL XTAL R z CLKMODE ...
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Resonator Frequency = 4 - 8MHz (optimized for 8MHz) 2 Terminal EXTAL XTAL R z CL1 CL2 Figure 3-3 Connecting a Ceramic Resonator Note: The OCCS_COHL bit must be set to 0 when a ceramic resonator is used. The reset ...
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Program Address Space, including the Interrupt Vector Table • Data Address Space, including the EOnCE Memory and Peripheral Memory Maps On-chip memory sizes for each device are summarized in identified in the “Use Restrictions” column of Note: Data Flash ...
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Table 4-2 OMR MB/MA Value at Reset OMR MB = OMR MA = Flash Secured EXTBOOT Pin 2,3 State Information in shaded areas not applicable to 56F8365/56F8165. 2. This bit is only configured at reset. If the ...
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Table 4-4 Program Memory Map at Reset Mode 0 ( Begin/End Internal Boot Address Internal Boot 16-Bit External Address Bus P:$1F FFFF P:$10 0000 External Program Memory P:$0F FFFF P:$05 0000 P:$04 FFFF On-Chip Program RAM P:$04 F800 ...
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The location of the vector table is determined by the Vector Base Address (VBA) register. Please see 5.6.11 for the reset value of the VBA. In some configurations, the reset address ...
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Table 4-5 Interrupt Vector Table Contents Vector Priority Peripheral Number Level 0-2 FLEXCAN 26 0-2 FLEXCAN 27 0-2 FLEXCAN 28 0-2 FLEXCAN 29 0-2 GPIOF 30 0-2 GPIOE 31 0-2 GPIOD 32 0-2 GPIOC 33 ...
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Table 4-5 Interrupt Vector Table Contents Vector Priority Peripheral Number Level TMRC 56 0-2 TMRC 57 0-2 TMRC 58 0-2 TMRC 59 0-2 TMRB 60 0-2 TMRB 61 0-2 TMRB 62 0-2 TMRB 63 0-2 TMRA 64 0-2 TMRA 65 ...
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Table 4-5 Interrupt Vector Table Contents Vector Priority Peripheral Number Level FLEXCAN2 82 0-2 FLEXCAN2 83 0-2 FLEXCAN2 84 0-2 FLEXCAN2 85 0-2 1. Two words are allocated for each entry in the vector table. This does not allow the ...
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Program Memory buses. They are controlled by one set of banked registers. Data Memory Flash resides on the Data Memory buses and is controlled separately by its own set of banked registers. The top nine words of the Program Memory ...
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Program Memory BOOT_FLASH_START + $3FFF BOOT_FLASH_START = $04_0000 PROG_FLASH_START + $03_FFFF PROG_FLASH_START + $02_0000 PROG_FLASH_START + $01_FFFF PROG_FLASH_START = $00_0000 Figure 4-1 Flash Array Memory Maps Table 4-7 shows the page and sector sizes used within each Flash memory block ...
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Table 4-8 EOnCE Memory Map (Continued) Address Register Acronym X:$FF FF8A OESCR X:$FF FF8E OBCNTR X:$FF FF90 OBMSK (32 bits) X:$FF FF91 — X:$FF FF92 OBAR2 (32 bits) X:$FF FF93 — X:$FF FF94 OBAR1 (24 bits) X:$FF FF95 — X:$FF ...
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Table 4-9 summarizes base addresses for the set of peripherals on the 56F8365 and 56F8165 devices. Peripherals are listed in order of the base address. The following tables list all of the ...
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Table 4-9 Data Memory Peripheral Base Address Map Summary (Continued) Peripheral FM FlexCAN FlexCAN2 Table 4-10 External Memory Integration Registers Address Map Register Acronym Address Offset CSBAR 0 CSBAR 1 CSBAR 2 CSBAR 3 CSBAR 4 CSBAR 5 CSBAR 6 ...
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Table 4-11 Quad Timer A Registers Address Map Register Acronym TMRA0_CMP1 TMRA0_CMP2 TMRA0_CAP TMRA0_LOAD TMRA0_HOLD TMRA0_CNTR TMRA0_CTRL TMRA0_SCR TMRA0_CMPLD1 TMRA0_CMPLD2 TMRA0_COMSCR TMRA1_CMP1 TMRA1_CMP2 TMRA1_CAP TMRA1_LOAD TMRA1_HOLD TMRA1_CNTR TMRA1_CTRL TMRA1_SCR TMRA1_CMPLD1 TMRA1_CMPLD2 TMRA1_COMSCR TMRA2_CMP1 TMRA2_CMP2 TMRA2_CAP TMRA2_LOAD TMRA2_HOLD TMRA2_CNTR TMRA2_CTRL TMRA2_SCR ...
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Table 4-11 Quad Timer A Registers Address Map (Continued) Register Acronym TMRA2_CMPLD1 TMRA2_CMPLD2 TMRA2_COMSCR TMRA3_CMP1 TMRA3_CMP2 TMRA3_CAP TMRA3_LOAD TMRA3_HOLD TMRA3_CNTR TMRA3_CTRL TMRA3_SCR TMRA3_CMPLD1 TMRA3_CMPLD2 TMRA3_COMSCR Table 4-12 Quad Timer B Registers Address Map Quad Timer B is NOT available in ...
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Table 4-12 Quad Timer B Registers Address Map (Continued) Quad Timer B is NOT available in the 56F8165 device Register Acronym TMRB1_CMP1 TMRB1_CMP2 TMRB1_CAP TMRB1_LOAD TMRB1_HOLD TMRB1_CNTR TMRB1_CTRL TMRB1_SCR TMRB1_CMPLD1 TMRB1_CMPLD2 TMRB1_COMSCR TMRB2_CMP1 TMRB2_CMP2 TMRB2_CAP TMRB2_LOAD TMRB2_HOLD TMRB2_CNTR TMRB2_CTRL TMRB2_SCR ...
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Table 4-12 Quad Timer B Registers Address Map (Continued) Quad Timer B is NOT available in the 56F8165 device Register Acronym TMRB3_SCR TMRB3_CMPLD1 TMRB3_CMPLD2 TMRB3_COMSCR Table 4-13 Quad Timer C Registers Address Map Register Acronym TMRC0_CMP1 TMRC0_CMP2 TMRC0_CAP TMRC0_LOAD TMRC0_HOLD ...
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Table 4-13 Quad Timer C Registers Address Map (Continued) Register Acronym TMRC2_CMP1 TMRC2_CMP2 TMRC2_CAP TMRC2_LOAD TMRC2_HOLD TMRC2_CNTR TMRC2_CTRL TMRC2_SCR TMRC2_CMPLD1 TMRC2_CMPLD2 TMRC2_COMSCR TMRC3_CMP1 TMRC3_CMP2 TMRC3_CAP TMRC3_LOAD TMRC3_HOLD TMRC3_CNTR TMRC3_CTRL TMRC3_SCR TMRC3_CMPLD1 TMRC3_CMPLD2 TMRC3_COMSCR Table 4-14 Quad Timer D Registers Address ...
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Table 4-14 Quad Timer D Registers Address Map (Continued) Quad Timer D is NOT available in the 56F8165 device Register Acronym TMRD0_LOAD TMRD0_HOLD TMRD0_CNTR TMRD0_CTRL TMRD0_SCR TMRD0_CMPLD1 TMRD0_CMPLD2 TMRD0_COMSCR TMRD1_CMP1 TMRD1_CMP2 TMRD1_CAP TMRD1_LOAD TMRD1_HOLD TMRD1_CNTR TMRD1_CTRL TMRD1_SCR TMRD1_CMPLD1 TMRD1_CMPLD2 TMRD1_COMSCR ...
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Table 4-14 Quad Timer D Registers Address Map (Continued) Quad Timer D is NOT available in the 56F8165 device Register Acronym TMRD3_CMP1 TMRD3_CMP2 TMRD3_CAP TMRD3_LOAD TMRD3_HOLD TMRD3_CNTR TMRD3_CTRL TMRD3_SCR TMRD3_CMPLD1 TMRD3_CMPLD2 TMRD3_COMSCR Table 4-15 Pulse Width Modulator A Registers Address ...
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Table 4-15 Pulse Width Modulator A Registers Address Map (Continued) PWMA is NOT available in the 56F8165 device Register Acronym PWMA_PMDISMAP2 PWMA_PMCFG PWMA_PMCCR PWMA_PMPORT PWMA_PMICCR Table 4-16 Pulse Width Modulator B Registers Address Map Register Acronym PWMB_PMCTL PWMB_PMFCTL PWMB_PMFSA PWMB_PMOUT ...
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Table 4-17 Quadrature Decoder 0 Registers Address Map Register Acronym DEC0_DECCR DEC0_FIR DEC0_WTR DEC0_POSD DEC0_POSDH DEC0_REV DEC0_REVH DEC0_UPOS DEC0_LPOS DEC0_UPOSH DEC0_LPOSH DEC0_UIR DEC0_LIR DEC0_IMR Table 4-18 Quadrature Decoder 1 Registers Address Map Quadrature Decoder 1 is NOT available in the ...
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Table 4-18 Quadrature Decoder 1 Registers Address Map (Continued) Quadrature Decoder 1 is NOT available in the 56F8165 device Register Acronym DEC1_IMR Table 4-19 Interrupt Control Registers Address Map Register Acronym IPR 0 IPR 1 IPR 2 IPR 3 IPR ...
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Table 4-19 Interrupt Control Registers Address Map (Continued) Register Acronym IPR10 Table 4-20 Analog-to-Digital Converter Registers Address Map Register Acronym ADCA_CR1 ADCA_CR2 ADCA_ZCC ADCA_LST 1 ADCA_LST 2 ADCA_SDIS ADCA_STAT ADCA_LSTAT ADCA_ZCSTAT ADCA_RSLT 0 ADCA_RSLT 1 ADCA_RSLT 2 ADCA_RSLT 3 ADCA_RSLT ...
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Table 4-20 Analog-to-Digital Converter Registers Address Map (Continued) Register Acronym ADCA_LLMT 6 ADCA_LLMT 7 ADCA_HLMT 0 ADCA_HLMT 1 ADCA_HLMT 2 ADCA_HLMT 3 ADCA_HLMT 4 ADCA_HLMT 5 ADCA_HLMT 6 ADCA_HLMT 7 ADCA_OFS 0 ADCA_OFS 1 ADCA_OFS 2 ADCA_OFS 3 ADCA_OFS 4 ...
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Table 4-21 Analog-to-Digital Converter Registers Address Map (Continued) Register Acronym ADCB_RSLT 0 ADCB_RSLT 1 ADCB_RSLT 2 ADCB_RSLT 3 ADCB_RSLT 4 ADCB_RSLT 5 ADCB_RSLT 6 ADCB_RSLT 7 ADCB_LLMT 0 ADCB_LLMT 1 ADCB_LLMT 2 ADCB_LLMT 3 ADCB_LLMT 4 ADCB_LLMT 5 ADCB_LLMT 6 ...
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Table 4-21 Analog-to-Digital Converter Registers Address Map (Continued) Register Acronym ADCB_POWER ADCB_CAL Table 4-22 Temperature Sensor Register Address Map Temperature Sensor is NOT available in the 56F8165 device Register Acronym TSENSOR_CNTL Table 4-23 Serial Communication Interface 0 Registers Address Map ...
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Table 4-25 Serial Peripheral Interface 0 Registers Address Map (Continued) Register Acronym SPI0_SPDSR SPI0_SPDRR SPI0_SPDTR Table 4-26 Serial Peripheral Interface 1 Registers Address Map Register Acronym SPI1_SPSCR SPI1_SPDSR SPI1_SPDRR SPI1_SPDTR Table 4-27 Computer Operating Properly Registers Address Map Register Acronym ...
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Table 4-29 GPIOA Registers Address Map Register Acronym GPIOA_PUR GPIOA_DR GPIOA_DDR GPIOA_PER GPIOA_IAR GPIOA_IENR GPIOA_IPOLR GPIOA_IPR GPIOA_IESR GPIOA_PPMODE GPIOA_RAWDATA Table 4-30 GPIOB Registers Address Map Register Acronym GPIOB_PUR GPIOB_DR GPIOB_DDR GPIOB_PER GPIOB_IAR GPIOB_IENR GPIOB_IPOLR GPIOB_IPR GPIOB_IESR GPIOB_PPMODE GPIOB_RAWDATA Table 4-31 ...
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Table 4-31 GPIOC Registers Address Map (Continued) Register Acronym GPIOC_DR GPIOC_DDR GPIOC_PER GPIOC_IAR GPIOC_IENR GPIOC_IPOLR GPIOC_IPR GPIOC_IESR GPIOC_PPMODE GPIOC_RAWDATA Table 4-32 GPIOD Registers Address Map Register Acronym Address Offset GPIOD_PUR GPIOD_DR GPIOD_DDR GPIOD_PER GPIOD_IAR GPIOD_IENR GPIOD_IPOLR GPIOD_IPR GPIOD_IESR GPIOD_PPMODE GPIOD_RAWDATA ...
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Table 4-33 GPIOE Registers Address Map (Continued) Register Acronym Address Offset GPIOE_DDR GPIOE_PER GPIOE_IAR GPIOE_IENR GPIOE_IPOLR GPIOE_IPR GPIOE_IESR GPIOE_PPMODE GPIOE_RAWDATA Table 4-34 GPIOF Registers Address Map Register Acronym GPIOF_PUR GPIOF_DR GPIOF_DDR GPIOF_PER GPIOF_IAR GPIOF_IENR GPIOF_IPOLR GPIOF_IPR GPIOF_IESR GPIOF_PPMODE GPIOF_RAWDATA Table ...
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Table 4-35 System Integration Module Registers Address Map (Continued) Register Acronym SIM_SCR1 SIM_SCR2 SIM_SCR3 SIM_MSH_ID SIM_LSH_ID SIM_PUDR SIM_CLKOSR SIM_GPS SIM_PCE SIM_ISALH SIM_ISALL SIM_PCE2 Table 4-36 Power Supervisor Registers Address Map Register Acronym LVI_CONTROL LVI_STATUS Table 4-37 Flash Module Registers Address ...
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Table 4-37 Flash Module Registers Address Map (Continued) Register Acronym FMPROTB FMUSTAT FMCMD FMOPT 0 FMOPT 1 FMOPT 2 Table 4-38 FlexCAN Registers Address Map FlexCAN is NOT available in the 56F8165 device Register Acronym FCMCR FCCTL0 FCCTL1 FCTMR FCMAXMB ...
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Table 4-38 FlexCAN Registers Address Map (Continued) FlexCAN is NOT available in the 56F8165 device Register Acronym FCIFLAG1 FCR/T_ERROR_CNTRS FCMB0_CONTROL FCMB0_ID_HIGH FCMB0_ID_LOW FCMB0_DATA FCMB0_DATA FCMB0_DATA FCMB0_DATA FCMSB1_CONTROL FCMSB1_ID_HIGH FCMSB1_ID_LOW FCMB1_DATA FCMB1_DATA FCMB1_DATA FCMB1_DATA FCMB2_CONTROL FCMB2_ID_HIGH FCMB2_ID_LOW FCMB2_DATA FCMB2_DATA FCMB2_DATA FCMB2_DATA ...
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Table 4-38 FlexCAN Registers Address Map (Continued) FlexCAN is NOT available in the 56F8165 device Register Acronym FCMB3_DATA FCMB3_DATA FCMB3_DATA FCMB3_DATA FCMB4_CONTROL FCMB4_ID_HIGH FCMB4_ID_LOW FCMB4_DATA FCMB4_DATA FCMB4_DATA FCMB4_DATA FCMB5_CONTROL FCMB5_ID_HIGH FCMB5_ID_LOW FCMB5_DATA FCMB5_DATA FCMB5_DATA FCMB5_DATA FCMB6_CONTROL FCMB6_ID_HIGH FCMB6_ID_LOW FCMB6_DATA FCMB6_DATA ...
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Table 4-38 FlexCAN Registers Address Map (Continued) FlexCAN is NOT available in the 56F8165 device Register Acronym FCMB6_DATA FCMB7_CONTROL FCMB7_ID_HIGH FCMB7_ID_LOW FCMB7_DATA FCMB7_DATA FCMB7_DATA FCMB7_DATA FCMB8_CONTROL FCMB8_ID_HIGH FCMB8_ID_LOW FCMB8_DATA FCMB8_DATA FCMB8_DATA FCMB8_DATA FCMB9_CONTROL FCMB9_ID_HIGH FCMB9_ID_LOW FCMB9_DATA FCMB9_DATA FCMB9_DATA FCMB9_DATA FCMB10_CONTROL ...
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Table 4-38 FlexCAN Registers Address Map (Continued) FlexCAN is NOT available in the 56F8165 device Register Acronym FCMB10_DATA FCMB10_DATA FCMB11_CONTROL FCMB11_ID_HIGH FCMB11_ID_LOW FCMB11_DATA FCMB11_DATA FCMB11_DATA FCMB11_DATA FCMB12_CONTROL FCMB12_ID_HIGH FCMB12_ID_LOW FCMB12_DATA FCMB12_DATA FCMB12_DATA FCMB12_DATA FCMB13_CONTROL FCMB13_ID_HIGH FCMB13_ID_LOW FCMB13_DATA FCMB13_DATA FCMB13_DATA FCMB13_DATA ...
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Table 4-38 FlexCAN Registers Address Map (Continued) FlexCAN is NOT available in the 56F8165 device Register Acronym FCMB14_DATA FCMB14_DATA FCMB15_CONTROL FCMB15_ID_HIGH FCMB15_ID_LOW FCMB15_DATA FCMB15_DATA FCMB15_DATA FCMB15_DATA Table 4-39 FlexCAN2 Registers Address Map FlexCAN2 is NOT available in the 56F8165 device ...
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Table 4-39 FlexCAN2 Registers Address Map (Continued) FlexCAN2 is NOT available in the 56F8165 device Register Acronym FC2IFLAG1 FC2R/T_ERROR_CNTRS FC2IFLAG 2 FC2MB0_CONTROL FC2MB0_ID_HIGH FC2MB0_ID_LOW FC2MB0_DATA FC2MB0_DATA FC2MB0_DATA FC2MB0_DATA FC2MSB1_CONTROL FC2MSB1_ID_HIGH FC2MSB1_ID_LOW FC2MB1_DATA FC2MB1_DATA FC2MB1_DATA FC2MB1_DATA FC2MB2_CONTROL FC2MB2_ID_HIGH FC2MB2_ID_LOW FC2MB2_DATA FC2MB2_DATA ...
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Table 4-39 FlexCAN2 Registers Address Map (Continued) FlexCAN2 is NOT available in the 56F8165 device Register Acronym FC2MB3_ID_LOW FC2MB3_DATA FC2MB3_DATA FC2MB3_DATA FC2MB3_DATA FC2MB4_CONTROL FC2MB4_ID_HIGH FC2MB4_ID_LOW FC2MB4_DATA FC2MB4_DATA FC2MB4_DATA FC2MB4_DATA FC2MB5_CONTROL FC2MB5_ID_HIGH FC2MB5_ID_LOW FC2MB5_DATA FC2MB5_DATA FC2MB5_DATA FC2MB5_DATA FC2MB6_CONTROL FC2MB6_ID_HIGH FC2MB6_ID_LOW FC2MB6_DATA ...
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Table 4-39 FlexCAN2 Registers Address Map (Continued) FlexCAN2 is NOT available in the 56F8165 device Register Acronym FC2MB7_ID_LOW FC2MB7_DATA FC2MB7_DATA FC2MB7_DATA FC2MB7_DATA FC2MB8_CONTROL FC2MB8_ID_HIGH FC2MB8_ID_LOW FC2MB8_DATA FC2MB8_DATA FC2MB8_DATA FC2MB8_DATA FC2MB9_CONTROL FC2MB9_ID_HIGH FC2MB9_ID_LOW FC2MB9_DATA FC2MB9_DATA FC2MB9_DATA FC2MB9_DATA FC2MB10_CONTROL FC2MB10_ID_HIGH FC2MB10_ID_LOW FC2MB10_DATA ...
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Table 4-39 FlexCAN2 Registers Address Map (Continued) FlexCAN2 is NOT available in the 56F8165 device Register Acronym FC2MB10_DATA FC2MB10_DATA FC2MB10_DATA FC2MB11_CONTROL FC2MB11_ID_HIGH FC2MB11_ID_LOW FC2MB11_DATA FC2MB11_DATA FC2MB11_DATA FC2MB11_DATA FC2MB12_CONTROL FC2MB12_ID_HIGH FC2MB12_ID_LOW FC2MB12_DATA FC2MB12_DATA FC2MB12_DATA FC2MB12_DATA FC2MB13_CONTROL FC2MB13_ID_HIGH FC2MB13_ID_LOW FC2MB13_DATA FC2MB13_DATA FC2MB13_DATA ...
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Table 4-39 FlexCAN2 Registers Address Map (Continued) FlexCAN2 is NOT available in the 56F8165 device Register Acronym FC2MB14_DATA FC2MB14_DATA FC2MB14_DATA FC2MB15_CONTROL FC2MB15_ID_HIGH FC2MB15_ID_LOW FC2MB15_DATA FC2MB15_DATA FC2MB15_DATA FC2MB15_DATA 4.8 Factory Programmed Memory The Boot Flash memory block is programmed during manufacturing ...
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Features The ITCN module design includes these distinctive features: • Programmable priority levels for each IRQ • Two programmable Fast Interrupts • Notification to SIM module to restart clocks out of Wait and Stop modes • Drives initial address ...
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Table 5-2. Interrupt Priority Encoding IPIC_LEVEL[1: See IPIC field definition in 5.3.3 Fast Interrupt Handling Fast interrupts are described in the DSP56800E Reference Manual. The interrupt controller recognizes fast interrupts before the core does. A fast interrupt ...
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Block Diagram Priority Level 2 -> 4 INT1 Decode Priority Level 2 -> 4 INT82 Decode Figure 5-1 Interrupt Controller Block Diagram 5.5 Operating Modes The ITCN module design contains two major modes of operation: • Functional Mode The ...
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Register Descriptions A register address is the sum of a base address and an address offset. The base address is defined at the system level and the address offset is defined at the module level. The ITCN peripheral has ...
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Add. Register Offset Name IPR0 BKPT_U0 IPL IPR1 IPR2 FMCBE IPL FMCC IPL IPR3 GPIOD IPL GPIOE IPL W R SPI0_RCV ...
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Add. Register Offset Name $1F IPR10 W = Reserved Figure 5-2 ITCN Register Map Summary 5.6.1 Interrupt Priority Register 0 (IPR0) Base + $ Read 0 0 BKPT_U0IPL Write RESET ...
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Reserved—Bits 9–0 This bit field is reserved or not implemented read as 0 and cannot be modified by writing. 5.6.2 Interrupt Priority Register 1 (IPR1) Base + $ Read Write RESET ...
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It is disabled by default. • IRQ disabled (default) • IRQ is priority level 1 • IRQ is priority level 2 • IRQ is priority level 3 5.6.3 Interrupt Priority Register 2 ...
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IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 5.6.3.4 PLL Loss of Lock Interrupt Priority Level (LOCK IPL)—Bits ...
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IRQ is priority level 1 • IRQ is priority level 2 5.6.4 Interrupt Priority Register 3 (IPR3) Base + $ Read GPIOD GPIOE IPL IPL Write RESET Figure 5-6 ...
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FlexCAN Message Buffer Interrupt Priority Level (FCMSGBUF IPL)— Bits 9–8 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • ...
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Interrupt Priority Register 4 (IPR4) Base + $ Read SPI0_RCV SPI1_XMIT IPL Write RESET Figure 5-7 Interrupt Priority Register 4 (IPR4) 5.6.5.1 SPI 0 Receiver Full Interrupt Priority Level (SPI0_RCV IPL)—Bits 15–14 This ...
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IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 5.6.5.6 GPIOB Interrupt Priority Level (GPIOB IPL)—Bits 3–2 This field is used to set the interrupt ...
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Quadrature Decoder 1 HOME Signal Transition or Watchdog Timer Interrupt Priority Level (DEC1_HIRQ IPL)—Bits 13–12 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled ...
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IRQ is priority level 1 • IRQ is priority level 2 5.6.6.7 SCI 1 Transmitter Empty Interrupt Priority Level (SCI1_XMIT IPL)— Bits 3–2 This field is used to set the interrupt priority level for IRQs. ...
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IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 5.6.7.3 Timer D, Channel 2 Interrupt Priority Level (TMRD2 IPL)—Bits ...
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IRQ is priority level 1 • IRQ is priority level 2 5.6.7.8 Quadrature Decoder 0, HOME Signal Transition or Watchdog Timer Interrupt Priority Level (DEC0_HIRQ IPL)—Bits 1–0 This field is used to set the interrupt ...
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IRQ is priority level 1 • IRQ is priority level 2 5.6.8.4 Timer B, Channel 1 Interrupt Priority Level (TMRB1 IPL)—Bits 9–8 This field is used to set the interrupt priority level for IRQs. This ...
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IRQ is priority level 1 • IRQ is priority level 2 5.6.9 Interrupt Priority Register 8 (IPR8) Base + $ Read SCI0_RCV SCI0_RERR IPL Write RESET Figure 5-11 Interrupt ...
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SCI0 Transmitter Empty Interrupt Priority Level (SCI0_XMIT IPL)— Bits 7–6 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • ...
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Interrupt Priority Register 9 (IPR9) Base + $ Read PWMA_F IPL PWMB_F IPL Write RESET Figure 5-12 Interrupt Priority Register 9 (IPR9) 5.6.10.1 PWM A Fault Interrupt Priority Level (PWMA_F IPL)—Bits 15–14 This ...
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IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 5.6.10.5 ADC A Zero Crossing or Limit Error Interrupt Priority Level (ADCA_ZC IPL)—Bits 7–6 This field ...
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Vector Base Address Register (VBA) Base + $ Read Write RESET Figure 5-13 Vector Base Address Register (VBA) 5.6.11.1 Reserved—Bits 15–13 This bit field is reserved or not implemented. It ...
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Fast Interrupt 0 Vector Address Low Register (FIVAL0) Base + $ Read Write RESET Figure 5-15 Fast Interrupt 0 Vector Address Low Register (FIVAL0) 5.6.13.1 Fast Interrupt 0 Vector Address Low (FIVAL0)—Bits 15–0 ...
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Part 5.3.3. IRQs used as fast interrupts must be set to priority level 2. Unexpected results will occur if a fast interrupt vector is set to any other priority. Fast interrupts automatically become the highest-priority level 2 interrupt, ...
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IRQ pending for this vector number • IRQ pending for this vector number 5.6.18.2 Reserved—Bit 0 This bit is reserved or not implemented read as 1 and cannot be modified ...
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IRQ Pending 3 Register (IRQP3) Base + $ Read Write RESET Figure 5-23 IRQ Pending 3 Register (IRQP3) 5.6.21.1 IRQ Pending (PENDING)—Bits 64–49 This register combines with the other five to represent the ...
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IRQ Pending (PENDING)—Bits 81–85 This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 85. • IRQ pending for this vector number • IRQ pending for ...
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IRQ was taken. This field is only updated when the 56800E core jumps to a new interrupt service routine. Note: Nested interrupts may cause this field to be updated before the original interrupt service ...
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IRQA interrupt is a low-level sensitive (default) • IRQA interrupt is falling-edge sensitive. 5.6.31 Reserved —Base + $1E 5.6.32 Interrupt Priority Register 10 (IPR10) Base + $ Read Write ...
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IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 5.6.32.5 FlexCAN2 Bus-Off Interrupt Priority Level (FlexCAN2_BOFF IPL)— Bits 1 ...
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Part 6 System Integration Module (SIM) 6.1 Introduction The SIM module is a system catchall for the glue logic that ties together the system-on-chip. It controls distribution of resets and clocks and provides a number of control features. The system ...
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Reset Mode, which has two submodes: — POR and RESET operation The 56800E core and all peripherals are reset. This occurs when the internal POR is asserted or the RESET pin is asserted. — COP reset and software reset ...
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Register Descriptions Table 6-1 SIM Registers (SIM_BASE = $00 F350) Address Offset Address Acronym Base + $0 SIM_CONTROL Base + $1 SIM_RSTSTS Base + $2 SIM_SCR0 Base + $3 SIM_SCR1 Base + $4 SIM_SCR2 Base + $5 SIM_SCR3 Base ...
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Add. Register Offset Name SIM_ $0 CONTROL SIM_ $1 RSTSTS SIM_SCR0 SIM_SCR1 SIM_SCR2 SIM_SCR3 SIM_MSH_ ...
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Software Reset (SW RST)—Bit 4 This bit is always read as 0. Writing this bit will cause the part to reset. 6.5.1.4 Stop Disable (STOP_DISABLE)—Bits 3–2 • Stop mode will be entered when the ...
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External Reset (EXTR)—Bit the EXTR bit indicates an external system reset has occurred. This bit will be cleared by a Power-On Reset or by software. Writing this bit position will set the bit, ...
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Least Significant Half of JTAG ID (SIM_LSH_ID) This read-only register displays the least significant half of the JTAG ID for the chip. This register reads $D01D. Base + $ Read Write RESET 1 ...
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RESET—Bit 11 This bit controls the pull-up resistors on the RESET pin. 6.5.6.6 IRQ—Bit 10 This bit controls the pull-up resistors on the IRQA and IRQB pins. 6.5.6.7 XBOOT—Bit 9 This bit controls the pull-up resistors on the EXTBOOT ...
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This can be changed by altering [A23:A20], as shown in Base + $ Read Write RESET Figure 6-9 CLKO Select Register (SIM_CLKOSR) 6.5.7.1 Reserved—Bits 15–10 This bit field is reserved ...
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Reserved for factory test—DFLASH clock • 00111 = Oscillator output • 01000 = F (from OCCS) out • 01001 = Reserved for factory test—IPB clock • 01010 = Reserved for factory test—Feedback (from OCCS, this is path ...
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Quad Timer Controlled SPI Controlled Figure 6-10 Overall Control of GPIOC Pads Using SIM_GPS Control Table 6-2 Control of GPIOC Pads Using SIM_GPS Control Pin Function GPIO Input GPIO Output Quad Timer Input / Quad 2 Decoder Input Quad Timer ...
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EMI Controlled CAN2 Controlled Figure 6-11 Overall Control of GPIOD Pads Using SIM_GPS Control Table 6-3 Control of GPIOD Pads Using SIM_GPS Control Pin Function GPIO Input 0 GPIO Output 0 EMI I/O 1 CAN2 1 1. This applies to ...
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GPIOD1 (D1)—Bit 5 This bit selects the alternate function for GPIOD1. • CS3 • CAN2_RX 6.5.8.3 GPIOD0 (D0)—Bit 4 • CS2 • CAN2_TX 6.5.8.4 GPIOC3 (C3)—Bit 3 This bit selects the ...
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Base + $ Read EMI ADCB ADCA CAN DEC1 DEC0 Write RESET Figure 6-13 Peripheral Clock Enable Register (SIM_PCE) 6.5.9.1 External Memory Interface Enable (EMI)—Bit 15 Each bit controls clocks to the indicated peripheral. ...
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Quad Timer D Enable (TMRD)—Bit 9 Each bit controls clocks to the indicated peripheral. • Clocks are enabled • The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.8 Quad Timer C ...
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The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.15 Pulse Width Modulator B Enable (PWMB)—Bit 1 Each bit controls clocks to the indicated peripheral. • Clocks are enabled • ...
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Base + $ Read Write RESET Figure 6-15 I/O Short Address Location High Register (SIM_ISALH) 6.5.10.1 Input/Output Short Address Low (ISAL[23:22])—Bit 1–0 This field represents the upper two address bits of ...
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Clock Generation Overview The SIM uses an internal master clock from the OCCS (CLKGEN) module to produce the peripheral and system (core and memory) clocks. The maximum master clock frequency is 120MHz. Peripheral and system clocks are generated at ...
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Stop and Wait Mode Disable Function Permanent Disable Reprogrammable Disable Clock Select Figure 6-17 Internal Stop Disable Circuit The 56800E core contains both STOP and WAIT instructions. Both put the CPU to sleep. For lowest power consumption in Stop ...
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Resets may be asserted asynchronously, but are always released internally on a rising edge of the system clock. Part 7 Security Features The 56F8365/56F8165 offers security features intended to prevent unauthorized users from reading the contents of the Flash Memory ...
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Proper implementation of Flash security requires that no access to the EOnCE port is provided when security is enabled. The 56800E core has an input which disables reading of internal memory via the JTAG/EOnCE. The FM sets this input at ...
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Two examples of FM_CLKDIV calculations follow. EXAMPLE 1: If the system clock is the 8MHz crystal frequency because the PLL has not been set up, the input clock will be below 12.8MHz, so PRDIV8 = FM_CLKDIV[ Using the ...
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Part 8 General Purpose Input/Output (GPIO) 8.1 Introduction This section is intended to supplement the GPIO information found in the 56F8300 Peripheral User Manual and contains only chip-specific information. This information supercedes the generic information in the 56F8300 Peripheral User ...
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Table 8-1 56F8365 GPIO Ports Configuration Available Port GPIO Port Pins in Width 56F8365 Table 8-2 56F8165 GPIO Ports Configuration Available Port GPIO Port Pins in Width 56F8165 ...
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Table 8-3 GPIO External Signals Map Pins in shaded rows are not available in 56F8365 / 56F8165 Pins in italics are NOT available in the 56F8165 device GPIO Port GPIO Bit GPIOA 7 ...
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Table 8-3 GPIO External Signals Map (Continued) Pins in shaded rows are not available in 56F8365 / 56F8165 Pins in italics are NOT available in the 56F8165 device GPIO Port GPIO Bit GPIOC 5 6 ...
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Table 8-3 GPIO External Signals Map (Continued) Pins in shaded rows are not available in 56F8365 / 56F8165 Pins in italics are NOT available in the 56F8165 device GPIO Port GPIO Bit GPIO D ...
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Table 8-3 GPIO External Signals Map (Continued) Pins in shaded rows are not available in 56F8365 / 56F8165 Pins in italics are NOT available in the 56F8165 device GPIO Port GPIO Bit ...
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In such systems, a bus may carry both 3.3V- and 5V-compatible I/O voltage levels (a standard 3.3V I/O is designed to receive a maximum voltage of 3.3V ± 10% during normal ...
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Table 10-1 Absolute Maximum Ratings (Continued) Characteristic Ambient Temperature (Automotive) Ambient Temperature (Industrial) Junction Temperature (Automotive) Junction Temperature (Industrial) Storage Temperature (Automotive) Storage Temperature (Industrial corresponding GPIO pin is configured as open drain. Note: Pins in italics are ...
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Table 10-2 56F8365/56F8165 ElectroStatic Discharge (ESD) Protection Characteristic ESD for Human Body Model (HBM) ESD for Machine Model (MM) ESD for Charge Device Model (CDM) Characteristic Junction to ambient Natural convection Junction to ambient (@1m/sec) Junction to ambient Natural convection ...
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Thermal Characterization Parameter, Psi-JT (Ψ ter of case as defined in JESD51-2. Ψ vironments. 5. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other ...
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Table 10-4 Recommended Operating Conditions (V = 0V, V REFLO Characteristic Flash Endurance (Industrial) (Program Erase Cycles) Flash Data Retention (Automotive) Note: Total chip source or sink current cannot exceed 200mA See Pin Groups listed in Table 10-1 Freescale Semiconductor ...
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DC Electrical Characteristics Note: The 56F8165 device is specified to meet Industrial requirements only; CAN is NOT available on the 56F8165 device. Table 10-5 DC Electrical Characteristics At Recommended Operating Conditions; see Characteristic Symbol Output High Voltage Output Low ...
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Table 10-6 Power-On Reset Low Voltage Parameters Characteristic POR Trip Point 1 LVI, 2.5 volt Supply, trip point 2 LVI, 3.3 volt supply, trip point Bias Current 1. When V drops below V DD_CORE 2. When V drops below V ...
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Table 10-8 Current Consumption per Power Supply Pin (Typical) On-Chip Regulator Disabled (OCR_DIS = High) I Mode DD_Core RUN1_MAC 150mA Wait3 86mA Stop1 950μA Stop2 100μ Output Switching Characteristic Unloaded Output Voltage (0mA Load) Loaded Output Voltage (200mA ...
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Characteristics PLL Start-up time Resonator Start-up time Min-Max Period Variation Peak-to-Peak Jitter Bias Current Quiescent Current, power-down mode 10.2.1 Temperature Sensor Note: Temperature Sensor is NOT available in the 56F8165 device. Table 10-11 Temperature Sense Parametrics Characteristics 1 Slope (Gain) ...
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AC Electrical Characteristics Tests are conducted using the input levels specified in propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured between the 10% and 90% points, as shown in ...
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Data1 Valid Data1 Data Invalid State Data Active 10.4 Flash Memory Characteristics Table 10-12 Flash Timing Parameters Characteristic 1 Program time 2 Erase time Mass erase time 1. There is additional overhead which is part of the programming sequence. See ...
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External 90% 50% Clock 10 Note: The midpoint 10.6 Phase Locked Loop Timing Characteristic External reference crystal frequency for the PLL 2 PLL output frequency (f ) OUT 3 PLL stabilization time -40° ...
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Table 10-15 Crystal Oscillator Parameters Characteristic Bias Current, high-drive mode Bias Current, low-drive mode Quiescent Current, power-down mode 10.8 Reset, Stop, Wait, Mode Select, and Interrupt Timing Table 10-16 Reset, Stop, Wait, Mode Select, and Interrupt Timing Characteristic Minimum RESET ...
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IRQA, IRQB Figure 10-5 External Interrupt Timing (Negative Edge-Sensitive) A0–A15 t IDM , IRQA IRQB General Purpose I/O Pin IRQA IRQB Figure 10-6 External Level-Sensitive Interrupt Timing IRQA, IRQB A0–A15 Figure 10-7 Interrupt from Wait State Timing ...
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IW IRQA A0–A15 Figure 10-8 Recovery from Stop State Using Asynchronous Interrupt Timing 10.9 Serial Peripheral Interface (SPI) Timing Characteristic Cycle time Master Slave Enable lead time Master Slave Enable lag time Master Slave Clock (SCK) high time Master ...
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Characteristic Rise time Master Slave Fall time Master Slave 1. Parameters listed are guaranteed by design. SS (Input) SCLK (CPOL = 0) (Output) SCLK (CPOL = 1) (Output) t MISO (Input) MOSI (Output) Figure 10-9 SPI Master Timing (CPHA = ...
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SS (Input) SCLK (CPOL = 0) (Output) SCLK (CPOL = 1) (Output) MISO (Input) (ref MOSI (Output) Figure 10-10 SPI Master Timing (CPHA = 1) SS (Input) SCLK (CPOL = 0) (Input) SCLK (CPOL = 1) (Input) MISO ...
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SS (Input) SCLK (CPOL = 0) (Input) SCLK (CPOL = 1) (Input MISO (Output) MOSI (Input) Figure 10-12 SPI Slave Timing (CPHA = 1) 10.10 Quad Timer Timing Characteristic Timer input period Timer input high / low period ...
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Timer Inputs Timer Outputs 10.11 Quadrature Decoder Timing Table 10-19 Quadrature Decoder Timing Characteristic Quadrature input period Quadrature input high / low period Quadrature phase period 1. In the formulas listed the clock cycle. For 60MHz operation, T=16.67ns. ...
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Serial Communication Interface (SCI) Timing Characteristic Symbol 2 Baud Rate RXD 3 RXD Pulse Width TXD 4 TXD Pulse Width 1. Parameters listed are guaranteed by design the frequency of operation of the system clock, ZCLK, ...
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CAN_RX CAN receive data pin (Input) Figure 10-17 Bus Wake Up Detection 10.14 JTAG Timing Characteristic TCK frequency of operation 1 using EOnCE TCK frequency of operation not 1 using EOnCE TCK clock pulse width TMS, TDI data set-up time ...
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TCK (Input) TDI TMS (Input) TDO (Output) TDO (Output ) TDO (Output) Figure 10-19 Test Access Port Timing Diagram TRST (Input) 10.15 Analog-to-Digital Converter (ADC) Parameters Characteristic Input voltages Resolution 1 Integral Non-Linearity Differential Non-Linearity 160 t DS Input Data ...
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Table 10-23 ADC Parameters (Continued) Characteristic Monotonicity ADC internal clock Conversion range ADC channel power-up time ADC reference circuit power-up time Conversion time Sample time Input capacitance 5 Input injection current , per pin Input injection current, total V current ...
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Absolute error includes the effects of both gain error and offset error. 7. Please see the 56F8300Peripheral User’s Manual for additional information on ADC calibration. 8. ENOB = (SINAD - 1.76)/6.02 Figure 10-21 ADC Absolute Error Over Processing and ...
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Equivalent Circuit for ADC Inputs Figure 10-22 illustrates the ADC input circuit during sample and hold. S1 and S2 are always open/closed at the same time ...
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Analog Input 1 1. Parasitic capacitance due to package, pin-to-pin and pin-to-package base coupling; 1.8pf 2. Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing; 2.04pf 3. Equivalent resistance for the ESD isolation resistor and ...
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Table 10-24 IO Loading Coefficients at 10MHz PDU08DGZ_ME PDU04DGZ_ME Power due to capacitive loading on output pins is (first order) a function of the capacitive load and frequency at which the outputs change. in the IO cells as a function ...
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Part 11 Packaging 11.1 56F8365 Package and Pin-Out Information This section contains package and pin-out information for the 56F8365. This device comes in a 128-pin Low-profile Quad Flat Pack (LQFP). Figure 11-3 shows the mechanical parameters for this package, and ...
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Table 11-1 56F8365 128-Pin LQFP Package Identification by Pin Number Pin No. Signal Name Pin No. 1 INDEX0 2 HOME0 DD_IO CLKO 7 TXD0 8 RXD0 9 PHASEA1 10 PHASEB1 ...
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Table 11-1 56F8365 128-Pin LQFP Package Identification by Pin Number (Continued) Pin No. Signal Name Pin No. 28 GPIOB1 29 GPIOB2 30 GPIOB3 31 GPIOB4 32 PWMB0 11.2 56F8165 Package and Pin-Out Information This section contains package and pin-out information ...
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INDEX0 HOME0 PIN DD_IO CLKO TXD0 RXD0 SCLK1 MOSI1 MISO1 SS1 V 4 CAP V DD_IO GPIOA0 GPIOA1 GPIOA2 GPIOA3 GPIOA4 GPIOA5 V SS GPIOF0 GPIOF1 GPIOF2 V DD_IO GPIOF3 GPIOB0 GPIOB1 GPIOB2 ...
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Table 11-2 56F8165 128-Pin LQFP Package Identification by Pin Number (Continued) Pin No. Signal Name Pin No DD_IO CLKO 7 TXD0 8 RXD0 9 SCLK1 10 MOSI1 11 MISO1 12 ...
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Table 11-2 56F8165 128-Pin LQFP Package Identification by Pin Number (Continued) Pin No. Signal Name Pin No. 29 GPIOB2 30 GPIOB3 31 GPIOB4 32 PWMB0 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM ...
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... Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc. 2005, 2006. All rights reserved. MC56F8365 Rev. 7 01/2007 ...