MC68040RC33 Motorola, MC68040RC33 Datasheet
MC68040RC33
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MC68040RC33 Summary of contents
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... Freescale Semiconductor, Inc. µ MOTOROLA M68040 User’s Manual ©MOTOROLA INC., 1990 Revised 1992, 1993 For More Information On This Product, Including the MC68040, MC68040V, MC68LC040, MC68EC040, and MC68EC040V Go to: www.freescale.com ...
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... Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold ...
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... MC68040 Electrical and Thermal Characteristics Section 12 Ordering Information and Mechanical Data Appendix A MC68LC040 Appendix B MC68EC040 Appendix C MC68040V and MC68EC040V Appendix D M68000 Family Summary Appendix E Floating-Point Emulation (M68040FPSP) Index iv For More Information On This Product, PREFACE Appendices M68040 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
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... Integer Unit Supervisor Programming Model .................................... 2-5 2.2.2.1 Interrupt and Master Stack Pointers .............................................. 2-6 2.2.2.2 Status Register .............................................................................. 2-7 2.2.2.3 Vector Base Register ..................................................................... 2-7 2.2.2.4 Alternate Function Code Registers ................................................ 2-7 2.2.2.5 Cache Control Register ................................................................. 2-8 vi For More Information On This Product, Title Section 1 Introduction Section 2 Integer Unit M68040 USER’S MANUAL Go to: www.freescale.com Page Number MOTOROLA ...
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... MMU Effect on RSTI and MDIS ............................................................. 3-31 3.6.1 Effect of RSTI on the MMUs .............................................................. 3-31 3.6.2 Effect of MDIS on Address Translation .............................................. 3-31 3.7 MMU Instructions .................................................................................. 3-33 3.7.1 MOVEC ............................................................................................. 3-33 3.7.2 PFLUSH............................................................................................. 3-33 3.7.3 PTEST ............................................................................................... 3-33 3.7.4 Register Programming Considerations.............................................. 3-34 MOTOROLA For More Information On This Product, Title Section 3 Memory Management Unit M68040 USER’S MANUAL Go to: www.freescale.com Page Number vii ...
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... Transfer Size (SIZ1, SIZ0) ................................................................ 5-7 5.3.7 Lock (LOCK) ...................................................................................... 5-7 5.3.8 Lock End (LOCKE) ............................................................................ 5-7 5.3.9 Cache Inhibit Out (CIOUT) ................................................................ 5-8 5.4 Bus Transfer Control Signals ................................................................ 5-8 5.4.1 Transfer Start (TS) ............................................................................. 5-8 viii For More Information On This Product, Title Section 4 Instruction and Data Caches Section 5 Signal Description M68040 USER’S MANUAL Go to: www.freescale.com Page Number MOTOROLA ...
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... Test Data Out (TDO) ......................................................................... 5-15 5.12.5 Test Reset (TRST)—Not on MC68040V and MC68EC040V............. 5-15 5.13 Power Supply Connections ................................................................... 5-15 5.14 Signal Summary .................................................................................... 5-16 IEEE 1149.1 Test Access Port (JTAG) 6.1 Overview ............................................................................................... 6-2 6.2 Instruction Shift Register ....................................................................... 6-3 6.2.1 EXTEST ............................................................................................. 6-3 MOTOROLA For More Information On This Product, Title Section 6 M68040 USER’S MANUAL Go to: www.freescale.com Page Number ix ...
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... PRIVATE ........................................................................................... 6-5 6.2.7 DRVCTL.S......................................................................................... 6-5 6.2.8 BYPASS ............................................................................................ 6-6 6.3 Boundary Scan Register ....................................................................... 6-6 6.4 Restrictions ........................................................................................... 6-12 6.5 Disabling The IEEE Standard 1149.1A Operation ................................ 6-13 6.6 Motorola M68040 BSDL Description (Version 2.2) ............................... 6-15 6.7 MC68040, MC68LC040, MC68EC040 JTAG Electrical Characteristics .......................................................... 6-21 7.1 Bus Characteristics ............................................................................... 7-1 7.2 Data Transfer Mechanism..................................................................... 7-3 7.3 Misaligned Operands ............................................................................ 7-6 7.4 Processor Data Transfers ..................................................................... 7-9 7.4.1 Byte, Word, and Long-Word Read Transfers .................................... 7-10 7 ...
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... Floating-Point Post-Instruction Stack Frame (Format $3) ................. 8-23 8.4.5 Eight-Word Stack Frame (Format $4)................................................ 8-23 8.4.6 Access Error Stack Frame (Format $7) ............................................. 8-24 8.4.6.1 Effective Address ........................................................................... 8-24 8.4.6.2 Special Status Word (SSW) ........................................................... 8-24 8.4.6.3 Write-Back Status .......................................................................... 8-26 8.4.6.4 Fault Address ................................................................................. 8-26 MOTOROLA For More Information On This Product, Title Section 8 Exception Processing M68040 USER’S MANUAL Go to: www.freescale.com Page Number xi ...
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... Signaling Not-a-Number (SNAN)....................................................... 9-27 9.7.2.1 Maskable Exception Conditions..................................................... 9-27 9.7.2.2 Nonmaskable Exception Conditions .............................................. 9-27 9.7.3 Operand Error ................................................................................... 9-28 9.7.3.1 Maskable Exception Conditions..................................................... 9-29 9.7.3.2 Nonmaskable Exception Conditions .............................................. 9-30 9.7.4 Overflow ............................................................................................ 9-31 9.7.4.1 Maskable Exception Conditions..................................................... 9-31 9.7.4.2 Nonmaskable Exception Conditions .............................................. 9-31 xii For More Information On This Product, Title Section 9 M68040 USER’S MANUAL Go to: www.freescale.com Page Number MOTOROLA ...
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... MC68040 Die and Package ............................................................... 11-12 11.8.2 MC68040 Power Considerations ....................................................... 11-12 11.9 MC68040 Thermal Management Techniques ....................................... 11-14 11.9.1 Still Air................................................................................................ 11-17 11.9.2 Forced Air .......................................................................................... 11-18 11.9.3 With Heat Sink ................................................................................... 11-19 11.9.4 With Heat Sink and Forced Air .......................................................... 11-22 MOTOROLA For More Information On This Product, Title Section 10 Instruction Timings Section 11 M68040 USER’S MANUAL Go to: www.freescale.com Page Number xiii ...
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... Input AC Timing Specifications.......................................................... A-12 B.1 MC68EC040 Differences ...................................................................... B-4 B.2 JTAG Scan (JS1–JS0) .......................................................................... B-5 B.3 Access Control Units............................................................................. B-5 B.3.1 Access Control Registers .................................................................. B-5 B.3.2 Address Comparison ......................................................................... B-7 B.3.3 Effect of RSTI on the ACU................................................................. B-8 xiv For More Information On This Product, Title Section 12 Appendix A MC68LC040 Appendix B MC68EC040 M68040 USER’S MANUAL Go to: www.freescale.com Page Number MOTOROLA ...
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... Instruction Shift Register ................................................................... C-11 C.6.1.1 EXTEST ......................................................................................... C-12 C.6.1.2 HIGHZ ............................................................................................ C-12 C.6.1.3 SAMPLE/PRELOAD ...................................................................... C-12 C.6.1.4 CLAMP........................................................................................... C-12 C.6.1.5 BYPASS......................................................................................... C-13 C.6.2 Boundary Scan Register.................................................................... C-13 C.6.3 Restrictions ........................................................................................ C-16 C.6.4 Disabling The IEEE Standard 1149.1A Operation............................. C-16 C.6.5 MC68040V and MC68EC040V JTAG Electrical Characteristics ....... C-17 MOTOROLA For More Information On This Product, Title Appendix C MC68040V and MC68EC040V M68040 USER’S MANUAL Go to: www.freescale.com Page Number xv ...
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... Maximum Ratings .............................................................................. C-19 C.7.2 Thermal Characteristics .................................................................... C-19 C.7.3 DC Electrical Specifications .............................................................. C-20 C.7.4 Power Dissipation.............................................................................. C-20 C.7.5 Clock AC Timing Specifications ........................................................ C-21 C.7.6 Output AC Timing Specifications ....................................................... C-22 C.7.7 Input AC Timing Specifications.......................................................... C-23 Floating-Point Emulation (M68040FPSP) xvi For More Information On This Product, Title Appendix D M68000 Family Summary Appendix E Index M68040 USER’S MANUAL Go to: www.freescale.com Page Number MOTOROLA ...
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... Translation Table Using S-Bit and W-Bit To Set Protection ......................... 3-25 3-20 ATC Organization......................................................................................... 3-26 3-21 ATC Entry and Tag Fields ............................................................................ 3-27 3-22 Address Translation Flowchart..................................................................... 3-32 3-23 MMU Status Interpretation ........................................................................... 3-35 4-1 Overview of Internal Caches ........................................................................ 4-2 4-2 Cache Line Formats ..................................................................................... 4-3 4-3 Caching Operation ....................................................................................... 4-4 4-4 Cache Control Register ................................................................................ 4-5 MOTOROLA For More Information On This Product, Title M68040 USER’S MANUAL Go to: www.freescale.com Page Number xvii ...
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... Interrupt Acknowledge Bus Cycle Flowchart ............................................... 7-32 7-22 Interrupt Acknowledge Bus Cycle Timing .................................................... 7-33 7-23 Autovector Interrupt Acknowledge Bus Cycle Timing .................................. 7-34 7-24 Breakpoint Interrupt Acknowledge Bus Cycle Flowchart ............................. 7-35 7-25 Breakpoint Interrupt Acknowledge Bus Cycle Timing .................................. 7-36 xviii For More Information On This Product, Title M68040 USER’S MANUAL Go to: www.freescale.com Page Number MOTOROLA ...
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... Floating-Point User Programming Model ..................................................... 9-2 9-2 Floating-Point Control Register .................................................................... 9-4 9-3 FPSR Condition Code Byte.......................................................................... 9-4 9-4 FPSR Quotient Byte ..................................................................................... 9-5 9-5 FPSR Exception Status Byte ....................................................................... 9-5 9-6 FPSR Accrued Exception Byte .................................................................... 9-6 9-7 Intermediate Result Format.......................................................................... 9-12 9-8 Rounding Algorithm Flowchart ..................................................................... 9-14 MOTOROLA For More Information On This Product, Title M68040 USER’S MANUAL Go to: www.freescale.com Page Number xix ...
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... MC68EC040 Functional Signal Groups ....................................................... B-4 B-4 MC68EC040 Access Control Register Format ............................................ B-6 B-5 MC68EC040 Initial Power-On Reset Timing................................................ B-8 B-6 MC68EC040 Normal Reset Timing .............................................................. B-9 B-7 Clock Input Timing Diagram ......................................................................... B-14 B-8 Read/Write Timing ....................................................................................... B-17 B-9 Bus Arbitration Timing.................................................................................. B-18 xx For More Information On This Product, Title M68040 USER’S MANUAL Go to: www.freescale.com Page Number MOTOROLA ...
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... Snoop Hit Timing.......................................................................................... C-26 C-16 Snoop Miss Timing....................................................................................... C-27 C-17 Other Signal Timing ..................................................................................... C-28 C-18 Going into LPSTOP with Arbitration ............................................................. C-29 C-19 LPSTOP no Arbitration, CPU is Master ....................................................... C-30 C-20 Exiting LPSTOP with Interrupt...................................................................... C-31 C-21 Exiting of LPSTOP with RESET ................................................................... C-31 MOTOROLA For More Information On This Product, Title M68040 USER’S MANUAL Go to: www.freescale.com Page Number xxi ...
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... Interrupt Acknowledge Termination Summary ............................................. 7-31 7-5 TA and TEA Assertion Results ..................................................................... 7-37 7-6 M68040 Bus Arbitration States .................................................................... 7-48 8-1 Exception Vector Assignments .................................................................... 8-5 8-2 Tracing Control ............................................................................................ 8-11 8-3 Interrupt Levels and Mask Values................................................................ 8-12 8-4 Exception Priority Groups ............................................................................ 8-19 xxii For More Information On This Product, LIST OF TABLES Title M68040 USER’S MANUAL Go to: www.freescale.com Page Number MOTOROLA ...
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... Bus Encodings During LPSTOP Broadcast Cycle ....................................... C-4 C-3 IEEE Standard 1149.1A Instructions............................................................ C-12 E-1 MC68040 Floating-Point Instructions ........................................................... E-2 E-2 MC68040FPSP Floating-Point Instructions.................................................. E-3 E-3 Support for Data Types and Data Formats .................................................. E-4 E-4 Exception Conditions ................................................................................... E-4 MOTOROLA For More Information On This Product, Title M68040 USER’S MANUAL Go to: www.freescale.com Page Number xxiii ...
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... The M68040 family is user object-code compatible with previous M68000 family members and is specifically optimized to reduce the execution time of compiler-generated code. All five processors implement Motorola’s latest HCMOS technology, providing an ideal balance between speed, power, and physical device size. 1.1 DIFFERENCES ...
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... Refer to Appendix B MC68EC040 for specific details on the MC68EC040. Refer to Appendix B MC68EC040 and Appendix C MC68040V and MC68EC040V for specific details on the MC68EC040V. Disregard information concerning the FPU and MMU when reading the following subsections. 1-2 For More Information On This Product, M68040 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
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... Conditional branches are optimized for the ® UNIX is a registered trademark of AT&T Bell Laboratories. MOTOROLA For More Information On This Product, M68040 USER’S MANUAL Go to: www.freescale.com ® ...
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... INSTRUCTION MEMORY UNIT DATA MEMORY UNIT DATA MMU/CACHE/SNOOP CONTROLLER DATA DATA ATC CACHE OPERAND DATA BUS Figure 1-1. Block Diagram M68040 USER’S MANUAL Go to: www.freescale.com INSTRUCTION ADDRESS ADDRESS BUS DATA R BUS O L DATA L ADDRESS E R BUS CONTROL SIGNALS MOTOROLA ...
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... PROGRAMMING MODEL The MC68040 programming model is separated into two privilege modes: supervisor and user. The S-bit in the status register (SR) indicates the privilege mode that the processor MOTOROLA For More Information On This Product, M68040 USER’S MANUAL Go to: www.freescale.com ...
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... The MC68040 user programming model also incorporates the MC68881/MC68882 programming model consisting of eight, 80-bit, floating-point data registers, a floating-point control register, a floating-point status register, and a floating- point instruction address register. 1-6 For More Information On This Product, M68040 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
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... VBR SFC DFC CACR URP SRP TC DTT0 DTT1 ITT0 ITT1 MMUSR Figure 1-2. Programming Model MOTOROLA For More Information On This Product, 79 FLOATING-POINT DATA REGISTERS FP CONTROL REGISTER FP STATUS REGISTER FP INSTRUCTION ADDRESS REGISTER USER STACK POINTER PROGRAM COUNTER CONDITION CODE REGISTER USER PROGRAMMING MODEL ...
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... Instructions that do not modify the FPIAR can be used to read the FPIAR in the exception handler without changing the previous value. 1-8 For More Information On This Product, M68040 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
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... ADDRESSING CAPABILITIES SUMMARY The M68040 supports the basic addressing modes of the M68000 family. The register indirect addressing modes support postincrement, predecrement, offset, and indexing, which are particularly useful for handling data structures common to sophisticated MOTOROLA For More Information On This Product, Size Supported In ...
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... Program Counter Indirect with Index 8-Bit Displacement Base Displacement Program Counter Memory Indirect Postindexed Preindexed Absolute Data Addressing Short Long Immediate 1-10 For More Information On This Product, Syntax Dn An (An) (An)+ –(An) (d16,An ,An,Xn) (bd,An,Xn) ([bd,An],Xn,od) ([bd,An,Xn],od ,PC ,PC,Xn) (bd,PC,Xn) ([bd,PC],Xn,od) ([bd,PC,Xn],od) (xxx).W (xxx).L #<xxx> M68040 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
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... Any Address or Data Register Rx, Ry Any source and destination registers, respectively. Xn Index Register—An, Dn, or suppressed. MOTOROLA For More Information On This Product, Other Operations Offset Word ø (SSP); SSP – 2 ø SSP; PC ø (SSP); SSP – 4 ø SSP; SR Register Specification M68040 USER’S MANUAL Go to: www ...
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... Instruction, Data, or Both Caches MMUSR MMU Status Register PC Program Counter Rc Any Non Floating-Point Control Register SFC Source Function Code Register SR Status Register 1-12 For More Information On This Product, Data Format And Type Subfields and Qualifiers Register Names M68040 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
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... Table 1-3. Notational Conventions (Concluded) * General Case. C Carry Bit in CCR cc Condition Codes from CCR FC Function Code N Negative Bit in CCR U Undefined, Reserved for Motorola Use. V Overflow Bit in CCR X Extend Bit in CCR Z Zero Bit in CCR — Not Affected or Applicable. ISP Supervisor/Interrupt Stack Pointer MSP ...
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... Bcc <label> BCHG Dn,<ea> BCHG #<data>,<ea> BCLR Dn,<ea> BCLR #<data>,<ea> BFCHG <ea>{offset:width} BFCLR <ea>{offset:width} BFEXTS <ea>{offset:width},Dn BFEXTU <ea>{offset:width},Dn BFFFO <ea>{offset:width},Dn BFINS Dn,<ea>{offset:width} BFSET <ea>{offset:width} BFTST <ea>{offset:width} BKPT #<data> BRA <label> BSET Dn,<ea> BSET #<data>,<ea> BSR <label> M68040 USER’S MANUAL Go to: www.freescale.com Syntax MOTOROLA ...
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... Destination ø Destination EORI Immediate Data EORI to CCR Source CCR ø CCR EORI supervisor state then Source else TRAP MOTOROLA For More Information On This Product, Operation BTST Dn,<ea> BTST #<data>,<ea> CAS Dc,Du,<ea> CAS2 Dc1–Dc2,Du1–Du2,(Rn1)–(Rn2) CHK <ea>,Dn CHK2 <ea>,Rn CINVL <caches>, (An) CINVP < ...
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... FMOVE.L FPcr,<ea> FMOVEM.X <list>,<ea> 4 FMOVEM.X Dn,<ea> FMOVEM.X <ea>,<list> 4 FMOVEM.X <ea>,Dn FMOVEM.L <list>,<ea> 5 FMOVEM.L <ea>,<list> 5 FMUL.<fmt> <ea>,FPn FMUL.X FPm,FPn FrMUL<fmt> <ea>,FPn 3 FrMUL.X FPm,FPn 3 M68040 USER’S MANUAL Go to: www.freescale.com Syntax extend byte to word extend word to long word extend byte to long word MOTOROLA ...
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... Destination Address ø PC JSR SP – 4 ø SP; PC ø (SP) Destination Address ø PC LEA <ea> ø An LINK SP – 4 ø SP; An ø (SP) SP ø An, SP+d ø SP MOTOROLA For More Information On This Product, Operation FNEG.<fmt> <ea>,FPn FNEG.X FPm,FPn FNEG.X FPn FrNEG.<fmt> <ea>,FPn 3 FrNEG.X FPm,FPn 3 FrNEG.X FPn 3 FNOP FRESTORE < ...
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... MOVEM <ea>,<list> 4 MOVEP Dx,(d n ,Ay) MOVEP (d n ,Ay),Dx MOVEQ #<data>,Dn MOVES Rn,<ea> MOVES <ea>,Rn MULS.W <ea>,Dn MULS.L <ea>,Dl MULS.L <ea>,Dh–Dl MULU.W <ea>,Dn MULU.L <ea>,Dl MULU.L <ea>,Dh–Dl NBCD <ea> NEG <ea> NEGX <ea> M68040 USER’S MANUAL Go to: www.freescale.com Syntax 16 16 ø ø ø ø ø ø 64 MOTOROLA ...
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... If condition true then 1s ø Destination else 0s ø Destination STOP If supervisor state then Immediate Data ø SR; STOP else TRAP SUB Destination – Source ø Destination MOTOROLA For More Information On This Product, Operation NOP NOT <ea> OR <ea>,Dn OR Dn,<ea> ORI #<data>,<ea> ORI #<data>,CCR ORI #<data>,SR PACK – ...
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... For More Information On This Product, Operation SUBA <ea>,An SUBI #<data>,<ea> SUBQ #<data>,<ea> SUBX Dx,Dy SUBX –(Ax),–(Ay) SWAP Dn TAS <ea> Offset ø (SSP); TRAP #<vector> TRAPcc TRAPcc.W #<data> TRAPcc.L #<data> TRAPV TST <ea> UNLK An UNPACK –(Ax),–(Ay),#(adjustment) UNPACK Dx,Dy,#(adjustment) M68040 USER’S MANUAL Go to: www.freescale.com Syntax MOTOROLA ...
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... These write- backs to memory can be deferred until the most opportune moment because of the M68040 bus interface. Figure 2-1 illustrates the IU pipeline. MOTOROLA For More Information On This Product, M68040 USER’S MANUAL Go to: www.freescale.com ...
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... For More Information On This Product, INSTRUCTION DATA FROM CACHE OR BUS CONTROLLER INSTRUCTION FETCH DECODE <ea> CALCULATE TO CACHE OR <ea> FETCH BUS CONTROLLER EXECUTE TO CACHE OR WRITE-BACK BUS CONTROLLER M68040 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
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... INSTRUCTION FETCH DECODE <ea> CALCULATE <ea> FETCH EXECUTE WRITE- BACK (WB3) INTEGER UNIT Figure 2-2. Write-Back Cycle Block Diagram MOTOROLA For More Information On This Product, INSTRUCTION MEMORY UNIT DATA MEMORY UNIT PHYSICAL ADDRESS DATA ATC DATA MMU/ CACHE/SNOOP CONTROLLER WB2 DATA CACHE M68040 USER’S MANUAL Go to: www ...
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... Figure 2-3. Integer Unit User Programming Model 2-4 For More Information On This Product (USP CCR M68040 USER’S MANUAL Go to: www.freescale.com DATA REGISTERS ADDRESS REGISTERS USER STACK POINTER PROGRAM COUNTER CONDITION CODE REGISTER MOTOROLA ...
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... M68040 are in the supervisor programming model. Thus, all application software is written to run in the user mode and migrates to the M68040 from any M68000 platform without modification. MOTOROLA For More Information On This Product, M68040 USER’S MANUAL Go to: www ...
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... For More Information On This Product '(ISP) INTERRUPT STACK POINTER 0 A7 "(MSP) MASTER STACK POINTER 7 0 (CCR) SR STATUS REGISTER 0 VBR VECTOR BASE REGISTER 2 0 SFC ALTERNATE SOURCE AND DESTINATION FUNCTION CODE REGISTERS DFC 0 CACHE CONTROL REGISTER CACR M68040 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
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... The processor automatically generates function codes to select address spaces for data and programs at the user and supervisor modes. Certain instructions use the SFC and DFC registers to specify the function codes for operations. MOTOROLA For More Information On This Product, USER BYTE (CONDITION CODE REGISTER) ...
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... Setting an enable bit enables the associated cache without affecting the state of any lines within the cache. A hardware reset clears the CACR, disabling both caches. 2-8 For More Information On This Product, M68040 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
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... External Translation Disable Input Signal (MDIS) for Emulator Support • Caching Mode Selected on Page Basis The MMUs completely overlap address translation time with other processing activities when the translation is resident in one of the ATCs. ATC accesses operate in parallel with MOTOROLA For More Information On This Product, NOTE M68040 USER'S MANUAL Go to: www ...
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... CACHE INSTRUCTION MMU/CACHE/SNOOP CONTROLLER INSTRUCTION MEMORY UNIT DATA MEMORY UNIT DATA MMU/CACHE/SNOOP CONTROLLER DATA DATA CACHE ATC OPERAND DATA BUS M68040 USER'S MANUAL Go to: www.freescale.com INSTRUCTION ADDRESS B ADDRESS U BUS DATA T BUS DATA E ADDRESS R BUS CONTROL SIGNALS MOTOROLA ...
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... ATCs may no longer be valid. A PFLUSH instruction should be executed to flush the ATCs before loading a new root pointer value, if necessary. Figure 3-3 illustrates the format of the 32-bit URP and SRP registers. Bits 8– MOTOROLA For More Information On This Product, 0 ...
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... A reset operation does not affect this bit. The bit must be initialized after a reset. 3-4 For More Information On This Product M68040 USER'S MANUAL Go to: www.freescale.com MOTOROLA ...
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... The user defines these bits, and the M68040 does not interpret them. U0 and U1 are echoed to the UPA0 and UPA1 signals, respectively external bus transfer results from an access. These bits can be programmed by the user to support external addressing, bus snooping, or other applications. MOTOROLA For More Information On This Product ...
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... This bit is set if the G-bit is set in the page descriptor. U1, U0—User Page Attributes These bits are set if corresponding bits in the page descriptor are set. 3-6 For More Information On This Product M68040 USER'S MANUAL Go to: www.freescale.com MOTOROLA ...
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... Only a portion of the translation table for the entire logical address space is required to be resident in memory at any time—specifically, only the portion of the table that translates MOTOROLA For More Information On This Product, M68040 USER'S MANUAL Go to: www ...
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... Each of the 128 root-level table descriptors corresponds to a 32-Mbyte block of memory and points to the base of a pointer-level table. 3-8 For More Information On This Product, SECOND M68040 USER'S MANUAL Go to: www.freescale.com FIRST ROOT LEVEL TABLES POINTER TABLES LEVEL THIRD PAGE LEVEL TABLES MOTOROLA ...
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... The exception handler can correct an invalid descriptor that indicates a nonresident page or one that identifies a portion of the translation table yet to be allocated. An access error due to a system malfunction can require the exception handler to write an error message and terminate the task. MOTOROLA For More Information On This Product ...
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... DESCRIPTOR (CHECK DESCRIPTOR TYPE) 'INDIRECT' 'RESIDENT' TYPE 'INDIRECT' FETCH INDIRECT DESCRIPTOR (CHECK DESCRIPTOR TYPE) 'RESIDENT' PFA = PHYSICAL ADDRESS FIELD OF DESCRIPTOR CREATE ATC ENTRY WITH R-BIT SET ATC TAG ATC ENTRY PFA, DF[U1,U0,S,CM,M],WP EXIT TABLE SEARCH M68040 USER'S MANUAL Go to: www.freescale.com FC2, LA, DF[G] MOTOROLA ...
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... THE NEXT LEVEL DESCRIPTOR. ABBREVIATIONS: WP – ACCUMULATED WRITE- PROTECTION STATUS V – LOGICAL "OR" OPERATOR – ASSIGNMENT OPERATOR Figure 3-10. Detailed Flowchart of Descriptor Fetch Operation MOTOROLA For More Information On This Product, FETCH DESCRIPTOR & UPDATE HISTORY AND STATUS TYPE = 'INDIRECT' FETCH DESCRIPTOR DESCRIPTOR ADDRESS ...
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... Freescale Semiconductor, Inc. Motorola highly recommends that the translation tables be placed in cache-inhibited memory space. Motorola also highly recommends table descriptors must not be left in states that are incoherent to the processor. Future processors may treat these recommendations as mandatory. The following paragraphs apply only to M68040 systems that cannot meet these recommendations ...
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... This field selects the cache mode and accesses serialization as follows Cachable, Write-through 01 = Cachable, Copyback 10 = Noncachable, Serialized 11 = Noncachable Section 4 Instruction and Data Caches provides detailed information on caching modes, and Section 7 Bus Operation provides information on serialization. MOTOROLA For More Information On This Product ...
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... This bit identifies a page as supervisor only. Only programs operating in the supervisor mode are allowed to access the portion of the logical address space mapped by this descriptor when the S-bit is set. If the bit is clear, both supervisor and user accesses are allowed. 3-14 For More Information On This Product, M68040 USER'S MANUAL Go to: www.freescale.com MOTOROLA ...
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... When the W-bit is set, a write access or a read-modify-write access to the logical address corresponding to this entry causes an access error exception to be taken. X—Motorola Reserved These bit fields are reserved for future use by Motorola. MOTOROLA For More Information On This Product, M68040 USER'S MANUAL Go to: www ...
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... The indirection capability also allows the page frame to appear at arbitrarily different addresses in the logical address spaces of each task. 3-16 For More Information On This Product, M68040 USER'S MANUAL Go to: www.freescale.com MOTOROLA ...
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... The page descriptor located at the address given by the indirect descriptor must not have a PDT field with an indirect encoding (it must be either a resident descriptor or invalid). Otherwise, the descriptor is treated as invalid, and the M68040 creates an ATC entry with a signaled error condition (R-bit in MMUSR is clear). MOTOROLA For More Information On This Product, LOGICAL ADDRESS POINTER INDEX ...
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... For More Information On This Product, LOGICAL ADDRESS POINTER INDEX PAGE INDEX $15 $01 $54 $04 TABLE $00 TABLE $00 TABLE $3B $00001800 $3B $15 $00003000 TABLE $7F ROOT-LEVEL POINTER-LEVEL TABLES TABLES M68040 USER'S MANUAL Go to: www.freescale.com PAGE OFFSET TABLE $00 TABLE $15 $01 $80000010 TABLE $1F FRAME ADDRESS PAGE-LEVEL TABLES MOTOROLA ...
Page 68
... This determination can be facilitated by using he unused bits in the descriptor to store status information concerning the invalid encoding. The M68040 does not interpret or modify an invalid descriptor’s fields except for the UDT field. This MOTOROLA For More Information On This Product, LOGICAL ADDRESS ...
Page 69
... UDT = INVALID UDT = INVALID UDT = INVALID UDT = INVALID TABLE $7F NONRESIDENT NONRESIDENT (PAGED OR (PAGED OR UNALLOCATED) UNALLOCATED) ROOT-LEVEL POINTER-LEVEL TABLES TABLES M68040 USER'S MANUAL Go to: www.freescale.com PAGE OFFSET TABLE $00 NONRESIDENT (PAGED OR UNALLOCATED) TABLE $15 $01 FRAME ADDRESS TABLE $1F NONRESIDENT (PAGED OR UNALLOCATED) PAGE-LEVEL TABLES MOTOROLA ...
Page 70
... U-bit occurs only if the U-bit was clear. Table 3-1 lists the page descriptor update operations for each combination of U-bit, M-bit, write-protected, and read or write access type. MOTOROLA For More Information On This Product, M68040 USER'S MANUAL Go to: www.freescale.com ...
Page 71
... Locked RMW Access to Set U Locked RMW Access to Set U None None Results 000 00 001 00 001 10 011 10 100 00 101 00 101 10 111 M68040 USER'S MANUAL Go to: www.freescale.com New Status U-Bit M-Bit MOTOROLA ...
Page 72
... The entire user and supervisor address spaces can be mapped together by loading the same root pointer address into both the SRP and URP registers. MOTOROLA For More Information On This Product, M68040 USER'S MANUAL Go to: www.freescale.com ...
Page 73
... SUPERVISOR AND USER SPACE THIS AREA IS SUPERVISOR ONLY, READ-ONLY THIS AREA IS SUPERVISOR ONLY, READ/WRITE THIS AREA IS SUPERVISOR OR USER, READ-ONLY THIS AREA IS SUPERVISOR OR USER, READ/WRITE M68040 USER'S MANUAL Go to: www.freescale.com TRANSLATION TABLE FOR TASK 'A' TRANSLATION TABLE FOR TASK 'B' TRANSLATION TABLE FOR ALL SUPERVISOR ACCESSES MOTOROLA ...
Page 74
... Freescale Semiconductor, Inc. PRIVILEGE SRP MODE URP URP & SRP POINT TO SAME A LEVEL TABLE NOTE Don’t care. Figure 3-19. Translation Table Using S-Bit and W-Bit To Set Protection MOTOROLA For More Information On This Product ROOT-LEVEL ...
Page 75
... PAGE OFFSET 12 SET 0 TAG ENTRY SET 1 • • • • • • TAG ENTRY SET HIT 3 2 HIT 2 1 HIT 1 HIT 0 COMPARATOR 0 M68040 USER'S MANUAL Go to: www.freescale.com PA(11–0) PA(12) MUX 1 PAGE SIZE 19 PA(31–13) 9 STATUS 29 29 MUX LINE SELECT HIT HIT DETECT MOTOROLA ...
Page 76
... M68040 suspends the access, initiates a table search to set the M-bit in the page descriptor, and writes over the old ATC entry with the current page descriptor information. The MMU then allows the original write access to be performed. This MOTOROLA For More Information On This Product, M ...
Page 77
... When the ATC does not contain the translation for a logical address, a miss occurs. The MMU aborts the current access and searches the translation tables in memory for the correct translation. If the table search completes without any errors, the MMU stores the 3-28 For More Information On This Product, M68040 USER'S MANUAL Go to: www.freescale.com MOTOROLA ...
Page 78
... The address for the current bus cycle and a TTR address match when the privilege mode and logical base address bits are equal. Each TTR can specify write protection for the block. When write protection is enabled for a block, write or read-modify-write accesses to the block are aborted. MOTOROLA For More Information On This Product, M68040 USER'S MANUAL Go to: www.freescale.com ...
Page 79
... A-line, illegal, CHK, or unimplemented instruction and the next page is non-resident. Instead, the M68040 attempts to prefetch the next instruction on the missing page, then the ATC access error exception is reported. The stacked PC points to the exceptional 3-30 For More Information On This Product, M68040 USER'S MANUAL Go to: www.freescale.com MOTOROLA ...
Page 80
... MMUs on the next boundary after the signal is negated. The assertion of this signal does not affect the operation of the transparent translation registers or execution of the PFLUSH or PTEST instructions. MOTOROLA For More Information On This Product, MDIS AND M68040 USER'S MANUAL Go to: www ...
Page 81
... LOGICAL ADDRESS UPA TTR1* [U1,U0] CM TTR1* [CM] EXIT PA ATC ENTRY [PA] UPA ATC ENTRY [U1,U0] CM ATC ENTRY [CM] EXIT M68040 USER'S MANUAL Go to: www.freescale.com LOGICAL ADDRESS MATCHES WITH TTR0* (TTR0*[ AND (WRITE OR RMW ACCESS) OTHERWISE ABORT CYCLE EXCEPTION PA LOGICAL ADDRESS UPA TTR0* [U1,U0] CM TTR0* [CM] EXIT MOTOROLA ...
Page 82
... MMUSR for the source of the fault. The M68040 MMU instructions use opcodes that are different from those for the corresponding instructions in the MC68030 and MC68851. All MMU opcodes for the MOTOROLA For More Information On This Product, Copy transfer modifier field from stack frame ...
Page 83
... In a typical access error exception handler, the flowchart illustrated in Figure 3-23 can be used to determine the cause of an MMU fault. The PTEST instruction sets the bits in the MMUSR appropriately, and the program can branch to the appropriate code segment for the condition. 3-34 For More Information On This Product, M68040 USER'S MANUAL Go to: www.freescale.com MOTOROLA ...
Page 84
... BRANCH TO "SUPERVISOR OTHERWISE WRITE OR RMW ACCESS INDICATED IN STACK NOT MMU * Refers to either instruction or data transparent translation register. Figure 3-23. MMU Status Interpretation MOTOROLA For More Information On This Product, PTEST (An BRANCH TO "BUS ERROR DURING TABLE SEARCH" CODE OTHERWISE VOILATION" ...
Page 85
... Allowing memory pages to be specified as write-through instead of copyback also supports cache coherency. When a processor writes to write-through pages, external MOTOROLA For More Information On This Product, NOTE M68040 USER’S MANUAL Go to: www ...
Page 86
... CACHE INSTRUCTION MMU/CACHE/SNOOP CONTROLLER INSTRUCTION MEMORY UNIT DATA MEMORY UNIT DATA MMU/CACHE/SNOOP CONTROLLER DATA DATA ATC CACHE OPERAND DATA BUS M68040 USER'S MANUAL Go to: www.freescale.com INSTRUCTION ADDRESS B U ADDRESS S BUS DATA R BUS DATA E ADDRESS R BUS CONTROL SIGNALS MOTOROLA ...
Page 87
... Consequently, if the accesses span page boundaries, misaligned accesses to peripherals are not possible unless the peripheral can tolerate double reads or writes. MOTOROLA For More Information On This Product, LW3 LW2 ...
Page 88
... PHYSICAL SET SELECT PA9–PA4 SET 0 TAG STATUS D0 SET 1 SET 63 TAG STATUS D0 TRANSLATED PHYSICAL ADDRESS PA31–PA10 COMPARATOR M68040 USER'S MANUAL Go to: www.freescale.com LINE 3 LINE DATA OR INSTRUCTION MUX LINE SELECT 3 HIT 3 HIT 2 HIT LOGICAL OR HIT 1 HIT 0 MOTOROLA ...
Page 89
... The state of the CDIS signal or the cache enable bits in the CACR does not affect the operation of CINV and CPUSH. Both instructions allow operation on a single cache line, all cache lines in a specific page MOTOROLA For More Information On This Product, 16 ...
Page 90
... When a miss causes a dirty cache line to be selected for replacement, the memory unit places the line in an internal copyback buffer. The replacement line is read into the cache, and writing the dirty cache line back to memory updates memory. 4-6 For More Information On This Product, M68040 USER'S MANUAL Go to: www.freescale.com MOTOROLA ...
Page 91
... CACHE PROTOCOL The cache protocol for processor and snooped accesses is described in the following paragraphs. In all cases, an external bus transfer will cause a cache line state to change MOTOROLA For More Information On This Product, M68040 USER’S MANUAL Go to: www.freescale.com ...
Page 92
... The cache line state does not change. A write-through access to a line containing dirty data constitutes a system programming error even if the D-bits for the line are unchanged. This situation can be 4-8 For More Information On This Product, M68040 USER'S MANUAL Go to: www.freescale.com MOTOROLA ...
Page 93
... Reserved (Snoop Inhibited) The snooping protocol and caching mechanism supported by the M68040 are optimized to support multimaster systems with the M68040 as the single caching master. In systems MOTOROLA For More Information On This Product, Requested Snoop Operation Alternate Bus Master Write Access Inhibit Snooping ...
Page 94
... A system programming error occurs when page attributes are changed without flushing the corresponding page from the cache, resulting in cache line states inconsistent with their page definitions. Even with these inconsistencies, the cache is defined and predictable. 4-10 For More Information On This Product, M68040 USER'S MANUAL Go to: www.freescale.com MOTOROLA ...
Page 95
... When a cache line read is initiated, the first cycle attempts to load the line entry corresponding to the instruction half-line or data item requested by the IU. Subsequent transfers are for the remaining entries in the cache line. In the case of a misaligned MOTOROLA For More Information On This Product, Table 4-2. TLNx Encoding ...
Page 96
... If a cache inhibit or bus error occurs on a replacement line read, a dirty line is restored to the cache from the push buffer. However, the line being replaced is not restored in the cache if it was originally valid and the cache line remains invalid. If the line 4-12 For More Information On This Product, M68040 USER'S MANUAL Go to: www.freescale.com MOTOROLA ...
Page 97
... The instruction and data caches function independently when servicing access requests from the IU. The following paragraphs discuss the operational details for the caches and present state diagrams depicting the cache line state transitions. MOTOROLA For More Information On This Product bus error terminates a push transfer, the processor M68040 USER’ ...
Page 98
... Table 4-3. I3–CINV/CPUSH INVALID Figure 4-5. Instruction-Cache Line State Diagram 4-14 For More Information On This Product, V1–CPU READ MISS V2–CPU READ HIT I1-CPU READ MISS V3–CINV/CPUSH V5–SNOOP READ HIT V6–SNOOP WRITE HIT M68040 USER'S MANUAL Go to: www.freescale.com VALID MOTOROLA ...
Page 99
... Transitions are labeled with a capital letter, indicating the previous state, followed by a number indicating the specific case listed in Table 4-4. MOTOROLA For More Information On This Product, Current State ...
Page 100
... D4—CPU WRITE MISS/WT D5—CPU WRITE HIT/CB D6—CPU WRITE HIT/WT D9—SNOOP READ HIT/LEAVE DIRTY D12—SNOOP WRITE HIT/SINK DATA & SIZE = LINE M68040 USER'S MANUAL Go to: www.freescale.com V1—CPU READ MISS V2—CPU READ HIT V4—CPU WRITE MISS/WT V6—CPU WRITE HIT/WT V9—SNOOP READ HIT/LEAVE DIRTY MOTOROLA ...
Page 101
... Not Possible (Snoop Control = 01 — Leave Dirty) NOTE: Dirty state transitions D4 and D6 are the result of a system programming error and should be avoided even though they are technically valid. MOTOROLA For More Information On This Product, Current State Invalid Cases Valid Cases V1 Read line from memory ...
Page 102
... M68040 USER'S MANUAL Go to: www.freescale.com Dirty Cases D10 Inhibit memory and source data invalid state D11 No action invalid state. D12 Inhibit memory and sink data; set Dn bits of modified long words; remain in current state. D13 No action invalid state. MOTOROLA ...
Page 103
... For the MC68EC040 and MC68EC040V only, ignore all references to the memory management unit (MMU). Some pin names are different on these parts; please refer to the appropriate appendix in the back of this book for more information. MOTOROLA For More Information On This Product, NOTES M68040 USER’S MANUAL Go to: www.freescale.com ...
Page 104
... Disables the translation mechanism of the MMUs. Processor reset. Asserted during execution of a RESET instruction to reset external devices. Indicates an interrupt is pending. Used during an interrupt acknowledge transfer to request internal generation of the vector number. Clock input used to derive all bus signal timing. M68040 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
Page 105
... This signal is not available on the MC68EC040 and the MC68EC040V. 3. These signals are different on power-up for the MC68LC040 and MC68EC040. 4. These signals are not available on the MC68040V and MC68EC040V. MOTOROLA For More Information On This Product, Function Clock input used for internal logic timing. The PCLK frequency is exactly 2 the BCLK frequency ...
Page 106
... IPL2 3 MC68040 IPEND AVEC PST0 PST1 PST2 PST3 BCLK PCLK 4 TCK TMS TDI TDO TRST GND M68040 USER’S MANUAL Go to: www.freescale.com BUS SNOOP CONTROL AND RESPONSE BUS ARBITRATION PROCESSOR CONTROL INTERRUPT CONTROL STATUS AND CLOCKS TEST POWER SUPPLY MOTOROLA ...
Page 107
... LPSTOP broadcast cycles on the MC68040V and MC68EC040V. Table 5-2. Transfer-Type Encoding TT1 TT0 MOTOROLA For More Information On This Product, Transfer Type Normal Access MOVE16 Access Alternate Logical Function Code Access Acknowledge Access M68040 USER’S MANUAL Go to: www.freescale.com 5- 5 ...
Page 108
... MMU Table Search Code Access 1 Supervisor Data Access* 0 Supervisor Code Access 1 Reserved TM0 Transfer Modifier 0 Logical Function Code 0 1 Reserved 0 Reserved 1 Logical Function Code 3 0 Logical Function Code 4 1 Reserved 0 Reserved 1 Logical Function Code 7 M68040 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
Page 109
... When the M68040 is not the bus master, the LOCKE signal is set to a high-impedance state. LOCKE drives high before MOTOROLA For More Information On This Product, M68040 USER’S MANUAL Go to: www ...
Page 110
... Transfer Error Acknowledge ( The current slave asserts this input signal to indicate an error condition for the bus transaction. When asserted with TA, this signal indicates that the processor should retry 5-8 For More Information On This Product, CIOUT ) TIP ) TA ) TEA ) M68040 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
Page 111
... Otherwise, MI remains asserted and the M68040 completes the transfer as a slave. It updates its caches on a write or supplies data to the alternate bus master on a read negated when the M68040 is the bus master. During a snoop MOTOROLA For More Information On This Product, TCI ...
Page 112
... Refer to Section 4 Instruction and Data Caches for information about the caches and to Section 7 Bus Operation for information about the multiplexed bus mode. Refer to Appendix E 5-10 For More Information On This Product, ) M68040 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
Page 113
... TLN1–TLN0, TM2–TM0, TT1–TT0, UPA1–UPA0 Miscellaneous Control Signals: IPL0 BB IPEND, MI, PST3–PST0, RSTO , TA, TDO, TIP , TS NOTE: High input level = small buffers enabled; low input level = large buffers enabled. MOTOROLA For More Information On This Product, IPL2 IPL0 – ...
Page 114
... PSTx encoding. This class indicates that the instruction is in its last instruction execution stage. These encodings exist for only one BCLK period per instruction and are mutually exclusive. 5-12 For More Information On This Product, IPEND ) M68040 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
Page 115
... All other instructions and conditions end with the ‘end current instruction’ encoding. For instance, if the processor is running back-to-back single clock instructions, the encoding ‘end current instruction’ remains asserted for as many clock cycles as instructions. MOTOROLA For More Information On This Product, PST0 Internal Status ...
Page 116
... This input signal is used in DLE mode to latch the input data bus on read transfers. DLE mode can be used to support asynchronous memory interfaces by allowing the interface to specify when data should be latched instead of requiring data to be valid on the rising edge of BCLK. 5-14 For More Information On This Product, )—NOT ON MC68EC040 M68040 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
Page 117
... CC sections of the processor. Section 12 Ordering Information and Mechanical Data describes the groupings MOTOROLA For More Information On This Product, )—Not on MC68040V and MC68EC040V power supply, positive with respect to ground. CC and ground connections. ...
Page 118
... High — — — Low No Low — Low Yes Low Yes Low No Low — — — High No High/Low Yes Low — Low No High — Low Yes Low — Low — Low — Low Yes High Yes High Yes High Yes MOTOROLA ...
Page 119
... Test Reset User-Programmable Attributes Power Supply NOTES: 1. This signal is not available on the MC68LC040 and MC68EC040. 2. These signals are different on power-up for the MC68LC040 and MC68EC040. 3. This signal is not available on the MC68EC040. MOTOROLA For More Information On This Product, Mnemonic Type Input/Output TS TT1, TT0 ...
Page 120
... Certain precautions must be observed to ensure that this logic does not interfere with system operation. Refer to 6.5 Disabling the IEEE Standard 1149.1A Operation. MOTOROLA For More Information On This Product, NOTE NOTE M68040 USER’S MANUAL Go to: www ...
Page 121
... TMS TCK TRST Figure 6-1. M68040 Test Logic Block Diagram 6-2 For More Information On This Product, Run-Test/Idle Capture-DR Update-DR Shift-DR TEST DATA REGISTERS 0 184-BIT BOUNDARY SCAN REGISTER BYPASS LATCHED DECODER 2 0 3-BIT INSTRUCTION SHIFT REGISTER M68040 USER’S MANUAL Go to: www.freescale.com TDO MOTOROLA ...
Page 122
... The external test instruction (EXTEST) selects the 184-bit boundary scan register. This instruction also activates two internal functions that are intended to protect the device from potential damage while performing boundary scan operations. MOTOROLA For More Information On This Product, Instruction Selected Test Data Register Accessed ...
Page 123
... EXTEST instruction. 6.2.4 DRVCTL.T The DRVCTL.T instruction is a Motorola public instruction that provides the ability to select one of two output drivers on a pin-by-pin basis intended for use with EXTEST or SHUTDOWN to provide an IEEE-compatible environment to select the output drivers for board-level test environments ...
Page 124
... The test logic controls the I/O state, and the bypass register is selected. 6.2.6 PRIVATE Motorola reserves this instruction for manufacturing use. The instruction does not change pin I/O as defined for system operation. 6.2.7 DRVCTL.S The DRVCTL.S instruction controls the output driver selection on a pin-by-pin basis. This instruction allows data in the boundary scan register to select the output driver during the update-DR state when the system logic has control of the signal I/O directions and levels ...
Page 125
... Figures 6-3 through 6-5 illustrate these three cell types. Figure 6-6 illustrates the general arrangement of these cells. 6-6 For More Information On This Product MUX 1 C1 Figure 6-2. Bypass Register M68040 USER’S MANUAL Go to: www.freescale.com TO TDO MOTOROLA ...
Page 126
... EXTEST, DRVCTL.T, AND SHUTDOWN 0 = OTHERWISE G1 DATA FROM 1 SYSTEM LOGIC MUX 1 Figure 6-3. Output Latch Cell (O.Latch) TO NEXT CELL TO SYSTEM LOGIC Figure 6-4. Input Pin Cell (I.Pin) MOTOROLA For More Information On This Product, TO NEXT CELL SHIFT MUX 1 C1 FROM CLOCK DR UPDATE DR2 LAST (DRVCTL ...
Page 127
... For More Information On This Product, SHIFT DR TO NEXT CELL G1 1 MUX FROM CLOCK DR RESET LAST UPDATE DR CELL TO NEXT CELL I/O.CTL EN O.LATCH I.PIN FROM TO NEXT LAST CELL PIN PAIR M68040 USER’S MANUAL Go to: www.freescale.com TO OUTPUT BUFFER (1 = DRIVE INPUT PIN MOTOROLA ...
Page 128
... I/O indicates a bidirectional pin. The last column lists the name of the associated control bit of the boundary scan register for three-state output and bidirectional pins. The boundary scan description language (BSDL) type for each cell can be found in note 1. MOTOROLA For More Information On This Product, Cell Name Bit io ...
Page 129
... Pin Type Ctrl Cell I/O 2 A24 io.ab A24 I/O io.ab I/O 2 A25 io.ab A25 I/O io.ab I/O 2 A26 io.ab A26 I/O io.ab I/O 2 A27 io.ab A27 I/O io.ab I/O 2 A28 io.ab A28 I/O io.ab I/O 2 A29 io.ab A29 I/O io.ab I/O 2 A30 io.ab A30 I/O io.ab I/O 2 A31 io.ab A31 I/O io.ab I io.db I io.db I io.db I io.db I io.db I io.db I io.db I io.db I io.db I io.db I/O 2 D10 io.db I/O 2 D11 io.db I/O 2 D12 io.db I/O 2 D13 io.db I/O 2 D14 io.db I/O 2 D15 io.db I/O 2 D16 io.db I/O 2 D17 io.db I/O 2 D18 io.db I/O 2 D19 io.db I/O 2 D20 io.db MOTOROLA ...
Page 130
... I.Pin D19 105 I.Pin D20 106 I.Pin D21 107 I.Pin D22 108 I.Pin D23 109 I.Pin D24 110 I.Pin D25 MOTOROLA For More Information On This Product, Output Ctrl Cell Bit Cell Type I/O 2 io.db 111 I.Pin I/O 2 io.db 112 I.Pin I/O 2 io.db 113 I.Pin I/O 2 io.db 114 I.Pin I ...
Page 131
... SC0 Input — Input — TBI Input — AVEC Input — TCI DLE 5 Input — PCLK Input — BCLK Input — Input — IPL0 Input — IPL1 Input — IPL2 Input — RSTI Input — CDIS MDIS 6 Input — MOTOROLA ...
Page 132
... RSTI while TCK is held either high or low meets the two considerations pulse asserts TRST , the TAP controller is forced into the test-logic-reset state and can remain in this state as long as a rising edge on the TCK signal does not occur when TMS is low. MOTOROLA For More Information On This Product, M68040 USER’S MANUAL Go to: www ...
Page 133
... Freescale Semiconductor, Inc. 6-14 For More Information On This Product, +5V 1K TDI TMS TRST TCLK NO CONNECTION TD0 Figure 6-7. Circuit Disabling IEEE Standard 1149.1A M68040 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
Page 134
... Freescale Semiconductor, Inc. 6.6 MOTOROLA M68040 BSDL DESCRIPTION (VERSION 2.2) Revision List: 1. LOCK and LOCKE controlled by io.1 vice io.0 (4D98D other changes to Version 2.1 BSDL. 2. Instruction opcodes changed for SAMPLE, SHUTDOWN, and BYPASS. 3. New instructions DRVCTL.T, DRVCTL.S and PRIVATE added. 4. New instructions DRVCTL.T and DRVCTL.S renamed to DRVCTL_T and DRVCTL_S for syntax compatibility ...
Page 135
... MOTOROLA ...
Page 136
... REGISTER_ACCESS of MC68040:entity is "BYPASS (SHUTDOWN, HI_Z, PRIVATE), "BOUNDARY (DRVCTL_T, DRVCTL_S) attribute BOUNDARY_CELLS of MC68040:entity is "BC_2, BC_4 attribute BOUNDARY_LENGTH of MC68040:entity is 184; attribute BOUNDARY_REGISTER of MC68040:entity is MOTOROLA For More Information On This Product, M68040 USER’S MANUAL Go to: www.freescale.com " & " & " & " & ...
Page 137
... MOTOROLA ...
Page 138
... D(22), input, "108 (BC_4, D(23), input, "109 (BC_4, D(24), input, "110 (BC_4, D(25), input, "111 (BC_4, D(26), input, "112 (BC_4, D(27), input, "113 (BC_4, D(28), input, MOTOROLA For More Information On This Product, safe ccell dsval rslt X, 151, 0, Z), X, 151, 0, Z), X, 151, 0, Z), X, 151, 0, Z), X, 151, 0, Z), X, 151, ...
Page 139
... MOTOROLA ...
Page 140
... MC68040, MC68LC040, MC68EC040 JTAG ELECTRICAL CHARACTERISTICS The following paragraphs provide information on JTAG electrical and timing specifications. This section is subject to change. For the most recent specifications, contact a Motorola sales office or complete the registration card at the beginning of this manual. JTAG DC Electrical Specifications Characteristic ...
Page 141
... Min Max 0 10 100 — 40 — — 100 — 50 — 50 — — 5 — TRST Timing Diagram M68040 USER’S MANUAL Go to: www.freescale.com Unit MHz MOTOROLA ...
Page 142
... DATA OUTPUTS DATA OUTPUTS DATA OUTPUTS Figure 6-10. Boundary Scan Timing Diagram TCLK TDI, TMS TDO TDO TDO Figure 6-11. Test Access Port Timing Diagram MOTOROLA For More Information On This Product INPUT DATA VALID 8 OUTPUT DATA VALID 9 8 OUTPUT DATA VALID V IH ...
Page 143
... BCLK, and the two PCLK cycles corresponding to each BCLK cycle are divided into four states, T1–T4. Most outputs change during state T4, whether transitioning between a driven and high-impedance state or switching between assert and MOTOROLA For More Information On This Product, NOTE M68040 USER’ ...
Page 144
... For More Information On This Product, ), input hold time ( illustrated in Figure 7-1 are described in the AC electrical ho ho M68040 USER’S MANUAL Go to: www.freescale.com ), output hold –1/2 PCLK –1/2 PCLK and t (see MOTOROLA ...
Page 145
... For a burst-inhibited line transfer, A1 and A0 for each of the four accesses (the burst-inhibited line transfer and three long-word transfers) are copied from the lowest two bits of the access address used to initiate the line transfer. MOTOROLA For More Information On This Product, BYTE 1 ...
Page 146
... BYTEn BYTE BYTEn BYTEn M68040 USER’S MANUAL Go to: www.freescale.com BYTE 0 INTERNAL TO THE MC68040 D7–D0 EXTERNAL BUS BYTE 0 D15–D8 D7–D0 — — — — BYTEn — — BYTEn — — BYTEn BYTEn BYTEn BYTEn BYTEn BYTEn MOTOROLA ...
Page 147
... Freescale Semiconductor, Inc SIZ0 SIZ1 PAL16L8 U1 MC68040 Byte Data Select Generation. Motorola Worldwide Marketing Training Organization A0 A1 SIZ0 SIZ1 GND NC UUD UMD LMD LLD VCC /UUD = /A0 * /A1 + /SIZ1 * /SIZ0 + SIZ1 * SIZ0 /UMD = A0 * /A1 + /A1 * /SIZ1 + SIZ1 * SIZ0 ...
Page 148
... Undefined Undefined Read/Write Read/Write Read/Write Asserted/ Negated Negated Negated 3 Negated MMU Asserted Source 1 M68040 USER’S MANUAL Go to: www.freescale.com Interrupt Breakpoint Acknowledge Acknowledge $FFFFFFFF $00000000 $0 $0 Byte Byte $3 $3 Int. Level $1–7 $0 Undefined Undefined Read Read Negated Negated Negated Negated MOTOROLA ...
Page 149
... XXX Figure 7-5. Example of a Misaligned Long-Word Transfer — BYTE XXX XXX BYTE 0 XXX Figure 7-6. Example of a Misaligned Word Transfer MOTOROLA For More Information On This Product, DATA BUS — — BYTE 2 — — MEMORY BYTE 2 ...
Page 150
... TIP TA D31–D24 D23–D16 D15–D8 D7–D0 Figure 7-7. Misaligned Long-Word Read Transfer Timing 7-8 For More Information On This Product BYTE WORD BYTE 0 BYTE 1 BYTE 2 BYTE WORD BYTE READ READ READ M68040 USER’S MANUAL Go to: www.freescale.com C2 BYTE BYTE 3 MOTOROLA ...
Page 151
... BCLK signal. The M68040 moves data on the bus by issuing control signals and using a handshake protocol to ensure correct data movement. The following paragraphs describe the bus cycles for byte, word, long-word, and line read, write, and read-modify-write transfers. MOTOROLA For More Information On This Product, Number of Bus Cycles $0 * ...
Page 152
... Figure 7-8. Byte, Word, and Long-Word Read Transfer Flowchart 7-10 For More Information On This Product, EXTERNAL DEVICE PRESENT DATA 1) DECODE ADDRESS 2) PLACE DATA ON APPROPRIATE BYTES OF D31–D0 BASED ON SIZEx, A0, AND A1 3) ASSERT TA TERMINATE CYCLE 1) REMOVE DATA FROM D31–D0 2) NEGATE TA M68040 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
Page 153
... TT1, TT0 TM2–TM0 R/W CIOUT TS TIP TA D31–D24 D23–D16 D15–D8 D7–D0 BYTE READ Figure 7-9. Byte, Word, and Long-WordRead Transfer Timing MOTOROLA For More Information On This Product BYTE WORD WORD READ LONG-WORD WITH WAIT M68040 USER’S MANUAL Go to: www ...
Page 154
... The address and transfer attributes supplied by the processor remain stable during the transfers, and the selected device terminates each transfer by driving the long word on 7-12 For More Information On This Product, M68040 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
Page 155
... M68040 stalls until the second access of the burst (the address of the instruction to be executed) has completed. Figures 7-10 and 7-11 illustrate a flowchart and functional timing diagram for a line read bus transfer. MOTOROLA For More Information On This Product, M68040 USER’S MANUAL Go to: www ...
Page 156
... PRESENT DATA 1) DECODE ADDRESS 2) PLACE DATA ON D31–D0 3) ASSERT TA TERMINATE CYCLE 1) REMOVE DATA FROM D31–D0 2) NEGATE TA (IF NECESSARY) 3) INCREMENT ADDRESS BITS A3, A2 (IF NECESSARY) WHEN FOUR LONG WORDS TRANSFERRED M68040 USER’S MANUAL Go to: www.freescale.com UNTIL FOUR LONG WORDS TRANSFERRED MOTOROLA ...
Page 157
... The R/W signal is driven high for a read cycle, and the size signals (SIZx) indicate line size. CIOUT is asserted for a MOVE16 operand read if the access is identified as noncachable. Refer to Section 3 Memory Management Unit MOTOROLA For More Information On This Product, C1 ...
Page 158
... The latched data is then passed to the appropriate memory unit. Clock 4 (C4) This clock is identical to C3 except that once TA is recognized asserted, the latched value corresponds to the third long word of data for the burst. 7-16 For More Information On This Product, M68040 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
Page 159
... Otherwise, the processor negates TIP during the first half of the next clock. Figures 7-12 and 7-13 illustrate a flowchart and functional timing diagram for a burst- inhibited line read bus cycle. MOTOROLA For More Information On This Product, M68040 USER’S MANUAL Go to: www.freescale.com ...
Page 160
... PLACE DATA ON D31–D0 3) ASSERT TA AND TBI TERMINATE CYCLE 1) REMOVE DATA FROM D31–D0 2) NEGATE TA 1) DECODE ADDRESS 2) PLACE DATA ON D31–D0 3) ASSERT TA TERMINATE CYCLE 1) REMOVE DATA FROM D31–D0 2) NEGATE TA M68040 USER’S MANUAL Go to: www.freescale.com PRESENT DATA PRESENT DATA MOTOROLA ...
Page 161
... TT1, TT0 TM2–TM0 TLN1, TLN0 R/W CIOUT TS TIP TA TBI TCI D31–D0 INHIBITED LINE READ Figure 7-13. Burst-Inhibited Line Read Transfer Timing MOTOROLA For More Information On This Product LONG LONG LONG-WORD LONG-WORD READ READ M68040 USER’S MANUAL Go to: www.freescale.com ...
Page 162
... Figure 7-14. Byte, Word, and Long-Word Write Transfer Flowchart 7-20 For More Information On This Product, EXTERNAL DEVICE ACCEPT DATA 1) DECODE ADDRESS 2) LATCH DATA ON APPROPRIATE BYTES OF D31–D0 BASED ON SIZEx, A1, AND A0 3) ASSERT TRANSFER ACKNOWLEDGE (TA) TERMINATE CYCLE 1) NEGATE TA M68040 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
Page 163
... Appendix B MC68EC040 for information on the MC68EC040 memory unit. The processor asserts TS during C1 to indicate the beginning of a bus cycle. If not already asserted from a previous bus cycle, the TIP signal is also asserted at this time to indicate that a bus cycle is active. MOTOROLA For More Information On This Product BCLK A31– ...
Page 164
... The processor uses line write bus cycles to access a 16-byte operand for a MOVE16 instruction and to support cache line pushes. Both burst and burst-inhibited transfers are supported. Figures 7-16 and 7-17 illustrate a flowchart and functional timing diagram for a line write bus cycle. 7-22 For More Information On This Product, M68040 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
Page 165
... WORDS TRANSFERRED WORDS TRANSFERRED END OF BURST 1) REMOVE DATA FROM D31–D0 2) NEGATE TIP (IF REQUIRED) START NEXT CYCLE Figure 7-16. Line Write Transfer Flowchart MOTOROLA For More Information On This Product, EXTERNAL DEVICE ACCEPT DATA 1) DECODE ADDRESS (FIRST TRANSFER ONLY) 2) LATCH DATA ON D31–D0 3) ASSERT TA ...
Page 166
... SIZ1 and SIZ0 indicate line size. CIOUT is asserted for a MOVE16 operand read if the access is identified as noncachable. Refer to Section 3 Memory Management Unit (Except MC68EC040 and MC68EC040V) for information on the M68040 and 7-24 For More Information On This Product A3 M68040 USER’S MANUAL Go to: www.freescale.com C5 00 MOTOROLA ...
Page 167
... Otherwise, the processor negates TIP during the first half of the next clock. The processor also three-states the data bus during the first half of the next clock following termination of the write cycle. MOTOROLA For More Information On This Product, M68040 USER’S MANUAL Go to: www ...
Page 168
... Refer to Section 3 Memory Management Unit (Except MC68EC040 and MC68EC040V) for information on the M68040 and MC68LC040 memory units and Appendix B MC68EC040 for information on the MC68EC040 memory unit. 7-26 For More Information On This Product, M68040 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
Page 169
... TT1, TT0 TM2–TM0 R/W CIOUT LOCK LOCKE TS TIP TA D31–D24 D23–D16 D15–D8 D7–D0 Undefined Figure 7-18. Locked Transfer for TAS Instruction Timing MOTOROLA For More Information On This Product BYTE LOCKED TRANSFER M68040 USER’S MANUAL Go to: www.freescale.com ...
Page 170
... not recognized asserted at the end of C4, the processor appends a wait state instead of terminating the transfer. The processor continues to sample the TA signal on successive rising edges of BCLK until it is recognized asserted. 7-28 For More Information On This Product, M68040 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
Page 171
... Figure 7- flowchart of the procedure for making an interrupt pending. MOTOROLA For More Information On This Product, M68040 USER’S MANUAL Go to: www.freescale.com ...
Page 172
... IPL2–IPL0 IPEND IPLs RECOGNIZED IPLs SYNCHRONIZED COMPARE REQUEST WITH MASK IN SR Figure 7-20. Assertion of 7-30 For More Information On This Product, RESET SAMPLE AND SYNCHRONIZE IPL2–IPL0 > INTERRUPT LEVEL I2–I0, OR TRANSITION ON LEVEL 7 ASSERT IPEND ASSERT IPEND IPEND M68040 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
Page 173
... Some interrupting devices have programmable vector registers that contain the interrupt vectors for the exception handlers they use. Other interrupting conditions or devices cannot supply a vector number and use the autovector bus cycle described in 7.5.1.2 Autovector Interrupt Acknowledge Bus Cycle. MOTOROLA For More Information On This Product, AVEC Termination Condition Don’ ...
Page 174
... START NEXT CYCLE Figure 7-21. Interrupt Acknowledge Bus Cycle Flowchart 7-32 For More Information On This Product, EXTERNAL DEVICE REQUEST INTERRUPT PROVIDE VECTOR INFORMATION 1) PLACE VECTOR NUMBER ON BYTE D7–D0 2) ASSERT TRANSFER ACKNOWLEDGE (TA) TERMINATE CYCLE 1) REMOVE DATA FROM D7–D0 2) NEGATE TA M68040 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
Page 175
... The vector number supplied in an autovector operation is derived from the interrupt priority level of the current interrupt. When the AVEC signal is asserted with TA during an interrupt acknowledge bus cycle, the M68040 ignores the state of the data bus and internally MOTOROLA For More Information On This Product, C1 ...
Page 176
... M68040 automatically generates the spurious interrupt vector number 24 ($18) instead of the interrupt vector number and TEA are both asserted, the processor retries the cycle. 7-34 For More Information On This Product BYTE INTERRUPT LEVEL INTERRUPT ACKNOWLEDGE AUTOVECTORED M68040 USER’S MANUAL Go to: www.freescale.com C2 WRITE STACK MOTOROLA ...
Page 177
... SET TRANSFER MODIFIER TM2–TM0 NEGATE CIOUT 9) ASSERT TS FOR ONE CLOCK 10) ASSERT TIP INITIATE ILLEGAL INSTRUCTION EXCEPTION PROCESSING Figure 7-24. Breakpoint Interrupt Acknowledge Bus Cycle Flowchart MOTOROLA For More Information On This Product, EXTERNAL DEVICE ASSERT TA OR TEA TERMINATE CYCLE 1) NEGATE TA OR TEA M68040 USER’S MANUAL Go to: www ...
Page 178
... TEA can also be asserted in combination with TA to cause a retry of a bus cycle in error. 7-36 For More Information On This Product BYTE BREAKPOINT ACKNOWLEDGE M68040 USER’S MANUAL Go to: www.freescale.com C2 WRITE STACK MOTOROLA ...
Page 179
... If a dirty data cache line is being replaced and a bus error occurs during the replacement line read, the dirty line is restored from an internal push MOTOROLA For More Information On This Product, TA ...
Page 180
... TEA pin can cause physical bus errors. Furthermore, because FSAVE instructions usually place the state frame on the system stack, the occurrence of a physical bus error when using the system stack indicates a serious hardware error. 7-38 For More Information On This Product, M68040 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
Page 181
... A31–A0 UPA1, UPA0 SIZ1 SIZ0 TT1, TT0 TM2–TM0 R/W CIOUT TS TIP TA TEA D31–D0 Figure 7-26. Word Write Access Terminated with MOTOROLA For More Information On This Product WORD WRITE CYCLE WRITE STACK M68040 USER’S MANUAL Go to: www.freescale.com C2 TEA Timing 7- 39 ...
Page 182
... D31–D0 NOTE: The selected device increments the value on A3 and A2. Figure 7-27. Line Read Access Terminated with 7-40 For More Information On This Product A3 M68040 USER’S MANUAL Go to: www.freescale.com TEA ENDS BURST – NO EXCEPTION TAKEN TEA Timing MOTOROLA ...
Page 183
... The processor retries any read or write cycles of a read-modify-write transfer separately; LOCK remains asserted during the entire retry sequence. If the last bus cycle of a locked access is retried, LOCKE remains asserted through the retry of the write cycle. MOTOROLA For More Information On This Product, C1 ...
Page 184
... BCLK A31–A0 UPA1, UPA0 SIZ1, SIZ0 TT1, TT0 TM2–TM0 R/W CIOUT TS TIP TA TEA TBI D31–D0 RETRY SIGNALED Figure 7-29. Retry Operation on Line Write 7-42 For More Information On This Product LINE RETRY CYCLE M68040 USER’S MANUAL Go to: www.freescale.com C5 MOTOROLA ...
Page 185
... When a write operation reaches the integer unit’s write-back stage, all previous instructions have completed. When a read access to a serialized noncachable page begins, only a bus error exception MOTOROLA For More Information On This Product, M68040 USER’S MANUAL Go to: www ...
Page 186
... Since the user defines the functionality of the external arbiter, it can be configured to support any desired priority scheme. For systems in which the processor is the only possible bus master, the bus can 7-44 For More Information On This Product, M68040 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
Page 187
... The processor negates BR when there are no pending accesses to allow the external arbiter to grant the bus to the alternate bus master if necessary. MOTOROLA For More Information On This Product, M68040 USER’S MANUAL Go to: www.freescale.com ...
Page 188
... Figure 7- bus arbitration state diagram illustrating the relationship of these five states with an example of an external bus arbiter circuit. Table 7-6 lists the five states and the conditions that indicate them. 7-46 For More Information On This Product, M68040 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
Page 189
... OWNERSHIP, *BG IBR BBO DRIVEN BY MC68040, THREE-STATED *ENDCYCLE BBI *BG BB BBI BBO BR IBR D Q BCLK Figure 7-30. M68040 Internal Interpretation State Diagram and MOTOROLA For More Information On This Product, *BG TSI *BBI BG TSI *BG IDLE, BBO DRIVEN BY MC68040, TSI *THREE-STATED BBI *BG BG* IBR IBR SNOOP, ...
Page 190
... Active Bus Cycle bus is driven with defined values; TIP is asserted. M68040 asserts BB; arbiter asserts BG; Park bus is driven with undefined values; TIP is asserted. M68040 three-states BB; arbiter asserts and Snooped BG; M68040 does not drive the bus. M68040 USER’S MANUAL Go to: www.freescale.com Conditions MOTOROLA ...
Page 191
... If an external bus arbiter is designed to wait for the M68040 to assert BB before proceeding, then the system experiences an extended period of time in which bus arbitration is locked. Motorola recommends that an external bus arbiter not assume that there is a direct relationship between BR and and BG signals. ...
Page 192
... BCLK A31–A0 TRANSFER ATTRIBUTES TS TIP TA D31– AM_BR * AM_BG ALTERNATE MASTER * AM indicates the alternate bus master. Figure 7-32. Processor Bus Request Timing 7-50 For More Information On This Product PROCESSOR M68040 USER’S MANUAL Go to: www.freescale.com C8 C9 ALTERNATE MASTER MOTOROLA ...
Page 193
... TRANSFER ATTRIBUTES R/W TS TIP TA TEA D31– AM_BR * AM_BG PROCESSOR * AM indicates the alternate bus master. Figure 7-33. Arbitration During Relinquish and Retry Timing MOTOROLA For More Information On This Product ALTERNATE MASTER M68040 USER’S MANUAL Go to: www.freescale.com C7 C8 PROCESSOR 7- 51 ...
Page 194
... Each processor is allowed to own the bus without relinquishing it to maintain the integrity of locked transfers. This example also illustrates 7-52 For More Information On This Product BUS BUS OWNED IMPLICITLY AND ACTIVE OWNED PROCESSOR M68040 USER’S MANUAL Go to: www.freescale.com BUS OWNED AND IDLE MOTOROLA ...
Page 195
... A. Note that even though processor 1 recognizes BG1 is asserted, it does not take the bus because processor 1 asserts BB whenever the boundary condition results in processor 1 performing another bus cycle. The external arbiter stays in state A until LOCKE is asserted, then proceeds to state B to MOTOROLA For More Information On This Product, BB LOCK ...
Page 196
... Similar to the M68040 fairness arbitration example, the restriction on using LOCKE applies to this example. Figure 7-36 illustrates the state diagram for dual M68040 prioritized arbitration. 7-54 For More Information On This Product, M68040 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
Page 197
... M68040 is performing a locked bus operation. In either case, the M68040 is the default bus master; if there are no pending requests from either device, the external arbiter gives the bus to the M68040. Similar to the M68040 fairness arbitration example, the restriction on using LOCKE applies to this example. MOTOROLA For More Information On This Product, BB BR2 ...
Page 198
... For More Information On This Product, 040_BR AM_BR, 040_BG* BB 040_BR BB AM_BR 040_BR* AM_BR LOCK LOCKE V AM_BR LOCK* BB LOCK LOCKE* M68040 USER’S MANUAL Go to: www.freescale.com STATE C AM_BG*, 040_BG 040_BR BB* STATE B AM_BG*, 040_BG BB 040_BR* STATE C AM_BG*, 040_BG 040_BR BB* STATE B AM_BG*, 040_BG BB LOCK LOCK LOCKE MOTOROLA ...
Page 199
... In either case, the M68040 is the default bus master; therefore, if there are no pending requests from either device, the external bus arbiter gives the bus to the M68040. ABR CLK ABGACK CLK Figure 7-38. Sample Synchronizer Circuit MOTOROLA For More Information On This Product, M68040 USER’S MANUAL Go to: www.freescale.com ...
Page 200
... V RV* V RA* S4 040_BG*, AM_BG 040_BG*, 040_BG*, AM_BG* AM_BG 040_BG*, AM_BG RV RV* V RA* S4 040_BG*, AM_BG 040_BR 040_BG*, 040_BG*, AM_BG* AM_BG 040_BG*, AM_BG RV MOTOROLA AV AV ...