mc68ec030 Freescale Semiconductor, Inc, mc68ec030 Datasheet
mc68ec030
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mc68ec030 Summary of contents
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... Technical Summary Second-Generation 32-Bit Enhanced Embedded Controller The MC68EC030 is a 32-bit embedded controller that streamlines the functionality of an MC68030 for the requirements of embedded control applications. The MC68EC030 is optimized to maintain performance while using cost-effective memory subsystems. The rich instruction set and addressing mode capabilities of the MC68020, MC68030, and MC68040 have been maintained, allowing a clear migration path for M68000 systems ...
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... MC68EC030 also supports the fast synchronous bus of the MC68030 for off- chip caches and fast memories. Like the MC68030, the MC68EC030 bus is capable of fetching up to four long words of data in a burst mode compatible with DRAM chips that have burst capability. Burst mode can reduce ( percent) the time necessary to fetch the four long words ...
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... The data cache uses a write-through policy with programmable write allocation for cache misses MC68EC030 TECHNICAL DATA For More Information On This Product, Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. 4 MC68EC030 TECHNICAL DATA For More Information On This Product, Go to: www.freescale.com ...
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... Each segment can be marked as cacheable or non cacheable to control cache accesses to that memory space. As shown in the programming models (see Figures 3 and 4), the MC68EC030 has 16 32-bit general- purpose registers, a 32-bit program counter, two 32-bit supervisor stack pointers, a 16-bit status register, a 32-bit vector base register, two 3-bit alternate function code registers, two 32-bit cache handling (address and control) registers, and two 32-bit transparent translation registers. Registers D0– ...
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... INTERRUPT PRIORITY MASK EXTEND NEGATIVE CONDITION CODES OVERFLOW CARRY Figure 5. Status Register MC68EC030 TECHNICAL DATA For More Information On This Product, Go to: www.freescale.com INTERRUPT STACK POINTER MASTER STACK POINTER STATUS REGISTER VECTOR BASE REGISTER ALTERNATE FUNCTION CODE REGISTERS CACHE CONTROL ...
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... Freescale Semiconductor, Inc. All microprocessors of the M68000 Family support instruction tracing (via the T0 status bit in the MC68EC030) where each instruction executed is followed by a trap to a user-defined trace routine. The MC68EC030, like the MC68030 and MC68040, also has the capability to trace only on change-of-flow instructions (branch, jump, subroutine call and return, etc ...
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... The program counter relative mode also has index and offset capabilities; this addressing mode is generally required to support position- independent software. In addition to these addressing modes, the MC68EC030 provides data operand sizing and scaling; these features provide performance enhancements to the programmer. ...
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... Freescale Semiconductor, Inc. Table 1. MC68EC030 Addressing Modes Addressing Modes Register Direct Addressing Data Register Direct Address Register Direct Register Indirect Address Register Indirect Address Register Indirect with Postincrement Address Register Indirect with Predecrement Address Register Indirect with Displacement Register Indirect with Index ...
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... Freescale Semiconductor, Inc. INSTRUCTION SET OVERVIEW The MC68EC030 instruction set is listed in Table 2. Each instruction, with few exceptions, operates on bytes, words, and long words, and most instructions can use any of the 18 addressing modes. The MC68EC030 is upward source- and object-level code compatible with the M68000 Family because it supports all instructions of previous family members ...
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... the hit ratio or the percentage of time that the data is found in the cache. Thus, for a given system design, the two MC68EC030 on-chip caches provide an even more substantial CPU performance increase over that obtainable with the MC68020 instruction cache. Alternately, slower and less expensive memories can be used for the same controller performance ...
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... FC2 (supervisor/user) value, four valid bits (one for each long-word entry), and the four long-word entries (see Figure 6). The instruction cache is automatically filled by the MC68EC030 whenever a cache miss occurs; using the burst transfer capability four long words can be filled in one burst operation. The caches cannot be manipulated directly by the programmer except by the use of the CACR, which provides cache clearing and cache entry clearing facilities ...
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... Figure 7. On-Chip Data Cache Organization OPERAND TRANSFER MECHANISM The MC68EC030 offers three different mechanisms by which data can be transferred into and out of the chip. Asynchronous bus cycles, compatible with the asynchronous bus on the MC68020 and MC68030, can transfer data in a minimum of three clock cycles; the amount of data transferred on each cycle is ...
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... If the port responds that bits wide, the MC68EC030 latches all 32 bits of data and continues. If the port responds that bits wide, the MC68EC030 latches the 16 valid bits of data and continues. An 8-bit port is handled similarly but has four bus read cycles. Each port is fixed in the assignment to particular sections of the data bus. However, the MC68EC030 has no restrictions concerning the alignment of operands in memory ...
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... HALT BURST READ CYCLES The MC68EC030 provides support for burst filling of its on-chip instruction and data caches, adding to the overall system performance. The on-chip caches are organized with a line size of four long words; there is only one tag for the four long words in a line. Since locality of reference is present to some degree in most programs, filling of all four entries when a single entry misses can be advantageous, especially if the time spent filling the additional entries is minimal ...
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... If the exception is a reset, the M-bit is simply cleared, and the reset vector is accessed. The MC68EC030 provides the same extensions to the exception stacking process as the MC68020, MC68030, and MC68040. If the M-bit is set, the master stack pointer (MSP) is used for all task-related exceptions ...
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... The coprocessor interface is a mechanism for extending the instruction set of the M68000 Family. The interface provided on the MC68EC030 is the same as that on the MC68020 and MC68030. Examples of these extensions are the addition of specialized data operands for the existing data types or, for the case of floating point, the inclusion of new data types and operations MC68881/MC68882 floating-point coprocessors ...
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... Bus response signal that indicates a port size of 32 bits and that data STERM may be latched on the next falling clock edge. Prevents data from being loaded into the MC68EC030 instruction and CIIN data caches. Reflects the CI bit in ACx registers; indicates that external caches CIOUT should ignore these accesses ...
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... Signal Name Mnemonic Power Supply Ground No Connect CLK Clock input to the controller. Table 3. Signal Index – Continued V CC Power supply. GND Ground connection not connect. MC68EC030 TECHNICAL DATA For More Information On This Product, Go to: www.freescale.com Function 1 9 ...
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... +273 C) K=P D • 273 •P D MC68EC030 TECHNICAL DATA For More Information On This Product, Go to: www.freescale.com The device contains circuitry to Unit protect the inputs against damage due to high static voltages or V electric fields; however, precautions should be taken to ...
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... Note that the testing levels used to verify conformance to the AC specifications does not affect the guaranteed DC operation of the device as specified in the DC electrical specifications Substitution of JC for JA in equation (1) results in a lower MC68EC030 TECHNICAL DATA For More Information On This Product, Go to: www.freescale.com JC and ...
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... 2.0 V VALID OUTPUT 0.8 V VALID OUTPUT 2.0 V 2.0 V VALID INPUT 0 2.0 V 0.8 V 2 2.0 V 0.8 V MC68EC030 TECHNICAL DATA For More Information On This Product, Go to: www.freescale.com 2 2.0 V 2.0 V VALID OUTPUT n+1 0 DRIVE 2 2.4 V VALID INPUT 0.8 V DRIVE TO 0 ...
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... SIZ0–SIZ1, FC0–FC2 CBREQ, CIOUT, STATUS, REFILL BG , D0–D31 CBREQ, AS, DS, R /W, RMC, DBEN, IPEND HALT,RESET ECS, OCS CIOUT, STATUS, REFILL All Other MC68EC030 TECHNICAL DATA For More Information On This Product, Go to: www.freescale.com Symbol Min Unit GND ...
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... CIOUT , Address Data RMC IPEND CIOUT , , , Address CBREQ Valid CIOUT Address Valid to Asserted Negated RMC CIOUT , Address MC68EC030 TECHNICAL DATA For More Information On This Product, Go to: www.freescale.com MHz Unit Min Min ...
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... Invalid AS , BERR , HALT , AVEC Negated BERR , HALT , AVEC Negated Valid (Skew) RMC Not Asserted) Negated Negated MC68EC030 TECHNICAL DATA For More Information On This Product, Go to: www.freescale.com MHz Unit Min Min — 16 — ns — 40 — — ...
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... Clock Low Asynchronous Read Asynchronous Write Synchronous Read Synchronous Write HALT , Asserted Negated (Rerun) REFIL L Asserted REFILL Negated MC68EC030 TECHNICAL DATA For More Information On This Product, Go to: www.freescale.com 25 MHz 40 MHz Unit Min Min — 5 — — ...
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... READ cycles with no wait states. 10. These specifications allow system designers to guarantee that an alternate bus master has stopped driving the bus when the MC68EC030 regains control of the bus after an arbitration sequence. 11. DS will not be asserted for synchronous write cycles with no wait states ...
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... R DBEN 40 45 DSACK0 31A DSACK1 31 D31-D0 27 BERR HALT 47A ALL INPUTS 60 CIIN 61 CBREQ Asynchronous Read Cycle Timing Diagram MC68EC030 TECHNICAL DATA For More Information On This Product, Go to: www.freescale.com 29A 27A 48 47B ...
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... 12A 10 10B 10A 14A 31A 27A Asynchronous Write Cycle Timing Diagram MC68EC030 TECHNICAL DATA For More Information On This Product, Go to: www.freescale.com 15A 25A ...
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... CLK RMC 6 12A ECS 6A OCS 14B 46A R/W 40 DBEN CIOUT CBREQ 61 STERM 60 CIIN CBACK D31-D0 27 Synchronous Read Cycle Timing Diagram MC68EC030 TECHNICAL DATA For More Information On This Product, Go to: www.freescale.com 45A 12 30A ...
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... CLK 6 RMC 12A ECS 6A OCS 9 AS 14B DS 20 46A R/W 42 45A DBEN BERR HALT 27A Synchronous Write Cycle Timing Diagram MC68EC030 TECHNICAL DATA For More Information On This Product, Go to: www.freescale.com 28A 28A 3 1 ...
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... The voltage swing through this range should start outside and pass through the range so that the rise or fall will be linear between 0.8 V and 2.0 V. Figure 15 Bus Arbitration Timing Diagram MC68EC030 TECHNICAL DATA For More Information On This Product, Go to: www.freescale.com 33 37A 34 37 39A ...
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... Freescale Semiconductor, Inc. CLK IPEND CDIS STATUS REFILL 47A 62 Figure 16. Other Signal Timings MC68EC030 TECHNICAL DATA For More Information On This Product, Go to: www.freescale.com ...
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... B A The MC68030 has four additional guide pins not present on the MC68EC030. Therefore, an MC68EC030 fits in a socket designed for the MC68030, but the MC68030 does not necessary fit in a socket intended for the MC68EC030. The Vcc and GND pins are separated into three groups to provide individual power ...
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... NOTES: 0.135 1. DIMENSIONING AND TOLERANCING PER 0.022 ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH 0.195 3. DIMENSION D INCLUDES LEAD FINISH. 0.060 0.150 MC68EC030 TECHNICAL DATA For More Information On This Product, Go to: www.freescale.com 0.76 (0.030 ...
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... Freescale Semiconductor, Inc. Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Motorola products are not ...