mc68hc705c9a Freescale Semiconductor, Inc, mc68hc705c9a Datasheet
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... MC68HC705C9A Advance Information Data Sheet M68HC05 Microcontrollers MC68HC705C9A Rev. 4.1 9/2005 freescale.com This document contains certain information on a new product.Specifications and information herein are subject to change without notice. ...
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... MC68HC705C9A Advance Information Data Sheet To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://www.freescale.com/ The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location ...
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Revision History MC68HC05C9A Advance Information Data Sheet, Rev. 4.1 4 Freescale Semiconductor ...
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List of Chapters Chapter 1 General Description ...
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List of Chapters MC68HC05C9A Advance Information Data Sheet, Rev. 4.1 6 Freescale Semiconductor ...
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Table of Contents 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Timer I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents MC68HC05C9A Advance Information Data Sheet, Rev. 4.1 12 Freescale Semiconductor ...
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... Introduction The MC68HC705C9A HCMOS microcomputer is a member of the M68HC05 Family. The MC68HC705C9A is the EPROM version of the MC68HC05C9A and also can be configured as the EPROM version of the MC68HC05C12A. The MC68HC705C9A memory map consists of 12,092 bytes of user EPROM and 176 bytes of RAM when it is configured as an MC68HC05C12A and 15,932 bytes of user EPROM and 352 bytes of RAM when configured as an MC68HC05C9A ...
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General Description BOOT ROM — 239 BYTES USER EPROM — 15,936 BYTES USER RAM —352 BYTES CPU CONTROL IRQ M68HC05 MCU RESET RESET PROGRAM COUNTER OSC1 INTERNAL OSCILLATOR OSC2 COP WATCHDOG DIVIDE ...
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... Configuration Options The options and functions of the MC68HC705C9A can be configured to emulate either the MC68HC05C9A or the MC68HC05C12A. The ROM device MC68HC05C9A has eight ROM mask options to select external interrupt/internal pullup capability on each of the eight port B bits. Other optional features are controlled by software addressable registers during operation of the microcontroller ...
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General Description • The port D data direction register ($0007) is disabled and the seven port D pins become input only. • SPI output signals (MOSI, MISO, and SCK) do not require the data direction register control for output capability. ...
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Bit 7 Read: SEC Write: C12A — C12A/C9A Mode Select Bit This read/write bit selects between C12A configuration and C9A configuration Configured to emulate MC68HC05C12A 0 = Configured to emulate MC68HC05C9A C12IRQ — C12A Interrupt Request Bit ...
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General Description 1.5 Software-Programmable Options (MC68HC05C9A Mode Only) The C9A option register (OR), shown in register contains the programmable bits for the following options: • Map two different areas of memory between RAM and EPROM, one of 48 bytes and ...
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Functional Pin Descriptions Figure 1-5, Figure 1-6, Figure 1-7, and A functional description of the pins follows. A line over a signal name indicates an active low signal. For example, RESET is active high and RESET is active low. ...
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General Description Figure 1-6. 42-Pin SDIP Pin Assignments MC68HC05C9A Advance Information Data Sheet, Rev. 4 RESET IRQ 2 OSC1 OSC2 PP 39 PA7 4 TCAP 38 PA6 5 PD7 37 PA5 ...
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PA5 8 PA4 9 PA3 10 PA2 11 PA1 12 PA0 13 PB0 14 PB1 15 PB2 16 PB3 N/C 17 Figure 1-7. 44-Lead PLCC Pin Assignments The above 44-pin PLCC pin assignment diagram is for compatibility with MC68HC05C9A. ...
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General Description 1 PA6 2 PA5 3 PA4 4 PA3 5 PA2 6 PA1 7 PA0 8 PB0 9 PB1 10 PB2 11 PB3 Figure 1-8. 44-Pin QFP Pin Assignments 1.6.1 V and Power is supplied to ...
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RESET As an input pin, this active low RESET pin is used to reset the MCU to a known startup state by pulling RESET low output pin, when in MC68HC05C9A mode only, the RESET pin indicates that ...
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General Description MC68HC05C9A Advance Information Data Sheet, Rev. 4.1 24 Freescale Semiconductor ...
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Chapter 2 Memory 2.1 Introduction The MCU has a 16-Kbyte memory map when configured as either an MC68HC05C9A or an MC68HC05C12A. The memory map consists of registers (I/O, control, and status), user RAM, user EPROM, bootloader ROM, and reset and ...
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Memory $0000 I/O REGISTERS 32 BYTES $001F $0020 USER EPROM RAM 48 BYTES 48 BYTES RAM0 = 0 RAM0 = 1 $004F $0050 RAM 176 BYTES $00BF $00C0 (STACK) 64 BYTES $00FF $0100 USER EPROM RAM 128 BYTES 128 BYTES ...
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I/O REGISTERS 32 BYTES $001F $0020 USER EPROM 48 BYTES $004F $0050 RAM 176 BYTES $00BF $00C0 (STACK) 64 BYTES $00FF $0100 UNUSED 3840 BYTES $0FFF $1000 USER EPROM 12,032 BYTES $3EFF $3F00 BOOTLOADER ROM AND VECTORS 240 BYTES ...
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... Memory 2.4 EPROM Security A security feature has been incorporated into the MC68HC705C9A to help prevent external access to the contents of the EPROM in any mode of operation. Once enabled, this feature can be disabled only by completely erasing the EPROM. For OTP (plastic) packages, once the security feature has been enabled, it cannot be disabled ...
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Addr $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F $0010 $0011 $0012 $0013 $0014 $0015 $0016 $0017 $0018 $0019 $001A $001B $001C $001D $001E $001F MC68HC05C9A Advance Information Data Sheet, Rev. 4.1 ...
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Memory Addr. Register Name Port A Data Register $0000 (PORTA) See page 47. Port B Data Register $0001 (PORTB) See page 48. Port C Data Register $0002 (PORTC) See page 48. Port D Data Register $0003 (PORTD) See page 48. ...
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Addr. Register Name SCI Baud Rate Register $000D BAUD See page 69. SCI Control Register 1 $000E (SCCR1) See page 65. SCI Control Register 2 $000F (SCCR2) See page 66. SCI Status Register $0010 (SCSR) See page 68. SCI Data ...
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Memory Addr. Register Name Timer Register Low (TRL) $0019 See page 55. Alternate Timer Register High $001A (ATRH) See page 55. Alternate Timer Register Low $001B (ATRL) See page 55. EPROM Programming Register $001C (EPR) COP Reset Register $001D (COPRST) ...
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Chapter 3 Central Processor Unit (CPU) 3.1 Introduction This section contains the basic programmers model and the registers contained in the CPU. 3.2 CPU Registers The MCU contains five registers as shown in the programming model of order is shown ...
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Central Processor Unit (CPU) 3.2.1 Accumulator (A) The accumulator is a general-purpose 8-bit register used to hold operands and results of arithmetic calculations or data manipulations. 3.2.2 Index Register (X) The index register is an 8-bit register used for the ...
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Chapter 4 Interrupts 4.1 Introduction The MCU can be interrupted by five different sources, four maskable hardware interrupts, and one non-maskable software interrupt: • External signal on the IRQ pin or port B pins • 16-bit programmable timer • Serial ...
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Interrupts Table 4-1. Vector Addresses for Interrupts and Resets Function Source Power-on reset Reset RESET pin COP watchdog Software interrupt User code (SWI) External IRQ pin port B pins interrupt ICF bit Timer OCF bit interrupts TOF bit TDRE bit ...
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Y Y RESTORE REGISTERS FROM STACK: CCR,A,X,PC MC68HC05C9A Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor FROM RESET I BIT IN CCR SET? N CLEAR IRQ IRQ OR PORT B Y REQUEST EXTERNAL LATCH INTERRUPT N INTERNAL Y TIMER INTERRUPT ...
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Interrupts 4.4 Timer Interrupt Three different timer interrupt flags cause a timer interrupt whenever they are set and enabled. The interrupt flags are in the timer status register (TSR), and the enable bits are in the timer control register (TCR). ...
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Chapter 5 Resets 5.1 Introduction The MCU can be reset four ways: by the initial power-on reset function active low input to the RESET pin, by the COP the clock monitor. A reset immediately stops the ...
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Resets t V VDDR DD 2 OSC1 4064t CYC t CYC INTERNAL 1 CLOCK INTERNAL ADDRESS BUS 1 3FFE 3FFF INTERNAL DATA NEW NEW BUS 1 PCH PCL RESET 4 (C9A) RESET (C12A) Notes: 1. Internal timing signal and bus ...
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MC68HC05C9A Compatible COP This COP is controlled with two registers; one to reset the COP timer and the other to enable and control COP and clock monitor functions. INTERNAL ÷4 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 CPU ...
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Resets $001E Bit 7 Read: 0 Write: Reset Unimplemented Figure 5-5. COP Control Register (COPCR) COPF — Computer Operating Properly Flag Reading the COP control register clears COPF COP or clock monitor reset has occurred. 0 ...
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... In the event that an inadvertent STOP instruction is executed, neither COP will allow the system to recover. The MC68HC705C9A offers two solutions to this problem, one available in C9A mode (see Clock Monitor Reset) and one available in C12A mode (see 5 ...
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... STOP instruction as a NOP so the device will never enter stop mode; if the user code is not being executed properly, the COP will provide a system reset. To emulate this feature on the MC68HC705C9A (configured as an MC68HC05C12A), set the STOPDIS bit in the C12MOR. Stop mode will not actually be disabled as on the MC68HC05C12A, but the clock monitor circuit will be activated ...
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Chapter 6 Low-Power Modes 6.1 Introduction This section describes the low-power modes. 6.2 Stop Mode The STOP instruction places the MCU in its lowest-power consumption mode. In stop mode, the internal oscillator is turned off, halting all internal processing, including ...
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Low-Power Modes 6.3 Wait Mode The WAIT instruction places the MCU in a low-power consumption mode, but the wait mode consumes more power than the stop mode. All CPU action is suspended, but the timer, serial communications interface (SCI), serial ...
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Chapter 7 Input/Output (I/O) Ports 7.1 Introduction This section briefly describes the 31 input/output (I/O) lines arranged as one 7-bit and three 8-bit ports. All of these port pins are programmable as either inputs or outputs under software control of ...
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Input/Output (I/O) Ports 7.3 Port B Port 8-bit bidirectional port. The port B data register is at $0001 and the data direction register (DDR $0005. The contents of the port B data register are indeterminate ...
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PORT B EXTERNAL INTERRUPT MASK OPTION REGISTER CONTROLLED READ $0005 WRITE $0005 RESET WRITE $0001 READ $0001 SOFTWARE OR MASK OPTION REGISTER CONTROLLED DEPENDENT ON CONFIGURATION FROM OTHER PORT B PINS IRQ RESET EXTERNAL INTERRUPT VECTOR FETCH MC68HC05C9A Advance Information ...
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Input/Output (I/O) Ports MC68HC05C9A Advance Information Data Sheet, Rev. 4.1 50 Freescale Semiconductor ...
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Chapter 8 Capture/Compare Timer 8.1 Introduction This section describes the operation of the 16-bit capture/compare timer. of the capture/compare subsystem. HIGH LOW BYTE BYTE $16 OUTPUT $17 COMPARE REGISTER OUTPUT COMPARE CIRCUIT TIMER STATUS ICF OCF TOF $13 REG. INTERRUPT ...
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Capture/Compare Timer 8.2 Timer Operation The core of the capture/compare timer is a 16-bit free-running counter. The counter provides the timing reference for the input capture and output compare functions. The input capture and output compare functions provide a means ...
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Timer Control Register The timer control register (TCR), shown in • Enables input capture interrupts • Enables output compare interrupts • Enables timer overflow interrupts • Controls the active edge polarity of the TCAP signal • Controls the active ...
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Capture/Compare Timer 8.3.2 Timer Status Register The timer status register (TSR), shown in • An active signal on the TCAP pin, transferring the contents of the timer registers to the input capture registers • A match between the 16-bit counter ...
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Timer Registers The timer registers (TRH and TRL), shown in 16-bit counter. Reading TRH before reading TRL causes TRL to be latched until TRL is read. Reading TRL after reading the timer status register clears the timer overflow flag ...
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Capture/Compare Timer 8.3.5 Input Capture Registers When a selected edge occurs on the TCAP pin, the current high and low bytes of the 16-bit counter are latched into the input capture registers (ICRH and ICRL). Reading ICRH before reading ICRL ...
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To prevent OCF from being set between the time it is read and the time the output compare registers are updated, use this procedure: 1. Disable interrupts by setting the I bit in the condition code register. 2. Write to ...
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Capture/Compare Timer MC68HC05C9A Advance Information Data Sheet, Rev. 4.1 58 Freescale Semiconductor ...
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Chapter 9 Serial Communications Interface (SCI) 9.1 Introduction This section describes the on-chip asynchronous serial communications interface (SCI). The SCI allows full-duplex, asynchronous, RS232 or RS422 serial communication between the MCU and remote devices, including other MCUs. The transmitter and ...
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Serial Communications Interface (SCI) 9.4 SCI Transmitter Features Features of the SCI transmitter include: • Transmit data register empty flag • Transmit complete flag • Send break INTERNAL BUS TRANSMIT $0011 DATA REGISTER TRANSMIT TDO DATA SHIFT PIN REGISTER TRDE ...
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Functional Description A block diagram of the SCI is shown in the wakeup method (WAKE bit) and data word length (M bit) of the SCI. SCCR2 provides control bits that individually enable the transmitter and receiver, enable system interrupts, ...
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Serial Communications Interface (SCI) 9.6 Data Format Receive data or transmit data is the serial data that is transferred to the internal data bus from the receive data input pin (RDI) or from the internal bus to the transmit data ...
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Address Mark Wakeup In address mark wakeup, the most significant bit (MSB character is used to indicate whether address (logic 1) or data (logic 0) character. Sleeping receivers will wake up whenever an address ...
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Serial Communications Interface (SCI) 9.11 Start Bit Detection When the input (idle) line is detected low tested for three more sample times (referred to as the start edge verification samples in Figure 0, a valid start bit has ...
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Transmit Data Out (TDO) Transmit data is the serial data from the internal data bus that is applied through the SCI to the output line. Data format is as discussed in a bit time by using a derivative of ...
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Serial Communications Interface (SCI) T8 — Bit 8 (Transmitted) When the SCI is transmitting 9-bit characters the ninth bit of the transmitted character loaded into the transmit shift register at the same time that the SCDR ...
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RIE — Receiver Interrupt Enable Bit This read/write bit enables SCI interrupt requests when the RDRF flag or the OR flag becomes set. Resets clear the RIE bit RDRF interrupt requests enabled 0 = RDRF interrupt requests disabled ...
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Serial Communications Interface (SCI) $0010 Bit 7 Read: TDRE Write: Reset Unimplemented TDRE — Transmit Data Register Empty Flag This clearable, read-only flag is set when the data in the SCDR transfers to the transmit shift register. TDRE ...
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FE — Receiver Framing Error Flag This clearable, read-only flag is set when there is a logic 0 where a stop bit should be in the character shifted into the receive shift register. If the received word causes both a ...
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Serial Communications Interface (SCI) MC68HC05C9A Advance Information Data Sheet, Rev. 4.1 70 Freescale Semiconductor ...
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Chapter 10 Serial Peripheral Interface (SPI) 10.1 Introduction The serial peripheral interface (SPI interface built into the device which allows several MC68HC05 MCUs, or MC68HC05 MCU plus peripheral devices interconnected within a single printed circuit board. ...
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Serial Peripheral Interface (SPI) SS SCK SCK SCK SCK MISO/MOSI MSB 10.3.1 Master In Slave Out (MISO) The MISO line is configured as an input in a master device and as an output in a slave device one ...
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SPSR. In master mode the SS pin can be selected general-purpose output (when configured as an MC68HC05C9A) by writing bit 5 of the port D data direction register, thus disabling the mode fault ...
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Serial Peripheral Interface (SPI) The SPI is double buffered on read, but not on write write is performed during data transfer, the transfer occurs uninterrupted, and the write will be unsuccessful. This condition will cause the write collision ...
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Bit 7 Read: SPIE Write: Reset Undetermined Figure 10-4. SPI Control Register (SPCR) SPIE — Serial Peripheral Interrupt Enable Bit This read/write bit enables SPI interrupts. Reset clears the SPIE bit SPI interrupts enabled ...
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Serial Peripheral Interface (SPI) SPR[1:0] 10.5.2 Serial Peripheral Status Register The SPI status register (SPSR), shown in • SPI transmission complete • Write collision • Mode fault $000B Bit 7 Read: SPIF Write: Reset: 0 SPIF — SPI Transfer Complete ...
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Clearing the MODF bit is accomplished by reading the SPSR (with MODF set), followed by a write to the SPCR. Control bits SPE and MSTR may be restored by user software to their original state during this clearing sequence or ...
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Serial Peripheral Interface (SPI) MC68HC05C9A Advance Information Data Sheet, Rev. 4.1 78 Freescale Semiconductor ...
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Chapter 11 Instruction Set 11.1 Introduction The microcontroller unit (MCU) instruction set has 62 instructions and uses eight addressing modes. The instructions include all those of the M146805 CMOS (complementary metal oxide silicon) Family plus one more: the unsigned multiply ...
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Instruction Set 11.2.4 Extended Extended instructions use three bytes and can access any address in memory. The first byte is the opcode; the second and third bytes are the high and low bytes of the operand address. When using the ...
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Instruction Types The MCU instructions fall into the following five categories: • Register/Memory instructions • Read-Modify-Write instructions • Jump/Branch instructions • Bit Manipulation instructions • Control instructions 11.3.1 Register/Memory Instructions These instructions operate on CPU registers and memory locations. ...
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Instruction Set 11.3.2 Read-Modify-Write Instructions These instructions read a memory location or a register, modify its contents, and write the modified value back to the memory location or to the register. Do not use read-modify-write operations on write-only registers. Table ...
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Jump/Branch Instructions Jump instructions allow the CPU to interrupt the normal sequence of the program counter. The unconditional jump instruction (JMP) and the jump-to-subroutine instruction (JSR) have no register operand. Branch instructions allow the CPU to interrupt the normal ...
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Instruction Set 11.3.4 Bit Manipulation Instructions The CPU can set or clear any writable bit in the first 256 bytes of memory, which includes I/O registers and on-chip RAM locations. The CPU can also test and branch based on the ...
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Instruction Set Summary Table 11-6. Instruction Set Summary (Sheet Source Operation Form ADC #opr ADC opr ADC opr Add with Carry ADC opr,X ADC opr,X ADC ,X ADD #opr ADD opr ADD opr Add without Carry ...
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Instruction Set Table 11-6. Instruction Set Summary (Sheet Source Operation Form BIT #opr BIT opr BIT opr Bit Test Accumulator with Memory Byte BIT opr,X BIT opr,X BIT ,X BLO rel Branch if Lower (Same as BCS) ...
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Table 11-6. Instruction Set Summary (Sheet Source Operation Form CLR opr CLRA CLRX Clear Byte CLR opr,X CLR ,X CMP #opr CMP opr CMP opr Compare Accumulator with Memory Byte CMP opr,X CMP opr,X CMP ,X COM ...
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Instruction Set Table 11-6. Instruction Set Summary (Sheet Source Operation Form LDA #opr LDA opr LDA opr Load Accumulator with Memory Byte LDA opr,X LDA opr,X LDA ,X LDX #opr LDX opr LDX opr Load Index Register ...
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Table 11-6. Instruction Set Summary (Sheet Source Operation Form RTI Return from Interrupt RTS Return from Subroutine SBC #opr SBC opr SBC opr Subtract Memory Byte and Carry Bit from SBC opr,X Accumulator SBC opr,X SBC ,X ...
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Instruction Set Table 11-6. Instruction Set Summary (Sheet Source Operation Form TXA Transfer Index Register to Accumulator WAIT Stop CPU Clock and Enable Interrupts A Accumulator C Carry/borrow flag CCR Condition code register dd Direct address of ...
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Bit Manipulation Branch Read-Modify-Write DIR DIR REL DIR INH MSB LSB BRSET0 BSET0 BRA NEG NEGA 3 DIR 2 DIR 2 REL 2 DIR BRCLR0 ...
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Instruction Set MC68HC05C9A Advance Information Data Sheet, Rev. 4.1 92 Freescale Semiconductor ...
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Chapter 12 Electrical Specifications 12.1 Maximum Ratings Maximum ratings are the extreme limits to which the MCU can be exposed without permanently damaging it. The MCU contains circuitry to protect the inputs against damage from high static voltages; however, do ...
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Electrical Specifications 12.4 Power Considerations The average chip-junction temperature, T θ × where: = Ambient temperature, ° θ = Package thermal resistance, junction to ambient, °C ...
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Electrical Characteristics Characteristic Output voltage = 10.0 µA I oad L = –10.0 µA I oad L Output high voltage (I = –0.8 mA) PA7–PA0, PB7–PB0, PC6–PC0, oad L TCMP, PD7, PD0 (I = –1.6 mA) PD5–PD1 oad ...
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Electrical Specifications 12.6 3.3-Vdc Electrical Characteristics Characteristic Output voltage = 10.0 µA I oad L = –10.0 µA I oad L Output high voltage (I = –0.2 mA) PA7–PA0, PB7–PB0, PC6–PC0, oad L TCMP, PD7, PD0 (I = –0.4 mA) ...
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–40° to 85° 4.00 mA 3.00 mA 2.00 mA 1.00 mA Figure 12-2. Maximum Supply Current vs Internal Clock Frequency, V Figure 12-3. Maximum Supply Current vs Internal Clock Frequency, V ...
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Electrical Specifications 12.7 5.0-Vdc Control Timing Characteristic Frequency of operation Crystal External clock ÷ 2) Internal pperating frequency (f OSC Crystal External clock Cycle time Crystal oscillator startup time Stop recovery startup time (crystal oscillator) RESET pulse width Timer (2) ...
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Control Timing Characteristic Frequency of operation Crystal External clock ÷ 2) Internal operating frequency (f OSC Crystal External clock Cycle time Crystal oscillator startup time Stop recovery startup time (crystal oscillator) RESET pulse width Timer (2) Resolution Input ...
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Electrical Specifications IRQ PIN a. Edge-Sensitive Trigger Condition. The minimum pulse width (t or 250 MHz). The period t OP execute the interrupt service routine plus 19 t IRQ1 . . NORMALLY . USED WITH WIRED-OR ...
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V DD (2) OSC1 PIN INTERNAL (3) CLOCK INTERNAL (3) ADDRESS BUS INTERNAL (3) DATA BUS RESET PIN Notes: 1. Power-on reset threshold is typically between 1 V and OSC1 line is meant to represent ...
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Electrical Specifications 12.9 5.0-Vdc Serial Peripheral Interface Timing No. Characteristic Operating frequency Master Slave Cycle time 1 Master Slave Enable lead time 2 Master Slave Enable lag time 3 Master Slave Clock (SCK) high time 4 Master Slave Clock (SCK) ...
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Vdc Serial Peirpheral Interface Timing No. Characteristic Operating frequency Master Slave Cycle time 1 Master Slave Enable lead time 2 Master Slave Enable lag time 3 Master Slave Clock (SCK) high time 4 Master Slave Clock (SCK) low ...
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Electrical Specifications SS SS pin of master held high. (INPUT) SCK (CPOL = 0) NOTE (OUTPUT) SCK (CPOL = 1) NOTE (OUTPUT) MISO (INPUT) 10 (ref) MOSI (OUTPUT) 13 Note: This first clock edge is generated internally, but is not ...
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SS (INPUT) SCK (CPOL = 0) (INPUT) 2 SCK (CPOL = 1) (INPUT) 8 MISO SLAVE (OUTPUT) 6 MOSI MSB IN (INPUT) Note: Not defined but normally MSB of character just received. SS (INPUT) SCK (CPOL = 0) (INPUT) 2 ...
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Electrical Specifications MC68HC05C9A Advance Information Data Sheet, Rev. 4.1 106 Freescale Semiconductor ...
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Chapter 13 Mechanical Specifications 13.1 Introduction This section describes the dimensions of the plastic dual in-line package (DIP), plastic shrink dual in-line package (SDIP), plastic leaded chip carrier (PLCC), and quad flat pack (QFP) MCU packages. The following figures show ...
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Mechanical Specifications 13.3 42-Pin Plastic Shrink Dual In-Line (SDIP) Package (Case 858-01) - -T- SEATING PLANE 0.25 (0.010 Figure 13-2. 42-Pin Plastic SDIP Package (Case 858-01) MC68HC05C9A Advance Information Data ...
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Plastic Leaded Chip Carrier (PLCC) (Case 777-02) -N- - 0.010 (0.25) T L-M NOTES: 1. DATUMS -L-, -M-, AND -N- ARE DETERMINED WHERE TOP OF LEAD SHOLDERS ...
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Mechanical Specifications 13.5 44-Lead Quad Flat Pack (QFP) (Case 824A-01 - -D- A 0.20 (0.008) M 0.05 (0.002) A-B S 0.20 (0.008 -C- H SEATING PLANE G DATUM -H- PLANE W ...
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... FN = Plastic-leaded chip carrier (PLCC Quad flat pack (QFP) MC68HC05C9A Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor Table 14-1. MC Order Numbers Temperature Range –40°C to 85°C –40°C to 85°C –40°C to 85°C –40°C to 85°C Order Number MC68HC705C9ACP MC68HC705C9ACB MC68HC705C9ACFN MC68HC705C9ACFB 111 ...
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Ordering Information MC68HC05C9A Advance Information Data Sheet, Rev. 4.1 112 Freescale Semiconductor ...
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Appendix A EPROM Programming A.1 Introduction This section describes programming of the EPROM. A.2 Bootloader Mode RESET Bootloader mode is entered upon the rising edge of RESET if the IRQ logic one. The bootloader code resides in ...
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EPROM Programming A.4 Programming Register (PROG) This register is used to program the EPROM array. To program a byte of EPROM, set LATCH, write data to the desired address, and set EPGM for t $001X Bit 7 Read: Write: Reset: ...
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Appendix B M68HC05Cx Family Feature Comparisons Refer to Table B-1 for a comparison of the features for all the M68HC05C Family members. MC68HC05C9A Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor 115 ...
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C4 C4A 705C4A C8 USER ROM 4160 4160 — 7744 USER EPROM — — 4160 — CODE NO YES YES NO SECURITY RAM 176 176 176 176 OPTION REGISTER $1FDF (IRQ/RAM/ (IRQ/SEC) SEC) MASK OPTION NO NO ...
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... P.O. Box 5405 Denver, Colorado 80217 1-800-441-2447 or 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com MC68HC705C9A Rev. 4.1, 9/2005 RoHS-compliant and/or Pb- free versions of Freescale products have the functionality and electrical characteristics of their non-RoHS-compliant and/or non-Pb- free counterparts. For further information, see http://www.freescale.com or contact your Freescale sales representative. ...