MC68HC908QY2 MOTOROLA [Motorola, Inc], MC68HC908QY2 Datasheet
MC68HC908QY2
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MC68HC908QY2 Summary of contents
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... M68HC08 Microcontrollers WWW.MOTOROLA.COM/SEMICONDUCTORS MC68HC908QY4 MC68HC908QT4 MC68HC908QY2 MC68HC908QT2 MC68HC908QY1 MC68HC908QT1 Data Sheet MC68HC908QY4/D 9/2002 ...
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... For your convenience, the page number designators have been linked to the appropriate location. Motorola and the Stylized M Logo are registered trademarks of Motorola, Inc. DigitalDNA is a trademark of Motorola, Inc. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA © Motorola, Inc., 2002 3 ...
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... Revision History Revision Date Level September, N/A Initial release 2002 MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 4 Revision History Description Page Number(s) N/A MOTOROLA ...
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... Section 10. Timer Interface Module (TIM 129 Section 11. Analog-to-Digital Converter (ADC 151 Section 12. Input/Output (I/O) Ports . . . . . . . . . . . . . . . 161 Section 13. External Interrupt (IRQ 171 Section 14. Keyboard Interrupt Module (KBI 177 Section 15. Computer Operating Properly (COP 189 MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA List of Sections List of Sections 5 ...
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... List of Sections Section 16. Low-Voltage Inhibit (LVI 195 Section 17. Break Module (BREAK 201 Section 18. Electrical Specifications 211 Section 19. Mechanical Specifications . . . . . . . . . . . . . 223 Section 20. Ordering Information . . . . . . . . . . . . . . . . . 227 MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 6 List of Sections MOTOROLA ...
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... Data Sheet — MC68HC908QY4 1.1 1.2 1.3 1.4 1.5 1.6 1.7 2.1 2.2 2.3 2.4 2.5 3.1 3.2 3.3 MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA Section 1. General Description Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Pin Function Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Section 2. Memory Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . . 33 Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Input/Output (I/O) Section .35 Section 3. Random-Access Memory (RAM) Contents ...
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... MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 8 Section 4. FLASH Memory (FLASH) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 FLASH Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . 48 FLASH Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . 49 FLASH Program Operation FLASH Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . . . 53 Wait Mode Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Section 5. Configuration Register (CONFIG) Contents ...
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... MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA Arithmetic/Logic Unit (ALU Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Section 7. System Integration Module (SIM) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 RST and IRQ Pins Initialization . . . . . . . . . . . . . . . . . . . . . . . .79 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . . 79 Bus Timing ...
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... MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 10 Interrupt Status Registers Interrupt Status Register .91 Interrupt Status Register .91 Interrupt Status Register .92 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . . 93 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 SIM Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Break Flag Control Register ...
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... MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA Oscillator Out 2 (BUSCLKX4 109 Oscillator Out (BUSCLKX2 109 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 Oscillator During Break Mode 110 CONFIG2 Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Input/Output (I/O) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Oscillator Status Register 111 Oscillator Trim Register (OSCTRIM 112 Section 9 ...
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... MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 12 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 TIM Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . . 134 Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . .135 Pulse Width Modulation (PWM 135 Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . 136 Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . 137 PWM Initialization ...
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... MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156 Input/Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Input/Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 ADC Status and Control Register 157 ADC Data Register 159 ADC Input Clock Register . . . . . . . . . . . . . . . . . . . . . . . . . 159 Section 12. Input/Output (I/O) Ports Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Introduction ...
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... MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 14 Section 14. Keyboard Interrupt Module (KBI) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Keyboard Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 Keyboard Status and Control Register 182 Keyboard Interrupt Enable Register . . . . . . . . . . . . . . . . . . 184 Auto Wake-up Interrupt Request . . . . . . . . . . . . . . . . . . . . 185 Wait Mode 186 Stop Mode ...
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... MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA Section 16. Low-Voltage Inhibit (LVI) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 Polled LVI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Forced Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 Voltage Hysteresis Protection . . . . . . . . . . . . . . . . . . . . . . 198 LVI Trip Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 LVI Status Register .199 LVI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 Low-Power Modes ...
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... Typical Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 18.13 Analog-to-Digital Converter Characteristics . . . . . . . . . . . . . . 221 18.14 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 19.1 19.2 19.3 19.4 19.5 19.6 19.7 MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 16 Section 18. Electrical Specifications Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 212 Functional Operating Range 213 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 5-V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 214 5-V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 5-V Oscillator Characteristics ...
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... MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA Section 20. Ordering Information Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227 Table of Contents Table of Contents 17 ...
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... Table of Contents MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 18 Table of Contents MOTOROLA ...
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... MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA Title Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 MCU Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Memory Map Control, Status, and Data Registers . . . . . . . . . . . . . . . . . . . . . 36 FLASH Control Register (FLCR FLASH Programming Flowchart . . . . . . . . . . . . . . . . . . . . . . . .52 FLASH Block Protect Register (FLBPR FLASH Block Protect Start Address . . . . . . . . . . . . . . . . . . . . . 53 Configuration Register 2 (CONFIG2 Configuration Register 1 (CONFIG1 CPU Registers ...
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... TIM Status and Control Register (TSC 141 10-5 TIM Counter Registers (TCNTH:TCNTL 144 10-6 TIM Counter Modulo Registers (TMODH:TMODL .144 10-7 TIM Channel Status and Control Registers (TSC0:TSC1 145 MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 20 Title XTAL Oscillator External Connections . . . . . . . . . . . . . . . . . .106 RC Oscillator External Connections . . . . . . . . . . . . . . . . . . . . 107 Oscillator Status Register (OSCSTAT) ...
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... COP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190 15-2 COP Control Register (COPCTL 192 16-1 LVI Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 16-2 LVI Status Register (LVISR 199 17-1 Break Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 203 17-2 Break I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . 203 MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA Title List of Figures List of Figures Page ...
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... Break Flag Control Register (BFCR 209 18-1 RC versus Frequency (5 Volts @ 25° 216 18-2 RC versus Frequency (3 Volts @ 25° 219 18-3 Typical Operating I 18-4 Typical Wait Mode I MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 22 Title , with All Modules Turned On (25° 220 DD , with ADC Turned On (25° 220 ...
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... MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA Title Summary of Device Variations . . . . . . . . . . . . . . . . . . . . . . . . . 25 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Function Priority in Shared Pins . . . . . . . . . . . . . . . . . . . . . . . .32 Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Examples of Protect Start Address Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Signal Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 PIN Bit Set Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 OSC2 Pin Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 Oscillator Modes ...
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... Mode, Edge, and Level Selection . . . . . . . . . . . . . . . . . . . . . . 147 11-1 MUX Channel Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 11-2 ADC Clock Divide Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 12-1 Port A Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 12-2 Port B Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 12-3 Port B Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 16-1 LVIOUT Bit Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 20-1 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227 MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 24 Title List of Tables Page MOTOROLA ...
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... M68HC08 central processor unit (CPU08) and are available with a variety of modules, memory sizes and types, and package types. MC68HC908QT1 MC68HC908QT2 MC68HC908QT4 MC68HC908QY1 MC68HC908QY2 MC68HC908QY4 MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA Section 1. General Description Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Pin Function Priority ...
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... FLASH security On-chip in-application programmable FLASH memory (with internal program/erase voltage generation) – MC68HC908QY4 and MC68HC908QT4 — 4096 bytes – MC68HC908QY2, MC68HC908QY1, MC68HC908QT2, and MC68HC908QT1 — 1536 bytes 128 bytes of on-chip random-access memory (RAM) 2-channel, 16-bit timer interface module (TIM) 4-channel, 8-bit analog-to-digital converter (ADC) on ...
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... Power-on reset Internal pullups on IRQ and RST to reduce external components Memory mapped I/O registers Power saving stop and wait modes MC68HC908QY4, MC68HC908QY2, and MC68HC908QY1 are available in these packages: – 16-pin plastic dual in-line package (PDIP) – 16-pin small outline integrated circuit (SOIC) package – ...
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... MCU Block Diagram Figure 1-1 1.5 Pin Assignments The MC68HC908QT4, MC68HC908QT2, and MC68HC908QT1 are available in 8-pin packages and the MC68HC908QY4, MC68HC908QY2, and MC68HC908QY1 in 16-pin packages. Figure 1-2 MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 28 MC68HC908QT4, MC68HC908QT2, and MC68HC908QT1 are available in these packages: – 8-pin PDIP – ...
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... ACCUMULATOR CPU REGISTERS INDEX REGISTER STACK POINTER PROGRAM COUNTER CONDITION CODE REGISTER MC68HC908QY4 AND MC68HC908QT4: 4096 BYTES MC68HC908QY2, MC68HC908QY1, MC68HC908QT2, AND MC68HC908QT1: 1536 BYTES USER FLASH Figure 1-1. Block Diagram POWER SUPPLY V SS ...
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... PTA0/TCH0/KBI0 PTA4/OSC2/AD2/KBI4 PTA1/TCH1/KBI1 PTB2 PTB3 PTA2/IRQ/KBI2 PTA3/RST/KBI3 MC68HC908QY2 AND MC68HC908QY4 PDIP/SOIC PTA1/TCH1/KBI1 PTA0/AD0/TCH0/KBI0 PTB2 PTB3 PTA2/IRQ/KBI2 PTA3/RST/KBI3 PTB4 PTB5 PTA5/OSC1/AD3/KBI5 PTA4/OSC2/KBI4 MC68HC908QY2 AND MC68HC908QY4 TSSOP Figure 1-2. MCU Pin Assignments General Description PTA0/AD0/TCH0/KBI0 PTA1/AD1/TCH1/KBI1 4 5 PTA2/IRQ/KBI2 8-PIN ASSIGNMENT ...
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... AD3 — A/D channel 3 input KBI5 — Keyboard interrupt input 5 (1) 8 general-purpose I/O ports. PTB[0:7] 1. The PTB pins are not available on the 8-pin packages. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA provides a description of the pin functions. Table 1-2. Pin Functions Description General Description General Description ...
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... Pin Function Priority Table 1 single pin. NOTE: Upon reset all pins come up as input ports regardless of the priority table. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 32 is meant to resolve the priority if multiple functions are enabled Table 1-3. Function Priority in Shared Pins Pin Name ...
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... Input/Output (I/O) Section .35 4096 bytes of user FLASH for MC68HC908QT4 and MC68HC908QY4 1536 bytes of user FLASH for MC68HC908QT2, MC68HC908QT1, MC68HC908QY2, and MC68HC908QY1 128 bytes of random access memory (RAM) 48 bytes of user-defined vectors, located in FLASH 416 bytes of monitor read-only memory (ROM) 1536 bytes of FLASH program and erase routines, located in ...
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... INTERNAL OSCILLATOR TRIM VALUE $FFC1 RESERVED FLASH $FFC2 FLASH 14 BYTES $FFCF $FFD0 USER VECTORS 48 BYTES $FFFF MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 34 MC68HC908QY1, and MC68HC908QY2 Figure 2-1. Memory Map Memory $0100 UNIMPLEMENTED 9984 BYTES $27FF $2800 AUXILIARY ROM 1536 BYTES $2DFF $2E00 UNIMPLEMENTED ...
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... MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA Figure 2-1 and in register figures in this document, $FE00 — Break status register, BSR $FE01 — Reset status register, SRSR $FE02 — Break auxiliary register, BRKAR $FE03 — Break flag control register, BFCR $FE04 — ...
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... See page 166. Reset: Read: Port B Input Pullup Enable $000C Register (PTBPUE) Write: See page 169. Reset: Unimplemented $000D $0019 Unimplemented Figure 2-2. Control, Status, and Data Registers (Sheet MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 36 Bit AWUL PTA5 PTA4 ...
Page 37
... TIM Counter Register High $0021 (TCNTH) Write: See page 144. Reset: Read: TIM Counter Register $0022 Low (TCNTL) Write: See page 144. Reset: Figure 2-2. Control, Status, and Data Registers (Sheet MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA Bit ...
Page 38
... See page 149. Reset: Read: TIM Channel 1 $002A Register Low (TCH1L) Write: See page 149. Reset: Unimplemented $002B $0035 Unimplemented Figure 2-2. Control, Status, and Data Registers (Sheet MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 38 Bit Bit 15 Bit 14 Bit 13 Bit ...
Page 39
... Break Status Register $FE00 (BSR) Write: See page 208. Reset: Read: SIM Reset Status Register $FE01 (SRSR) Write: See page 96. POR: Figure 2-2. Control, Status, and Data Registers (Sheet MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA Bit ...
Page 40
... Register (BRKL) Write: See page 206. Reset: Read: Break Status and Control $FE0B Register (BRKSCR) Write: See page 205. Reset: Figure 2-2. Control, Status, and Data Registers (Sheet MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 40 Bit ...
Page 41
... Value (Optional) Reset: $FFC1 Reserved Unimplemented $FFC2 $FFCF Unimplemented Read: COP Control Register $FFFF (COPCTL) Write: See page 192. Reset: Figure 2-2. Control, Status, and Data Registers (Sheet MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA Bit ...
Page 42
... Memory Vector Priority MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 42 Table 2-1. Vector Addresses Vector Address $FFDE Lowest IF15 $FFDF $FFE0 IF14 $FFE1 IF13 — IF6 $FFF2 IF5 $FFF3 $FFF4 IF4 $FFF5 $FFF6 IF3 $FFF7 IF2 — $FFFA IF1 $FFFB $FFFC — $FFFD $FFFE — ...
Page 43
... The stack pointer decrements during pushes and increments during pulls. NOTE: Be careful when using nested subroutines. The CPU may overwrite data in the RAM during a subroutine or during the interrupt stacking operation. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Random-Access Memory (RAM) 43 ...
Page 44
... Random-Access Memory (RAM) MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 44 Random-Access Memory (RAM) MOTOROLA ...
Page 45
... FLASH Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . 49 FLASH Program Operation FLASH Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . . . 53 Wait Mode Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 MC68HC908QY4 and MC68HC908QT4: 4096 bytes user FLASH from $EE00–$FDFF MC68HC908QY2, MC68HC908QT2, MC68HC908QY1 and MC68HC908QT1: 1536 bytes user FLASH from $F800–$FDFF FLASH Memory (FLASH) 45 ...
Page 46
... FLASH difficult for unauthorized users. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 46 $EE00 – $FDFF; user memory, 4096 bytes: MC68HC908QY4 and MC68HC908QT4 $F800 – $FDFF; user memory, 1536 bytes: MC68HC908QY2, MC68HC908QT2, MC68HC908QY1 and MC68HC908QT1 $FFD0 – $FFFF; user interrupt vectors, 48 bytes. FLASH Memory (FLASH) (1) ...
Page 47
... PGM — Program Control Bit This read/write bit configures the memory for program operation. PGM is interlocked with the ERASE bit such that both bits cannot be equal set the same time. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA $FE08 Bit 7 ...
Page 48
... However, in applications where a FLASH location will be erased and reprogrammed less than 1000 times, and speed is important, use the 1 ms page erase specification to get a lower minimum erase time. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 48 register. the block to be erased. ...
Page 49
... FLASH memory Figure 4-2 NOTE: Only bytes which are currently $FF may be programmed. 1. When in monitor mode, with security sequence failed (see block protect register instead of any FLASH address. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA register. memory address range. (minimum 10 s). nvs (minimum 4 ms) ...
Page 50
... The time between each FLASH address change, or the time between the last FLASH address programmed to clearing PGM bit, must not exceed the maximum programming time, t maximum. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 50 operation and enables the latching of address and data for programming ...
Page 51
... The FLBPR itself can be erased or programmed only with an external voltage, V pin. This voltage also allows entry from reset into the monitor mode. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA Once the FLBPR is programmed with a value other than $FF, ...
Page 52
... PROG This row program algorithm assumes the row programmed are initially erased. Figure 4-2. FLASH Programming Flowchart MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 52 1 SET PGM BIT 2 READ THE FLASH BLOCK PROTECT REGISTER 3 ...
Page 53
... FLASH memory for block protection. The FLASH is protected from this start address to the end of FLASH memory, at $FFFF. With this mechanism, the protect start address can be XX00, XX40, XX80, or XXC0 within the FLASH memory. See FLASH BLOCK PROTECT MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA $FFBE Bit 7 6 ...
Page 54
... NOTE: Standby mode is the power-saving mode of the FLASH module in which all internal control signals to the FLASH are inactive and the current consumption of the FLASH minimum. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 54 Table 4-1. Examples of Protect Start Address BPR[7:0] Start of Address of Protect Range $00– ...
Page 55
... Functional Description The configuration registers are used in the initialization of various options. The configuration registers can be written once after each reset. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Stop mode recovery time (32 4096 BUSCLKX4 cycles) ...
Page 56
... External oscillator (1, 0) External RC oscillator (1, 1) External XTAL oscillator RSTEN — RST Pin Function Selection NOTE: The RSTEN bit is cleared by a power-on reset (POR) only. Other resets will leave this bit unaffected. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 56 Figure 5-1 and Bit ...
Page 57
... LVI to operate during stop mode. Reset clears LVISTOP. LVIRSTD — LVI Reset Disable Bit LVIRSTD disables the reset signal from the LVI module. LVIPWRD — LVI Power Disable Bit LVIPWRD disables the LVI module. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA Bit ...
Page 58
... LVI is not protecting the MCU. STOP — STOP Instruction Enable Bit STOP enables the STOP instruction. COPD — COP Disable Bit COPD disables the COP module. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 LVI operates in 5-V mode 0 = LVI operates in 3-V mode 1 = Stop mode recovery after 32 BUSCLKX4 cycles ...
Page 59
... The M68HC08 CPU (central processor unit enhanced and fully object-code-compatible version of the M68HC05 CPU. The CPU08 Reference Manual (Motorola document order number CPU08RM/AD) contains a description of the CPU instruction set, addressing modes, and architecture. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA Section 6. Central Processor Unit (CPU) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 CPU Registers ...
Page 60
... CPU Registers Figure 6-1 the memory map. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 60 Object code fully upward-compatible with M68HC05 Family 16-bit stack pointer with stack manipulation instructions 16-bit index register with x-register manipulation instructions 8-MHz CPU internal bus frequency ...
Page 61
... H is the upper byte of the index register, and X is the lower byte. H:X is the concatenated 16-bit index register. In the indexed addressing modes, the CPU uses the contents of the index register to determine the conditional address of the operand. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA 7 15 ...
Page 62
... NOTE: The location of the stack is arbitrary and may be relocated anywhere in RAM. Moving the SP out of page 0 ($0000 to $00FF) frees direct address (page 0) space. For correct operation, the stack pointer must point only to RAM locations. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 62 Bit 14 13 ...
Page 63
... The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. Bits 6 and 5 are set permanently to logic 1. The following paragraphs describe the functions of the condition code register. Read: Write: Reset: MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA Bit ...
Page 64
... A return-from-interrupt (RTI) instruction pulls the CPU registers from the stack and restores the interrupt mask from the stack. After any reset, the interrupt mask is set and can be cleared only by the clear interrupt mask software instruction (CLI). MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 Overflow overflow ...
Page 65
... CPU08RM/AD) for a description of the instructions and addressing modes and more detail about the architecture of the CPU. 6.6 Low-Power Modes The WAIT and STOP instructions put the MCU in low power-consumption standby modes. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA 1 = Negative result 0 = Non-negative result 1 = Zero result ...
Page 66
... A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation if the break interrupt has been deasserted. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 66 Clears the interrupt mask (I bit) in the condition code register, enabling interrupts. After exit from wait mode by interrupt, the I bit remains clear ...
Page 67
... BCC rel Branch if Carry Bit Clear BCLR n, opr Clear Bit BCS rel Branch if Carry Bit Set (Same as BLO) BEQ rel Branch if Equal MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA provides a summary of the M68HC08 instruction set. Description A (A) + (M) + (C) A (A) + (M) « ...
Page 68
... Branch if Interrupt Mask Set BNE rel Branch if Not Equal BPL rel Branch if Plus BRA rel Branch Always BRCLR n,opr,rel Branch if Bit Clear BRN rel Branch Never MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 68 Description (PC rel ? ( (PC rel ? ( ...
Page 69
... CMP opr,SP CMP opr,SP COM opr COMA COMX Complement (One’s Complement) COM opr,X COM ,X COM opr,SP CPHX #opr Compare H:X with M CPHX opr MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA Description PC (PC rel ? (Mn (PC push (PCL) SP (SP) – 1; push (PCH) SP (SP) – ...
Page 70
... JSR opr,X JSR ,X LDA #opr LDA opr LDA opr LDA opr,X Load A from M LDA opr,X LDA ,X LDA opr,SP LDA opr,SP MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 70 Description (X) – (M) (A) U – – (A) – (M) – (X) – 1 ...
Page 71
... ORA opr,SP ORA opr,SP PSHA Push A onto Stack PSHH Push H onto Stack PSHX Push X onto Stack PULA Pull A from Stack PULH Pull H from Stack PULX Pull X from Stack MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA Description H ...
Page 72
... STX opr,X Store STX ,X STX opr,SP STX opr,SP SUB #opr SUB opr SUB opr SUB opr,X Subtract SUB opr,X SUB ,X SUB opr,SP SUB opr,SP MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 72 Description $FF SP (SP Pull (CCR) SP (SP ...
Page 73
... Indexed, 8-bit offset, post increment addressing mode IX2 Indexed, 16-bit offset addressing mode M Memory location N Negative bit 6.9 Opcode Map The opcode map is provided in MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA Description PC (PC Push (PCL) SP (SP) – 1; Push (PCH) SP (SP) – 1; Push (X) SP (SP) – ...
Page 74
Bit Manipulation Branch Read-Modify-Write DIR DIR REL DIR INH INH MSB LSB BRSET0 BSET0 BRA NEG NEGA NEGX 3 DIR 2 DIR 2 REL 2 DIR 1 INH ...
Page 75
... MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 RST and IRQ Pins Initialization . . . . . . . . . . . . . . . . . . . . . . . .79 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . . 79 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 Clock Start-Up from POR . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . . 80 Reset and System Initialization External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Active Resets from Internal Sources . . . . . . . . . . . . . . . . . . 81 Power-On Reset ...
Page 76
... Figure 7-2 state controller that coordinates CPU and exception timing. The SIM is responsible for: • • • • • MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 76 Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . . 93 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 SIM Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Break Flag Control Register ...
Page 77
... Address bus Internal address bus Data bus Internal data bus PORRST Signal from the power-on reset module to the SIM IRST Internal reset signal R/W Read/write signal MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA SIM COUNTER 2 CLOCK GENERATORS MASTER RESET CONTROL RESET Figure 7-1. SIM Block Diagram Table 7-1 ...
Page 78
... Read: Interrupt Status $FE05 Register 2 (INT2) Write: See page 91. Reset: Read: Interrupt Status $FE06 Register 3 (INT3) Write: See page 92. Reset: Figure 7-2. SIM I/O Register Summary MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 78 Bit Writing a logic 0 clears SBSW. ...
Page 79
... CPU and peripherals are inactive and held in an inactive phase until after the 4096 BUSCLKX4 cycle POR time out has completed. The RST pin is driven low by the SIM during this entire period. The IBUS clocks start upon completion of the time out. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA Section 5. Configuration Register FROM ...
Page 80
... The RST pin circuits include an internal pullup device. Pulling the asynchronous RST pin low halts all processing. The PIN bit of the SIM reset status register (SRSR) is set as long as RST is held low for a MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 80 Power-on reset module (POR) ...
Page 81
... The internal reset signal IRST continues to be asserted for an additional 32 cycles (see Figure opcode, COP time out, LVI, or POR (see IRST BUSCLKX4 ADDRESS MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA Table 7-2 Table 7-2. PIN Bit Set Timing Reset Type Number of Cycles Required to Set PIN POR ...
Page 82
... At power on, the following events occur: • • • • • • See MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 82 ILLEGAL ADDRESS RST ILLEGAL OPCODE RST COPRST POR LVI Figure 7-6. Sources of Internal Reset A POR pulse is generated. The internal reset signal is asserted. ...
Page 83
... The COP module is disabled during a break interrupt with monitor mode when BDCOP bit is set in break auxiliary register (BRKAR). MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA 32 32 ...
Page 84
... CPU and memories are released from reset to allow the reset vector sequence to occur. The SIM actively pulls down the (RST) pin for all internal reset sources. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 84 . The LVI bit in the SIM reset status register (SRSR) ...
Page 85
... External reset has no effect on the SIM counter (see for details.) The SIM counter is free-running after all reset states. See 7.5.2 Active Resets from Internal Sources internal reset recovery sequences. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA System Integration Module (SIM) System Integration Module (SIM) SIM Counter 7 ...
Page 86
... At the end of an interrupt, the RTI instruction recovers the CPU register contents from the stack so that normal processing can resume. Figure 7-10 MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 86 a. Maskable hardware CPU interrupts b. Non-maskable software interrupt instruction (SWI) Figure 7-8 Figure 7-9 shows interrupt recovery timing ...
Page 87
... YES (AS MANY INTERRUPTS AS EXIST ON CHIP) MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA FROM RESET YES BREAK INTERRUPT? I BIT SET BIT SET? NO YES IRQ INTERRUPT? NO YES TIMER INTERRUPT? NO LOAD PC WITH INTERRUPT VECTOR FETCH NEXT INSTRUCTION SWI YES INSTRUCTION? NO RTI YES INSTRUCTION? NO Figure 7-8 ...
Page 88
... If an interrupt is pending upon exit from the original interrupt service routine, the pending interrupt is serviced before the LDA instruction is executed. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 88 SP – – – ...
Page 89
... The SWI instruction is a non-maskable instruction that causes an interrupt regardless of the state of the interrupt mask (I bit) in the condition code register. NOTE: A software interrupt pushes PC onto the stack. A software interrupt does not push PC – hardware interrupt does. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA CLI LDA #$FF INT1 ...
Page 90
... Priority Highest Lowest 1. The I bit in the condition code register is a global mask for all interrupt sources except the SWI instruction. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 90 Table 7-3 summarizes the interrupt sources and the interrupt Table 7-3. Interrupt Sources Source ...
Page 91
... Interrupt Status Register 2 Address: $FE05 Read: Write: Reset — Interrupt Flags F This flag indicates the presence of interrupt requests from the sources shown in Bit 0–6 — Always read 0 MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA Bit IF5 IF4 ...
Page 92
... Section 17. Break Module break state by forcing it to the SWI vector location. Refer to the break interrupt subsection of each module to see how each module is affected by the break state. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 92 Bit ...
Page 93
... Wait Mode In wait mode, the CPU clocks are inactive while the peripheral clocks continue to run. ADDRESS BUS DATA BUS MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA Figure 7-15 shows the timing for wait mode entry. WAIT ADDR WAIT ADDR + 1 ...
Page 94
... Figure 7-16 ADDRESS BUS DATA BUS EXITSTOPWAIT NOTE: EXITSTOPWAIT = ADDRESS BUS DATA BUS BUSCLKX4 MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 94 and Figure 7-17 show the timing for wait recovery. $6E0B $6E0C $A6 $A6 $A6 ...
Page 95
... Figure 7-19 NOTE: To minimize stop current, all pins configured as inputs should be driven to a logic 1 or logic 0. ADDRESS BUS DATA BUS MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA Figure 7-18 shows the stop mode recovery time from interrupt or break CPUSTOP STOP ADDR STOP ADDR + 1 ...
Page 96
... Clear the SIM reset status register by reading it. A power-on reset sets the POR bit and clears all other bits in the register. Address: $FE01 Read: Write: POR: MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 96 STOP RECOVERY PERIOD STOP + 2 STOP + 2 STOP +1 Table 7-4. SIM Registers ...
Page 97
... ILOP — Illegal Opcode Reset Bit ILAD — Illegal Address Reset Bit (opcode fetches only) MODRST — Monitor Mode Entry Module Reset bit LVI — Low Voltage Inhibit Reset bit MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA 1 = Last reset caused by POR circuit 0 = Read of SRSR ...
Page 98
... BCFE — Break Clear Flag Enable Bit This read/write bit enables software to clear status bits by accessing status registers while the MCU break state. To clear status bits during the break state, the BCFE bit must be set. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 98 Bit 7 6 ...
Page 99
... Clear SBSW by writing a logic 0 to it. Reset clears SBSW. SBSW can be read within the break state SWI routine. The user can modify the return address on the stack by subtracting one from it. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA Bit 7 6 ...
Page 100
... System Integration Module (SIM) MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 100 System Integration Module (SIM) MOTOROLA ...
Page 101
... MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA Section 8. Oscillator Module (OSC) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Internal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Internal Oscillator Trimming . . . . . . . . . . . . . . . . . . . . . . 103 Internal to External Clock Switching 104 External Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 XTAL Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Oscillator Module Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 Crystal Amplifier Input Pin (OSC1) ...
Page 102
... Functional Description The oscillator contains these major subsystems: • • • • • MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 102 trimmable to . This is the default option out of reset. into OSC1. requires an external R connection only. The capacitor is internal to the chip. requires an external crystal or ceramic-resonator. ...
Page 103
... FLASH to the OSCTRIM register right at the beginning of assembly code. Reset loads OSCTRIM with a default value of $80. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA shows how BUSCLKX4 is derived from INTCLK and, like the Section 12 ...
Page 104
... No post-switch clock monitor feature is implemented (clock does not switch back to internal if external clock dies). MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 104 precharge an external crystal oscillator, set PTA4 (OSC2 output and drive high for several cycles. This may help the crystal circuit start more robustly ...
Page 105
... NOTE: The series resistor (R oscillator guidelines and may not be required for all ranges of operation, especially with high frequency crystals. Refer to the crystal manufacturer’s data for more information. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA Crystal Fixed capacitor Tuning capacitor, C ...
Page 106
... R In this configuration, the OSC2 pin can be left in the reset state as PTA4. Or, the OSC2EN bit in the port A pullup enable register can be set to enable the OSC2 function on the pin without affecting the clocks. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 106 BUSCLKX4 XTALCLK ...
Page 107
... Crystal Amplifier Input Pin (OSC1) The OSC1 pin is either an input to the crystal oscillator amplifier, an input to the RC oscillator circuit external clock source. For the internal oscillator configuration, the OSC1 pin can assume other functions according to MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA INTCLK SIMOSCEN EXTERNAL RC ...
Page 108
... OSC2 and may not represent the actual circuitry. The duty cycle of XTALCLK is unknown and may depend on the crystal and other external factors. Also, the frequency and amplitude of XTALCLK can be unstable at start up. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 108 Table 1-3. Function Priority in Pins, or the output of the oscillator clock (BUSCLKX4). ...
Page 109
... SIM and results in the internal bus frequency being one fourth of either the XTALCLK, RCCLK, or INTCLK frequency. 8.6 Low Power Modes The WAIT and STOP instructions put the MCU in low-power consumption standby modes. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA Oscillator Module (OSC) Oscillator Module (OSC) Low Power Modes Figure 8-2 8 ...
Page 110
... OSCOPT1 and OSCOPT0. All CONFIG2 register bits will have a default configuration. Refer to (CONFIG) Table 8-2 clock source. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 110 Section 5. Configuration Register for more information on how the CONFIG2 register is used. shows how the OSCOPT bits are used to select the oscillator Table 8-2 ...
Page 111
... This bit is ignored in monitor mode with the internal oscillator bypassed, PTM or CTM mode. ECGST — External Clock Status Bit This read-only bit indicates whether or not an external clock source is engaged to drive the system clock. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA $0036 Bit 7 6 ...
Page 112
... TRIM = $80). The trimmed frequency is guaranteed not to vary by more than ±5% over the full specified range of temperature and voltage. The reset value is $80, which sets the frequency to 12.8 MHz (3.2 MHz bus speed) ±25%. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 112 Bit 7 6 ...
Page 113
... Monitor mode entry can be achieved without use of the higher test voltage, V $FFFF are blank, thus reducing the hardware requirements for in-circuit programming. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA Section 9. Monitor ROM (MON) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Functional Description ...
Page 114
... All communication between the host computer and the MCU is through 1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or copying the FLASH difficult for unauthorized users. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 114 Normal user-mode pin functionality on most pins ...
Page 115
... MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA shows the pin conditions for entering monitor mode $FFFE and $FFFF does not contain $FF (programmed state): – The external clock is 9.8304 MHz – ...
Page 116
... C1– C2 V– 5 C2– DB9 Figure 9-2. Monitor Mode Circuit (Internal Clock, No High Voltage) MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 116 V DD 9.8304 MHz CLOCK + 74HC125 5 6 74HC125 ...
Page 117
... Forced $FF V monitor X DD (blank) mode Forced $FF V monitor X SS (blank) mode V Not DD User or X $FF mode V (programmed) SS MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA * 10 k 0.1 F 9.8304 MHz CLOCK TST + 9 74HC125 5 6 74HC125 External ...
Page 118
... Once out of reset, the MCU waits for the host to send eight security bytes (see signal (10 consecutive logic 0s) to the host, indicating that it is ready to receive a command. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 118 , to IRQ must be used to enter monitor mode. If monitor mode was entered as a result of the reset vector being blank (above condition set 2 or 3), the COP is always disabled regardless of the state of IRQ ...
Page 119
... PTA0 which will operate as serial communication port. Refer to Figure Regardless of the state of the IRQ pin, it will not function as a port input pin in monitor mode. Bit 2 of the Port A data register will always read 0. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA POR RESET IS VECTOR ...
Page 120
... Bit 2 of the Port A data register will always read 0. The BIH and BIL instructions will behave as if the IRQ pin is enabled, regardless of the settings in the configuration registers. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 120 (CONFIG). summarizes the differences between user mode and monitor Table 9-2 ...
Page 121
... Other standard baud rates can be accomplished using proportionally higher or lower frequency generators crystal is used as the source, be aware of the upper frequency limit that the MCU can operate. External Frequency MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA BIT 0 BIT 1 BIT 2 ...
Page 122
... ECHO Notes Echo delay, 2 bit times 2 = Cancel command delay, 11 bit times 3 = Wait 1 bit time before sending next byte. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 122 READ (read memory) WRITE (write memory) IREAD (indexed read) IWRITE (indexed write) READSP (read stack pointer) ...
Page 123
... A brief description of each monitor mode command is given in Table 9-4 Description Returned ECHO MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA through Table 9-9. Table 9-4. READ (Read Memory) Command Read byte from memory Operand 2-byte address in high-byte:low-byte order Data Returns contents of specified address Opcode $4A Command Sequence ...
Page 124
... Monitor ROM (MON) Description ECHO Description MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 124 Table 9-5. WRITE (Write Memory) Command Write byte to memory 2-byte address in high-byte:low-byte order; low byte followed by Operand data byte Data None Returned Opcode $49 Command Sequence FROM HOST ADDRESS ADDRESS ...
Page 125
... Description Returned A sequence of IREAD or IWRITE commands can access a block of memory sequentially over the full 64-Kbyte memory map. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA Table 9-7. IWRITE (Indexed Write) Command Write to last address accessed + 1 Operand Single data byte Data None Opcode $19 Command Sequence ...
Page 126
... Monitor ROM (MON) Description Description MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 126 Table 9-8. READSP (Read Stack Pointer) Command Reads stack pointer Operand None Data Returns incremented stack pointer value ( Returned high-byte:low-byte order Opcode $0C Command Sequence FROM HOST READSP READSP ECHO Table 9-9 ...
Page 127
... FLASH locations and execute code from FLASH. Security remains bypassed until a power-on reset occurs. If the reset was not a power-on reset, security remains bypassed and security code entry is not required. See MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA HIGH BYTE OF INDEX REGISTER CONDITION CODE REGISTER ...
Page 128
... FLASH module can also be mass erased by executing an erase routine that was downloaded into internal RAM. The mass erase operation clears the security code locations so that all eight security bytes become $FF (blank). MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 128 4096 + 32 CGMXCLK CYCLES FROM HOST ...
Page 129
... TIM Status and Control Register . . . . . . . . . . . . . . . . . . . . 141 10.10.2 TIM Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 10.10.3 TIM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . . 144 10.10.4 TIM Channel Status and Control Registers . . . . . . . . . . . . 145 10.10.5 TIM Channel Registers .148 MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA Section 10. Timer Interface Module (TIM) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Pin Name Conventions ...
Page 130
... The TIM shares two input/output (I/O) pins with two port A I/O pins. The full names of the TIM I/O pins are listed in name appear in the text that follows. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 130 Two input capture/output compare channels – Rising-edge, falling-edge, or any-edge input capture trigger – ...
Page 131
... COUNTER 16-BIT COMPARATOR TMODH:TMODL CHANNEL 0 16-BIT COMPARATOR TCH0H:TCH0L 16-BIT LATCH CHANNEL 1 16-BIT COMPARATOR TCH1H:TCH1L 16-BIT LATCH MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA shows the structure of the TIM. The central component of PRESCALER SELECT PS2 PS1 PS0 ELS0B ELS0A CH0F MS0A ...
Page 132
... See page 149. TIM Channel 0 Register Low $0027 (TCH0L) See page 149. TIM Channel 1 Status and Control Register $0028 (TSC1) See page 145. Figure 10-2. TIM I/O Register Summary MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 132 Bit Read: TOF TOIE TSTOP Write: 0 Reset: ...
Page 133
... When the counter reaches the value in the registers of an output compare channel, the TIM can set, clear, or toggle the channel pin. Output compares can generate TIM CPU interrupt requests. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA Bit 7 6 ...
Page 134
... Use the following methods to synchronize unbuffered changes in the output compare value on channel x: • • MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 134 10.5.3 Output When changing to a smaller value, enable channel x output compare interrupts and write the new value in the output compare interrupt routine ...
Page 135
... TIM to clear the channel pin on output compare if the state of the PWM pulse is logic 1. Program the TIM to set the pin if the state of the PWM pulse is logic 0. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA shows, the output compare value in the TIM channel Timer Interface Module (TIM) ...
Page 136
... PWM period. Also, using a TIM overflow interrupt routine to write a new, smaller pulse width value may cause the compare to be missed. The TIM may pass the new value before it is written. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 136 OVERFLOW OVERFLOW ...
Page 137
... PWM function, and TIM channel 1 status and control register (TSC1) is unused. While the MS0B bit is set, the channel 1 pin, TCH1, is available as a general-purpose I/O pin. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA When changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine ...
Page 138
... PWM signal generation when changing the PWM pulse width to a new, much larger value the TIM status control register (TSC), clear the TIM stop bit, MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 138 a. Stop the TIM counter by setting the TIM stop bit, TSTOP. ...
Page 139
... The TIM remains active after the execution of a WAIT instruction. In wait mode the TIM registers are not accessible by the CPU. Any enabled CPU interrupt request from the TIM can bring the MCU out of wait mode. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA Registers. ...
Page 140
... PTA0/TCH0 and PTA1/TCH1. Each channel I/O pin is programmable independently as an input capture pin or an output compare pin. PTA0/TCH0 can be configured as a buffered output compare or buffered PWM pin. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 140 7.9.2 Break Flag Control Register. Timer Interface Module (TIM) ...
Page 141
... Address: $0020 Read: Write: Reset: MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA TIM status and control register (TSC) TIM control registers (TCNTH:TCNTL) TIM counter modulo registers (TMODH:TMODL) TIM channel status and control registers (TSC0 and TSC1) TIM channel registers (TCH0H:TCH0L and TCH1H:TCH1L) ...
Page 142
... TRST bit. NOTE: Setting the TSTOP and TRST bits simultaneously stops the TIM counter at a value of $0000. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 142 1 = TIM counter has reached modulo value 0 = TIM counter has not reached modulo value 1 = TIM overflow interrupts enabled ...
Page 143
... TIM counter registers. NOTE: If you read TCNTH during a break interrupt, be sure to unlatch TCNTL by reading TCNTL before exiting the break interrupt. Otherwise, TCNTL retains the value latched during the break. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA Table 10-2 Table 10-2. Prescaler Selection PS1 ...
Page 144
... Read: Write: Reset: Address: $0024 Read: Write: Reset: Figure 10-6. TIM Counter Modulo Registers (TMODH:TMODL) NOTE: Reset the TIM counter before writing to the TIM counter modulo registers. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 144 $0021 TCNTH Bit Bit 15 Bit 14 Bit 13 ...
Page 145
... When channel output compare channel, CHxF is set when the value in the TIM counter registers matches the value in the TIM channel x registers. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA Flags input captures and output compares ...
Page 146
... NOTE: Before changing a channel function by writing to the MSxB or MSxA bit, set the TSTOP and TRST bits in the TIM status and control register (TSC). MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 146 1 = Input capture or output compare on channel input capture or output compare on channel x ...
Page 147
... After initially enabling a TIM channel register for input capture operation and selecting the edge sensitivity, clear CHxF to ignore any erroneous edge detection flags. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA shows how ELSxB and ELSxA work. Reset clears the Table 10-3. Mode, Edge, and Level Selection ...
Page 148
... The state of the TIM channel registers after reset is unknown. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 148 1 = Channel x pin toggles on TIM counter overflow Channel x pin does not toggle on TIM counter overflow. ...
Page 149
... Address: $0026 Read: Write: Reset: Address: $0027 Read: Write: Reset: Address: $0029 Read: Write: Reset: Address: $02A Read: Write: Reset: MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA TCH0H Bit Bit 15 Bit 14 Bit 13 Bit 12 Indeterminate after reset TCH0L Bit Bit 7 ...
Page 150
... Timer Interface Module (TIM) MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 150 Timer Interface Module (TIM) MOTOROLA ...
Page 151
... Introduction This section describes the analog-to-digital converter (ADC). The ADC is an 8-bit, 4-channel analog-to-digital converter. The ADC module is only available on the MC68HC908QY2, MC68HC908QT2, MC68HC908QY4, and MC68HC908QT4. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 ADC Port I/O Pins ...
Page 152
... Four ADC channels are available for sampling external sources at pins PTA0, PTA1, PTA4, and PTA5. An analog multiplexer allows the single ADC converter to select one of the four ADC channels as an ADC MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 152 4 channels with multiplexed input ...
Page 153
... READ DDRA WRITE DDRA WRITE PTA READ PTA CONVERSION COMPLETE INTERRUPT LOGIC AIEN COCO BUS CLOCK MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA shows a block diagram of the ADC. DDRAx RESET PTAx ADC DATA REGISTER ADC VOLTAGE IN ADCVIN ADC ADC CLOCK CLOCK ...
Page 154
... MHz, then one conversion will take complete. With a 1-MHz ADC internal clock the maximum sample rate is 62.5 kHz. Number of Bus Cycles = Conversion Time MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 154 and $00 if less than ADC Clock Cycles ...
Page 155
... If the ADC is not required to bring the MCU out of wait mode, power down the ADC by setting the CH[4:0] bits in ADSCR to logic 1’s before executing the WAIT instruction. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA Analog-to-Digital Converter (ADC) Analog-to-Digital Converter (ADC) ...
Page 156
... ADC channels to the ADC module. 11.8 Input/Output Registers These I/O registers control and monitor ADC operation: • • • MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 156 ADC status and control register (ADSCR) ADC data register (ADR) ADC clock register (ADICLK) Analog-to-Digital Converter (ADC) ...
Page 157
... ADCO — ADC Continuous Conversion Bit When set, the ADC will convert samples continuously and update ADR at the end of each conversion. Only one conversion is allowed when this bit is cleared. Reset clears the ADCO bit. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA Bit 7 6 ...
Page 158
... If any unused channels are selected, the resulting ADC conversion will be unknown. 2. The voltage levels supplied from internal reference nodes, as specified in the table, are used to verify the operation of the ADC converter both in production test and for user applications. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 158 Table 11-1 ...
Page 159
... ADIV2, ADIV1, and ADIV0 form a 3-bit field which selects the divide ratio used by the ADC to generate the internal ADC clock. shows the available clock configurations. The ADC clock should be set to approximately 1 MHz. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA Bit ...
Page 160
... Analog-to-Digital Converter (ADC) ADIV2 X = don’t care MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 160 Table 11-2. ADC Clock Divide Ratio ADIV1 ADIV0 Analog-to-Digital Converter (ADC) ADC Clock Rate Bus clock ÷ 1 Bus clock ÷ 2 Bus clock ÷ ...
Page 161
... Introduction The MC68HC908QT1, MC68HC908QT2, and MC68HC908QT4 have five bidirectional input-output (I/O) pins and one input only pin. The MC68HC908QY1, MC68HC908QY2, and MC68HC908QY4 have thirteen bidirectional pins and one input only pin. All I/O pins are programmable as inputs or outputs. NOTE: Connect any unused I/O pins to an appropriate logic level, either V V ...
Page 162
... PTA2 is input only. When the IRQ function is enabled in the configuration register 2 (CONFIG2), bit 2 of the port A data register (PTA) will always read a logic 0. In this case, the BIH and BIL instructions can be used to read the MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 162 Bit 7 6 ...
Page 163
... KBI[5:0] — Port A Keyboard Interrupts The keyboard interrupt enable bits, KBIE5–KBIE0, in the keyboard interrupt control enable register (KBIER) enable the port A pins as external interrupt pins (see (KBI)). MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA Bit ...
Page 164
... These read/write bits control port A data direction. Reset clears DDRA[5:0], configuring all port A pins as inputs. NOTE: Avoid glitches on port A pins by writing to the port A data register before changing data direction register A bits from MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 164 Bit ...
Page 165
... When DDRAx is a logic 0, reading address $0000 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA shows the port A I/O logic. READ DDRA ($0004) ...
Page 166
... RC oscillator option is selected. This bit has no effect for the XTAL or external oscillator options. PTAPUE[5:0] — Port A Input Pullup Enable Bits These read/write bits are software programmable to enable pullup devices on port A pins. Table 12-1 MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 166 Bit ...
Page 167
... Hi-Z = high impedance 5. Output does not apply to PTA2 12.4 Port B Port 8-bit general purpose I/O port. Port B is only available on the MC68HC908QY1, MC68HC908QY2, and MC68HC908QY4. 12.4.1 Port B Data Register The port B data register (PTB) contains a data latch for each of the eight port B pins. Address: $0001 ...
Page 168
... These read/write bits control port B data direction. Reset clears DDRB[7:0], configuring all port B pins as inputs. NOTE: Avoid glitches on port B pins by writing to the port B data register before changing data direction register B bits from the port B I/O logic. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 168 Bit ...
Page 169
... DDRBx, be configured as input. Each pullup device is automatically and dynamically disabled when its corresponding DDRBx bit is configured as output. Address: Read: Write: Reset: Figure 12-9. Port B Input Pullup Enable Register (PTBPUE) MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA Table 12-2 Table 12-2. Port B Pin Functions Accesses to DDRB PTB I/O Pin Bit ...
Page 170
... I/O pin pulled internal pullup Writing affects data register, but does not affect input. 4. Hi-Z = high impedance MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 170 1 = Corresponding port B pin configured to have internal pull if its DDRB bit is set Pullup device is disconnected on the corresponding port B pin regardless of the state of its DDRB bit ...
Page 171
... Features Features of the IRQ module include the following: • • • • • • MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA Section 13. External Interrupt (IRQ) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 IRQ Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . . 175 IRQ Status and Control Register ...
Page 172
... INTERNAL PULLUP DEVICE IRQ Figure 13-1. IRQ Module Block Diagram MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 172 Vector fetch — A vector fetch automatically generates an interrupt acknowledge signal that clears the IRQ latch. Software clear — Software can clear the interrupt latch by writing to the acknowledge bit in the interrupt status and control register (ISCR) ...
Page 173
... IRQ Status and Control Register $001D Write: (INTSCR) See page 176. Reset: Figure 13-2. IRQ I/O Register Summary MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA Vector fetch or software clear Return of the interrupt pin to logic 1 7.7 Exception Control. provides a summary of the IRQ I/O register. Bit ...
Page 174
... When the IRQ function is enabled in the CONFIG2 register, the BIH and BIL instructions can be used to read the logic level on the IRQ pin. If the IRQ function is disabled, these instructions will behave as if the IRQ pin MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 174 Vector fetch or software clear — A vector fetch generates an interrupt acknowledge signal to clear the latch ...
Page 175
... IRQ module, see (CONFIG). The ISCR has the following functions: • • • • MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA is connected to the IRQ pin; this can DD Section 7. System Integration Module (SIM). Section 5. Configuration Register Shows the state of the IRQ flag ...
Page 176
... Writing a logic 1 to this read/write bit disables IRQ interrupt requests. Reset clears IMASK1. MODE1 — IRQ Edge/Level Select Bit This read/write bit controls the triggering sensitivity of the IRQ pin. Reset clears MODE1. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 176 Bit ...
Page 177
... The keyboard interrupt module (KBI) provides six independently maskable external interrupts, which are accessible via the PTA0–PTA5 pins, plus one internal maskable interrupt controlled by the auto wake-up logic. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Keyboard Initialization ...
Page 178
... Register (KBIER) Write: See page 184. Reset: Figure 14-1. KBI I/O Register Summary MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 178 Six keyboard interrupt pins with separate keyboard interrupt enable bits and one keyboard interrupt mask One internal interrupt controlled by the auto wake-up logic, with ...
Page 179
... Writing the AWUIE bit in the keyboard interrupt enable register enables or disables the auto wake-up interrupt input (see applied to the AWUIREQ input with auto wake-up interrupt request enabled, latches a keyboard interrupt request. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA V DD CLR ...
Page 180
... MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 180 If the keyboard interrupt is edge-sensitive only, a falling edge on a keyboard interrupt input does not latch an interrupt request if another keyboard pin is already low. To prevent losing an interrupt request on one input because another input is still low, software can disable the latter input while it is low ...
Page 181
... When a keyboard interrupt pin is enabled, it takes time for the internal pullup to reach a logic 1. Therefore a false interrupt can occur as soon as the pin is enabled. This does not apply to an auto wake-up interrupt, which is internally generated without pullup. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA Keyboard Interrupt Module (KBI) Keyboard Interrupt Module (KBI) ...
Page 182
... Keyboard Status and Control Register The keyboard status and control register (KBSCR): • • • • MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 182 keyboard status and control register. keyboard interrupt enable register. to clear any false interrupts. DDRA bits in the data direction register A. ...
Page 183
... A or auto wake-up. Reset clears the IMASKK bit. MODEK — Keyboard Triggering Sensitivity Bit This read/write bit controls the triggering sensitivity of the keyboard interrupt pins on port A and auto wake-up. Reset clears MODEK. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA Bit ...
Page 184
... A to latch interrupt requests. Reset clears the keyboard interrupt enable register. AWUIE — Auto Wake-up Interrupt Enable Bit This read/write bit enables the auto wake-up interrupt input to latch interrupt requests. Reset clears AWUIE. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 184 Bit ...
Page 185
... Once the overflow count is reached in the generator counter, a wake-up request, AWUIREQ, is latched and sent to the KBI logic (see Wake-up interrupt requests will only be serviced if the associated interrupt enable bit, AWUIE, in KBIER is set. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA AUTOWUGEN DIV 2 ...
Page 186
... Stop Mode The keyboard module remains active in stop mode. Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of stop mode. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 186 COPRS = 0: 512 ms COPRS = Figure 14-2) has no effect on AWUL reading ...
Page 187
... With BCFE at logic 0 (its default state), writing to the keyboard acknowledge bit (ACKK) in the keyboard status and control register during the break state has no effect. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA Keyboard Module During Break Interrupts Keyboard Interrupt Module (KBI) ...
Page 188
... Keyboard Interrupt Module (KBI) MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 188 Keyboard Interrupt Module (KBI) MOTOROLA ...
Page 189
... The COP module helps software recover from runaway code. Prevent a COP reset by clearing the COP counter periodically. The COP module can be disabled through the COPD bit in the configuration 1 (CONFIG1) register. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 I/O Signals ...
Page 190
... BUSCLKX4 cycle overflow option, a 8-MHz crystal gives a COP timeout period of 32.766 ms. Writing any value to location $FFFF before an overflow occurs prevents a COP reset by clearing the COP counter and stages 12–5 of the SIM counter. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 190 SIM MODULE 12-BIT SIM COUNTER ...
Page 191
... SIM counter. Reading the COP control register returns the low byte of the reset vector. 15.4.3 Power-On Reset The power-on reset (POR) circuit in the SIM clears the SIM counter 4096 MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA Register. Register) clears the COP counter and clears bits 12–5 of the BUSCLKX4 cycles after power up. ...
Page 192
... Writing any value to $FFFF clears the COP counter and starts a new timeout period. Reading location $FFFF returns the low byte of the reset vector. Address: $FFFF Read: Write: Reset: MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 192 (CONFIG). (CONFIG). Bit ...
Page 193
... COP timeout period after entering or exiting stop mode. 15.9 COP Module During Break Mode The COP is disabled during a break interrupt with monitor mode when BDCOP bit is set in break auxiliary register (BRKAR). MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA Computer Operating Properly (COP) Computer Operating Properly (COP) Interrupts ...
Page 194
... Computer Operating Properly (COP) MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 194 Computer Operating Properly (COP) MOTOROLA ...
Page 195
... Introduction This section describes the low-voltage inhibit (LVI) module, which monitors the voltage on the V voltage falls below the LVI trip falling voltage, V MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA Section 16. Low-Voltage Inhibit (LVI) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 Polled LVI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Forced Reset Operation ...
Page 196
... Clearing the LVI power disable bit, LVIPWRD, enables the LVI to monitor V reset disable bit, LVIRSTD, enables the LVI module to generate a reset when V MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 196 Programmable LVI reset Programmable power consumption Selectable LVI trip voltage Programmable stop mode operation shows the structure of the LVI module ...
Page 197
... V register, the LVIPWRD bit must be at logic 0 to enable the LVI module, and the LVIRSTD bit must be at logic 1 to disable LVI resets. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA , to be configured for 5-V operation. Clearing the LVI5OR3 bit ...
Page 198
... NOTE: The microcontroller is guaranteed to operate at a minimum supply voltage. The trip point (V this. See 18.9 3-V DC Electrical Characteristics MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 198 to remain above the V DD level. In the configuration register, the LVIPWRD TRIPF . This prevents a condition in which the MCU is TRIPR ...
Page 199
... LVIOUT — LVI Output Bit This read-only flag becomes set when the that prevents oscillation into and out of reset (see clears the LVIOUT bit. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 MOTOROLA level while LVI resets have been disabled TRIPF Bit 7 6 ...
Page 200
... When the LVIPWRD bit in the configuration register is cleared and the LVISTOP bit in the configuration register is set, the LVI module remains active in stop mode. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out of stop mode. MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1 200 Low-Voltage Inhibit (LVI) MOTOROLA ...