MC74HC595 ON Semiconductor, MC74HC595 Datasheet
MC74HC595
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MC74HC595 Summary of contents
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Serial−Input/Serial or Parallel−Output Shift Register with Latched 3−State Outputs High−Performance Silicon−Gate CMOS The 74HC595 consists of an 8−bit shift register and an 8−bit D−type latch with three−state parallel outputs. The shift register accepts serial data and provides a ...
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PIN ASSIGNMENT OUTPUT ENABLE LATCH CLOCK SHIFT CLOCK ...
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... Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. †Derating — SOIC Package: – 7 mW/_C from 65_ to 125_C TSSOP Package: − 6.1 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D). RECOMMENDED OPERATING CONDITIONS Symbol Parameter ...
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... Maximum Three−State OZ Leakage Current, Q − Maximum Quiescent Supply CC Current (per Package) NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D). (Voltages Referenced to GND (V) Test Conditions – 0.1 V 2.0 out ...
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... NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D). C Power Dissipation Capacitance (Per Package Used to determine the no−load dynamic power consumption Semiconductor High−Speed CMOS Data Book (DL129/D pF, Input 6.0 ns) L ...
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TIMING REQUIREMENTS (Input Symbol Parameter t Minimum Setup Time, Serial Data Input A to Shift Clock su (Figure 5) t Minimum Setup Time, Shift Clock to Latch Clock su (Figure 6) t Minimum Hold Time, ...
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Serial Input A Reset Operation Reset shift register L X Shift data into shift H D register Shift register remains H X unchanged Transfer shift register H X contents to latch register Latch register remains X X unchanged Enable parallel ...
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SHIFT 90% 50% CLOCK 10 1/f max t t PLH PHL 90% OUTPUT 50 TLH THL Figure 1. LATCH 50% CLOCK t t PLH PHL 90% Q −Q A ...
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OUTPUT 13 ENABLE LATCH 12 CLOCK SERIAL 14 DATA INPUT A SHIFT 11 CLOCK 10 RESET EXPANDED LOGIC DIAGRAM ...
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SHIFT CLOCK SERIAL DATA INPUT A RESET LATCH CLOCK OUTPUT ENABLE SERIAL DATA OUTPUT SQ H NOTE: implies that the output ...
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... G K −T− SEATING PLANE 0.25 (0.010 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. PACKAGE DIMENSIONS SOIC−16 CASE 751B−05 ISSUE K −B− 0.25 (0.010 ...
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... −V− C 0.10 (0.004) −T− SEATING D PLANE 16X 0.36 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. PACKAGE DIMENSIONS TSSOP−16 CASE 948F−01 ISSUE Ç ...
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... Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303− ...