MC74LCX373 Motorola, MC74LCX373 Datasheet

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MC74LCX373

Manufacturer Part Number
MC74LCX373
Description
LOW-VOLTAGE CMOS OCTAL TRANSPARENT LATCH
Manufacturer
Motorola
Datasheet

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Low-Voltage CMOS Octal
Transparent Latch
With 5V-Tolerant Inputs and Outputs
(3-State, Non-Inverting)
transparent latch operating from a 2.7 to 3.6V supply. High impedance
TTL compatible inputs significantly reduce current loading to input drivers
while TTL compatible outputs offer improved switching noise
performance. A V I specification of 5.5V allows MC74LCX373 inputs to be
safely driven from 5V devices.
When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters
the latches. In this condition, the latches are transparent, i.e., a latch
output will change state each time its D input changes. When LE is LOW,
the latches store the information that was present on the D inputs a setup
time preceding the HIGH–to–LOW transition of LE. The 3–state standard
outputs are controlled by the Output Enable (OE) input. When OE is
LOW, the standard outputs are enabled. When OE is HIGH, the standard
outputs are in the high impedance state, but this does not interfere with
new data entering into the latches.
11/96
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Motorola, Inc. 1996
Designed for 2.7 to 3.6V V CC Operation
5V Tolerant — Interface Capability With 5V TTL Logic
Supports Live Insertion and Withdrawal
I OFF Specification Guarantees High Impedance When V CC = 0V
LVTTL Compatible
LVCMOS Compatible
24mA Balanced Output Sink and Source Capability
Near Zero Static Supply Current in All Three Logic States (10 A)
Substantially Reduces System Power Requirements
Latchup Performance Exceeds 500mA
ESD Performance: Human Body Model >2000V; Machine Model >200V
The MC74LCX373 is a high performance, non–inverting octal
The MC74LCX373 contains 8 D–type latches with 3–state outputs.
V CC
OE
20
1
O7
O0
19
2
D7
D0
18
3
Pinout: 20–Lead (Top View)
D6
D1
17
4
O6
O1
16
5
O5
O2
15
6
1
D5
D2
14
7
D4
13
D3
8
O4
O3
12
9
www.DataSheet4U.com
GND
LE
11
10
PIN NAMES
Pins
OE
LE
D0–D7
O0–O7
REV 4
20
20
20
20
TRANSPARENT LATCH
MC74LCX373
1
1
1
LOW–VOLTAGE
1
Function
Output Enable Input
Latch Enable Input
Data Inputs
3–State Latch Outputs
CMOS OCTAL
PLASTIC SOIC EIAJ
PLASTIC TSSOP
PLASTIC SSOP
CASE 751D–04
CASE 940C–03
PLASTIC SOIC
CASE 948E–02
CASE 967–01
DW SUFFIX
SD SUFFIX
DT SUFFIX
M SUFFIX

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MC74LCX373 Summary of contents

Page 1

... High impedance TTL compatible inputs significantly reduce current loading to input drivers while TTL compatible outputs offer improved switching noise performance specification of 5.5V allows MC74LCX373 inputs to be safely driven from 5V devices. The MC74LCX373 contains 8 D–type latches with 3–state outputs. ...

Page 2

... MC74LCX373 INPUTS High Voltage Level High Voltage Level One Setup Time Prior to the Latch Enable High–to–Low Transition Low Voltage Level Low Voltage Level One Setup Time Prior to the Latch Enable High–to–Low Transition; ...

Page 3

... V CC 3.6V –100 2.7V –12mA 3.0V –18mA 3.0V –24mA 2. 3.6V 100 2.7V 12mA 3.0V 16mA 3.0V 24mA 3 MC74LCX373 Condition Unit V V Output in 3–State V Note < GND < GND > ...

Page 4

... MC74LCX373 DC ELECTRICAL CHARACTERISTICS Symbol Characteristic I I Input Leakage Current I OZ 3–State Output Current I OFF Power–Off Leakage Current I CC Quiescent Supply Current I CC Increase per Input AC CHARACTERISTICS ( 2.5ns 50pF 500 ) Symbol Parameter t PLH Propagation Delay t PHL ...

Page 5

... WAVEFORM 3 – PROPAGATION DELAYS, LE MINIMUM PULSE WIDTH SETUP AND HOLD TIMES 2.5ns, 10 1MHz 500ns except when noted Figure 1. AC Waveforms V CC DUT TEST Figure 2. Test Circuit 5 MC74LCX373 2. PHL 2.7V 1. ...

Page 6

... MC74LCX373 –A – –B – 0.010 (0.25 SEATING G K PLANE 0.13 (0.005) 0.10 (0.004) M MOTOROLA OUTLINE DIMENSIONS DW SUFFIX PLASTIC SOIC PACKAGE CASE 751D–04 ISSUE 0.010 (0.25 –T M – ...

Page 7

... DETAIL E H DETAIL E 7 MC74LCX373 NOTES: 13 DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 14 CONTROLLING DIMENSION: MILLIMETER. 15 DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 16 DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION ...

Page 8

... JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–81–3521–8315 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 8 MC74LCX373/D LCX DATA BR1339 — REV 3 ...

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