MC74LVX259 ON Semiconductor, MC74LVX259 Datasheet

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MC74LVX259

Manufacturer Part Number
MC74LVX259
Description
8-Bit Addressable Latch/1-of-8 Decoder CMOS Logic Level Shifter
Manufacturer
ON Semiconductor
Datasheet
www.DataSheet4U.com
DataSheet U .com
4
with LSTTL–Compatible Inputs
silicon gate CMOS technology.
output which provides high noise immunity and stable output.
digital systems. The device has four modes of operation as shown in
the mode selection table.. In the addressable latch mode, the data on
Data In is written into the addressed latch. The addressed latch follows
the data input with all non–addressed latches remaining in their
previous states. In the memory mode, all latches remain in their
previous state and are unaffected by the Data or Address inputs. In the
one–of–eight decoding or demultiplexing mode, the addressed output
follows the state of Data In with all other outputs in the LOW state. In
the Reset mode, all outputs are LOW and unaffected by the address
and data inputs. When operating the LVX259 as an addressable latch,
changing more than one bit of the address could impose a transient
wrong address. Therefore, this should only be done while in the
memory mode.
voltages up to 7 V are applied, regardless of the supply voltage. This
allows the MC74LVX259 to be used to interface 5 V circuits to 3 V
circuits.
April, 2001 – Rev. 1
The MC74LVX259 is an 8–bit Addressable Latch fabricated with
The internal circuit is composed of three stages, including a buffer
The LVX259 is designed for general purpose storage applications in
The MC74LVX259 input structure provides protection when
CMOS–Compatible Outputs: V
High Speed: t
Low Power Dissipation: I
High Noise Immunity: V
Power Down Protection Provided on Inputs and Outputs
Balanced Propagation Delays
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300 mA
ESD Performance: HBM > 2000 V; Machine Model > 200 V
Semiconductor Components Industries, LLC, 2001
PD
= 7.0 ns (Typ) at V
NIH
CC
= 2 A (Max) at T
= V
OH
> 0.8 V
NIL
CC
= 28% V
= 3.3 V
CC
; V
OL
CC
A
< 0.1 V
= 25 C
CC
1
@Load
MC74LVX259D
MC74LVX259DR2
MC74LVX259DT
MC74LVX259DTR2
MC74LVX259M
MC74LVX259MEL
SOIC EIAJ–16
Device
CASE 751B
CASE 948F
DT SUFFIX
TSSOP–16
M SUFFIX
CASE 966
D SUFFIX
SOIC–16
ORDERING INFORMATION
A
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
http://onsemi.com
= Assembly Location
SO EIAJ–16
SO EIAJ–16 2000 Units/Reel
TSSOP–16
TSSOP–16 2000 Units/Reel
Package
MARKING DIAGRAMS
SO–16
SO–16
Publication Order Number:
16
16
1
1
AWLYWW
AWLYYWW
LVX259
LVX259
ALYW
MC74LVX259/D
2500 Units/Reel
LVX
259
48 Units/Rail
96 Units/Rail
48 Units/Rail
Shipping
9
8
8
9

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MC74LVX259 Summary of contents

Page 1

... Therefore, this should only be done while in the memory mode. The MC74LVX259 input structure provides protection when voltages are applied, regardless of the supply voltage. This allows the MC74LVX259 to be used to interface 5 V circuits circuits. High Speed 7.0 ns (Typ ...

Page 2

... GND 8 Figure 1. Pin Assignment MODE SELECTION TABLE Enable Reset DataSheet U .com MC74LVX259 RESET ADDRESS A1 INPUTS 14 ENABLE A2 13 DATA IN DATA RESET 9 Q4 ENABLE ...

Page 3

... DATA INPUT A0 ADDRESS A1 INPUTS A2 14 ENABLE 15 RESET 4 DataSheet U .com MC74LVX259 DECODER Figure 4. Expanded Logic Diagram http://onsemi.com ...

Page 4

... DC Output Voltage OUT T Operating Temperature Range, all Package Types Input Rise or Fall Time DataSheet U .com MC74LVX259 Parameter and GND Pins CC Human Body Model (Note 2.) Machine Model (Note 3.) Charged Device Model (Note 4.) Above V and Below GND at 125 C (Note 5.) CC Characteristics V CC http://onsemi ...

Page 5

... C Power Dissipation Capacitance (Note 6 defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. PD Average operating current can be obtained by the equation: I power consumption DataSheet U .com MC74LVX259 V CC Condition (V) 2.0 0.75 V 3.0 0.7 V 3.6 0.7 V 2.0 3.0 3 ...

Page 6

... ADDRESS 50% SELECT t su ENABLE Figure 9. Switching Waveform 4 DataSheet U .com MC74LVX259 Input 3 Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Test Conditions Î ...

Page 7

... and K are determined by component size. The clearance between the components and the cavity must be within 0.05 mm min 0.50 mm max. The component cannot rotate more than 10 within the determined cavity 4 DataSheet U .com MC74LVX259 TOP COVER TAPE SEE NOTE ...

Page 8

... Metric Dimensions Govern–English are in parentheses for reference only and K are determined by component size. The clearance between the components and the cavity must be within 0.05 mm min 0.50 mm max. The component cannot rotate more than 10 within the determined cavity 4 DataSheet U .com MC74LVX259 1.0 mm 1.75 mm 3.5 mm 2.4 mm 4.0 mm Min 0 ...

Page 9

... REEL DIMENSIONS Tape Size DataSheet U .com MC74LVX259 1.5 mm MIN (0.06”) 20.2 mm MIN A (0.795”) FULL RADIUS Figure 12. Reel Dimensions T&R Suffix A Max T1, T2 178 mm (7”) T3, T4 330 mm (13”) R2 330 mm (13”) R2 360 mm (14.173”) R2 360 mm (14.173” ...

Page 10

... TOP TAPE TAPE TAPE UTILIZATION BY PACKAGE Tape Size DataSheet U .com MC74LVX259 TAPE TRAILER (Connected to Reel Hub) COMPONENTS NO COMPONENTS 160 mm MIN DIRECTION OF FEED Figure 14. Tape Ends for Finished Goods User Direction of Feed Figure 15. TSSOP and SOIC R2 Reel Configuration/Orientation ...

Page 11

... G –T– L PIN 1 IDENT. C –T– DataSheet U .com MC74LVX259 PACKAGE DIMENSIONS SOIC–16 D SUFFIX CASE 751B–05 ISSUE J –B– TSSOP–16 DT SUFFIX CASE 948F–01 ISSUE O K 16X REF – ...

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