MC9S08GB60A Freescale Semiconductor, Inc, MC9S08GB60A Datasheet

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MC9S08GB60A

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MC9S08GB60A
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Freescale Semiconductor, Inc
Datasheet

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MC9S08GB60A
MC9S08GB32A
MC9S08GT60A
MC9S08GT32A
Data Sheet
HCS08
Microcontrollers
MC9S08GB60A
Rev. 1.02
02/2008
freescale.com

Related parts for MC9S08GB60A

MC9S08GB60A Summary of contents

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... MC9S08GB60A MC9S08GB32A MC9S08GT60A MC9S08GT32A Data Sheet HCS08 Microcontrollers MC9S08GB60A Rev. 1.02 02/2008 freescale.com ...

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... MC9S08GB60A Data Sheet Covers: MC9S08GB60A MC9S08GB32A MC9S08GT60A MC9S08GT32A MC9S08GB60A Rev. 1.02 02/2008 ...

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... Section 5.7 Real Time Interrupt. Changed the Maximun Low Power of FBE and FEE in Changed the Title of Table 13-2 from “IIC1A Register Field Descriptions” to “IIC1F Register Field Descriptions” ® technology licensed from SST. MC9S08GB60A Data Sheet, Rev. 1.02 Table A MHz. Freescale Semiconductor ...

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... Chapter 14 Analog-to-Digital Converter (S08ATDV3 221 Chapter 15 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 Appendix A Electrical Characteristics 259 Appendix B EB652: Migrating from the GB60 Series to the GB60A Series281 Appendix C Ordering Information and Mechanical Drawings 285 Freescale Semiconductor List of Chapters Title MC9S08GB60A Data Sheet, Rev. 1.02 Page 5 ...

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... Stop Modes ......................................................................................................................................34 3.6.1 Stop1 Mode ......................................................................................................................35 3.6.2 Stop2 Mode ......................................................................................................................35 3.6.3 Stop3 Mode ......................................................................................................................36 3.6.4 Active BDM Enabled in Stop Mode ................................................................................37 3.6.5 LVD Enabled in Stop Mode .............................................................................................37 3.6.6 On-Chip Peripheral Modules in Stop Modes ...................................................................37 Freescale Semiconductor Contents Title Chapter 1 Device Overview Chapter 2 Pins and Connections Chapter 3 Modes of Operation MC9S08GB60A Data Sheet, Rev. 1.02 Page 7 ...

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... LVD Reset Operation .......................................................................................................69 5.6.3 LVD Interrupt Operation .................................................................................................69 5.6.4 Low-Voltage Warning (LVW) .........................................................................................69 5.7 Real-Time Interrupt (RTI) ...............................................................................................................69 5.8 Reset, Interrupt, and System Control Registers and Control Bits ...................................................70 5.8.1 Interrupt Pin Request Status and Control Register (IRQSC) ...........................................71 8 Title Chapter 4 Memory Chapter 5 MC9S08GB60A Data Sheet, Rev. 1.02 Page Freescale Semiconductor ...

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... Port G Registers (PTGD, PTGPE, PTGSE, and PTGDD) ...............................................98 Internal Clock Generator (S08ICGV2) 7.1 Introduction ...................................................................................................................................103 7.1.1 Features ..........................................................................................................................104 7.1.2 Modes of Operation .......................................................................................................105 7.2 Oscillator Pins ...............................................................................................................................105 7.2.1 EXTAL— External Reference Clock / Oscillator Input ................................................105 7.2.2 XTAL— Oscillator Output ............................................................................................105 Freescale Semiconductor Title Chapter 6 Parallel Input/Output Chapter 7 MC9S08GB60A Data Sheet, Rev. 1.02 Page 9 ...

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... ICG Trim Register (ICGTRM) ......................................................................................126 Central Processor Unit (S08CPUV2) 8.1 Introduction ...................................................................................................................................127 8.1.1 Features ..........................................................................................................................127 8.2 Programmer’s Model and CPU Registers .....................................................................................128 8.2.1 Accumulator (A) ............................................................................................................128 8.2.2 Index Register (H:X) .....................................................................................................128 8.2.3 Stack Pointer (SP) ..........................................................................................................129 8.2.4 Program Counter (PC) ...................................................................................................129 8.2.5 Condition Code Register (CCR) ....................................................................................129 10 Title Chapter 8 MC9S08GB60A Data Sheet, Rev. 1.02 Page Freescale Semiconductor ...

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... KBI Interrupt Controls ...................................................................................................152 10.1 Introduction ...................................................................................................................................153 10.2 Features .........................................................................................................................................153 10.3 TPM Block Diagram .....................................................................................................................155 10.4 Pin Descriptions ............................................................................................................................156 10.4.1 External TPM Clock Sources ........................................................................................156 10.4.2 TPMxCHn — TPMx Channel n I/O Pins ......................................................................156 10.5 Functional Description ..................................................................................................................156 Freescale Semiconductor Title Chapter 9 Keyboard Interrupt (S08KBIV1) Chapter 10 Timer/PWM (S08TPMV1) MC9S08GB60A Data Sheet, Rev. 1.02 Page 11 ...

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... Receiver Functional Description ...................................................................................182 11.3.3.1 Data Sampling Technique .............................................................................183 11.3.3.2 Receiver Wakeup Operation .........................................................................183 11.3.4 Interrupts and Status Flags .............................................................................................184 11.3.5 Additional SCI Functions ..............................................................................................185 11.3.5.1 8- and 9-Bit Data Modes ...............................................................................185 11.3.5.2 Stop Mode Operation ....................................................................................185 11.3.5.3 Loop Mode ....................................................................................................186 12 Title Chapter 11 MC9S08GB60A Data Sheet, Rev. 1.02 Page Freescale Semiconductor ...

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... SCL — Serial Clock Line ..............................................................................................206 13.2.2 SDA — Serial Data Line ...............................................................................................206 13.3 Register Definition ........................................................................................................................206 13.3.1 IIC Address Register (IIC1A) ........................................................................................207 13.3.2 IIC Frequency Divider Register (IIC1F) .......................................................................207 13.3.3 IIC Control Register (IIC1C) .........................................................................................210 Freescale Semiconductor Title Chapter 12 Chapter 13 MC9S08GB60A Data Sheet, Rev. 1.02 Page 13 ...

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... Resets ............................................................................................................................................231 14.5 Interrupts .......................................................................................................................................231 14.6 ATD Registers and Control Bits ....................................................................................................231 14.6.1 ATD Control (ATDC) ....................................................................................................232 14.6.2 ATD Status and Control (ATD1SC) ..............................................................................234 14.6.3 ATD Result Data (ATD1RH, ATD1RL) ........................................................................235 14 Title Chapter REFH REFL ....................................................................... 225 , V DDAD SSAD ........................................................................... 225 MC9S08GB60A Data Sheet, Rev. 1.02 Page Freescale Semiconductor ...

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... Debug Trigger Register (DBGT) ..................................................................257 15.4.3.9 Debug Status Register (DBGS) ....................................................................258 A.1 Introduction ...................................................................................................................................259 A.2 Absolute Maximum Ratings ..........................................................................................................259 A.3 Thermal Characteristics .................................................................................................................260 A.4 Electrostatic Discharge (ESD) Protection Characteristics ............................................................261 A.5 DC Characteristics .........................................................................................................................261 Freescale Semiconductor Title Chapter 15 Development Support Appendix A Electrical Characteristics MC9S08GB60A Data Sheet, Rev. 1.02 Page 15 ...

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... B.5 Internal Clock Generator: Low-Power Oscillator Maximum Frequency ......................................282 B.6 Internal Clock Generator: Loss-of-Clock Disable Option ............................................................282 B.7 System Device Identification Register ..........................................................................................283 Ordering Information and Mechanical Drawings C.1 Ordering Information ....................................................................................................................285 C.2 Mechanical Drawings ....................................................................................................................285 16 Title Appendix B Appendix C MC9S08GB60A Data Sheet, Rev. 1.02 Page Freescale Semiconductor ...

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... Optional computer operating properly (COP) reset — Low-voltage detection with reset or interrupt — Illegal opcode detection with reset — Illegal address detection with reset (some devices don’t have illegal addresses) Freescale Semiconductor Chapter 15, “Development MC9S08GB60A Data Sheet, Rev. 1.02 Support”) 17 ...

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... general-purpose input/output (I/O) pins, depending on package selection • 64-pin low-profile quad flat package (LQFP) — MC9S08GBxxA • 48-pin quad flat package, no lead (QFN) — MC9S08GTxxA • 44-pin quad flat package (QFP) — MC9S08GTxxA 18 Table 1-1 for device specific information) MC9S08GB60A Data Sheet, Rev. 1.02 Freescale Semiconductor ...

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... RAM TPM 4K One 3-channel and one 5-channel, 16-bit timer 2K One 3-channel and one 5-channel, 16-bit timer 4K Two 2-channel, 16-bit timers 2K Two 2-channel, 16-bit timers MC9S08GB60A Data Sheet, Rev. 1.02 Chapter 1 Device Overview I/O Packages 56 64 LQFP 56 64 LQFP QFN 36 44 QFP (1) 39 ...

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... SERIAL PERIPHERAL INTERFACE MODULE (SPI1) SERIAL COMMUNICATIONS INTERFACE MODULE (SCI1) Table 2-2 Block Diagaram Symbol Key: = Not connected in 48- and 44-pin packages = Not connected in 44-pin packages MC9S08GB60A Data Sheet, Rev. 1. PTA7/KBI1P7– PTA0/KBI1P0 8 8 PTB7/AD1P7– PTB0/AD1P0 PTC7 PTC6 PTC5 ...

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... Analog-to-Digital Converter (ATD) Internal Clock Generator (ICG) Inter-Integrated Circuit (IIC) Keyboard Interrupt (KBI) Serial Peripheral Interface (SPI) Timer Pulse-Width Modulator (TPM) Central Processing Unit (CPU) TPM1 TPM2 RTI BUSCLK BDC MC9S08GB60A Data Sheet, Rev. 1.02 Chapter 1 Device Overview Version IIC1 ...

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... Otherwise the fixed-frequency clock will be BUSCLK. • ICGLCLK — Development tools can select this internal self-clocked source (~ 8 MHz) to speed up BDC communications in systems where the bus clock is slow. • ICGERCLK — External reference clock can be selected as the real-time interrupt clock source. 22 MC9S08GB60A Data Sheet, Rev. 1.02 Freescale Semiconductor ...

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... Chapter 2 Pins and Connections 2.1 Introduction This section describes signals that connect to package pins. It includes a pinout diagram, a table of signal properties, and detailed discussion of signals. Freescale Semiconductor MC9S08GB60A Data Sheet, Rev. 1.02 23 ...

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... PTF3 12 PTF4 13 PTE0/TxD1 14 PTE1/RxD1 15 IRQ Figure 2-1. MC9S08GBxxA in 64-Pin LQFP Package MC9S08GB60A Data Sheet, Rev. 1. PTA2/KBI1P2 47 PTA1/KBI1P1 46 PTA0/KBI1P0 45 PTF7 44 PTF6 43 PTF5 42 V REFL 41 V REFH 40 PTB7/AD1P7 39 PTB6/AD1P6 38 PTB5/AD1P5 37 PTB4/AD1P4 ...

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... PTC0/TxD2 3 PTC1/RxD2 4 PTC2/SDA1 5 PTC3/SCL1 6 PTC4 7 PTC5 8 PTC6 PTC7 9 10 PTE0/TxD1 11 PTE1/RxD1 12 IRQ Figure 2-2. MC9S08GTxxA in 48-Pin QFN Package Freescale Semiconductor MC9S08GB60A Data Sheet, Rev. 1.02 Chapter 2 Pins and Connections 36 PTA1/KBI1P1 35 PTA0/KBI1P0 34 V REFL 33 V REFH 32 PTB7/AD1P7 31 PTB6/AD1P6 30 PTB5/AD1P5 29 PTB4/AD1P4 28 PTB3/AD1P3 27 PTB2/AD1P2 PTB1/AD1P1 ...

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... MC9S08GBxxA application systems. MC9S08GTxxA connections will be similar except for the number of I/O pins available. A more detailed discussion of system connections follows MC9S08GB60A Data Sheet, Rev. 1.02 33 PTA1/KBI1P1 32 PTA0/KBI1P0 31 V REFL 30 V REFH 29 PTB7/AD1P7 ...

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... PTG3 PORT PTG4 G PTG5 PTG6 PTG7 PTF0 PTF1 PTF2 PTF3 PORT PTF4 F PTF5 PTF6 PTF7 Figure 2-4. Basic System Connections MC9S08GB60A Data Sheet, Rev. 1.02 Chapter 2 Pins and Connections PTA0/KBI1P0 PTA1/KBI1P1 PTA2/KBI1P2 PTA3/KBI1P3 PORT PTA4/KBI1P4 A PTA5/KBI1P5 PTA6/KBI1P6 PTA7/KBI1P7 PTB0/AD1P0 PTB1/AD1P1 PTB2/AD1P2 PTB3/AD1P3 PORT B ...

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... Internal power-on reset and low-voltage reset circuitry typically make external reset circuitry unnecessary. This pin is normally connected to the standard 6-pin background 28 Chapter 7, “Internal Clock Generator (when used) and R S MC9S08GB60A Data Sheet, Rev. 1.02 ), that is Self_reset (S08ICGV2).” should be low-inductance F ...

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... To prevent extra current drain from floating input pins, the reset initialization routine in the application program should either enable on-chip pullup devices or change the direction of unused pins to outputs so the pins do not float. Freescale Semiconductor , released, and sampled again approximately 38 Self_reset NOTE MC9S08GB60A Data Sheet, Rev. 1.02 Chapter 2 Pins and Connections Figure 2-4 for 29 ...

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... Chapter 12, “Serial Peripheral Interface (S08SPIV3)” Chapter 11, “Serial Communications Interface (S08SCIV1)” Chapter 6, “Parallel Input/Output” Chapter 6, “Parallel Input/Output” Chapter 7, “Internal Clock Generator (S08ICGV2)” Chapter 15, “Development Support” Chapter 6, “Parallel MC9S08GB60A Data Sheet, Rev. 1.02 Chapter 6, “Parallel 1 Reference Input/Output” for details. Freescale Semiconductor ...

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... SWC When pin is configured for SCI function, pin is configured for partial output drive. SWC SWC SWC SWC SWC SWC SWC SWC SWC SWC SWC SWC MC9S08GB60A Data Sheet, Rev. 1.02 Chapter 2 Pins and Connections Comments pins — IRQ should SS1 31 ...

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... SWC SWC Not available on 44-pin pkg SWC SWC Not available on 44-, or 48-pin pkg SWC SWC Not available on 44-, or 48-pin pkg SWC SWC Not available on 44-, or 48-pin pkg SWC SWC Not available on 44-, or 48-pin pkg MC9S08GB60A Data Sheet, Rev. 1.02 Comments Freescale Semiconductor ...

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... Active background mode is entered in any of five ways: • When the BKGD/MS pin is low at the rising edge of reset • When a BACKGROUND command is received through the BKGD pin • When a BGND instruction is executed • When encountering a BDC breakpoint Freescale Semiconductor MC9S08GB60A Data Sheet, Rev. 1.02 33 ...

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... One of three stop modes is entered upon execution of a STOP instruction when the STOPE bit in the system option register is set. In all stop modes, all internal clocks are halted. If the STOPE bit is not set 34 MC9S08GB60A Data Sheet, Rev. 1.02 Chapter 15, “Development Support. Freescale Semiconductor ...

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... Freescale Semiconductor Table 3-1. Stop Mode Behavior RAM ICG ATD Off Off Disabled Standby Off Disabled 2 Standby Off Disabled MC9S08GB60A Data Sheet, Rev. 1.02 Chapter 3 Modes of Operation Regulator I/O Pins RTI 1 Off Reset Off Standby States held Optionally on Standby States held Optionally on > V rising (V ...

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... When RTIS2:RTIS1:RTIS0 = 0:0:0, the real-time interrupt function and this 1-kHz source are disabled. Power consumption is lower when the 1-kHz source is disabled, but in that case the real-time interrupt cannot wake the MCU from stop. 36 MC9S08GB60A Data Sheet, Rev. 1.02 Freescale Semiconductor ...

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... Support,” section of this data sheet. If ENBDM RAM ICG Standby Active Disabled Table 3-3. LVD Enabled Stop Mode Behavior RAM ICG Standby Standby Disabled MC9S08GB60A Data Sheet, Rev. 1.02 Chapter 3 Modes of Operation ATD Regulator I/O Pins 2 Active States held Optionally on ATD Regulator I/O Pins 1 Active ...

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... SPI — When the MCU enters stop mode, the clocks to the SPI module stop. The module halts operation. If the MCU is configured to go into stop2 or stop1 mode, the SPI module will be reset upon wake-up from stop and must be reinitialized. 38 Section 3.6.3, “Stop3 Mode,” for specific information on MC9S08GB60A Data Sheet, Rev. 1.02 Section 3.6.1, “Stop1 . No conversion Freescale Semiconductor ...

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... If the MCU is configured to go into stop2 or stop1 mode, the IIC module will be reset upon wake-up from stop and must be reinitialized. Voltage Regulator — The voltage regulator enters a low-power standby state when the MCU enters any of the stop modes unless the LVD is enabled in stop mode or BDM is enabled. Freescale Semiconductor MC9S08GB60A Data Sheet, Rev. 1.02 Chapter 3 Modes of Operation 39 ...

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... Chapter 3 Modes of Operation 40 MC9S08GB60A Data Sheet, Rev. 1.02 Freescale Semiconductor ...

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... Freescale Semiconductor 0x0000 DIRECT PAGE REGISTERS 0x007F 0x0080 RAM 0x107F 0x1080 0x17FF 0x1800 HIGH PAGE REGISTERS 0x182B 0x182C 0xFFFF MC9S08GB32A/MC9S08GT32A MC9S08GB60A Data Sheet, Rev. 1.02 0x0000 0x007F 0x0080 RAM 2048 BYTES 0x087F 0x0880 UNIMPLEMENTED 3968 BYTES 0x17FF 0x1800 0x182B 0x182C UNIMPLEMENTED 26580 BYTES ...

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... TPM2 Channel 3 TPM2 Channel 2 TPM2 Channel 1 TPM2 Channel 0 TPM1 Overflow TPM1 Channel 2 TPM1 Channel 1 TPM1 Channel 0 ICG Low Voltage Detect IRQ SWI Reset MC9S08GB60A Data Sheet, Rev. 1.02 Chapter 5, “Resets, Vector Name Vrti Viic1 Vatd1 Vkeyboard1 Vsci2tx Vsci2rx Vsci2err Vsci1tx Vsci1rx Vsci1err ...

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... Freescale Semiconductor can use the more efficient direct addressing mode which only and Table 4-4 the whole address in column one is shown in bold. In 4-4, the register names in column two are shown in bold to set them apart MC9S08GB60A Data Sheet, Rev. 1.02 Chapter 4 Memory Table 4 summary of all 43 ...

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... SBR12 SBR6 SBR5 SBR4 SCISWAI RSRC M TCIE RIE ILIE TC RDRF IDLE TXDIR MC9S08GB60A Data Sheet, Rev. 1. PTAD3 PTAD2 PTAD1 PTAD0 PTAPE2 PTAPE1 PTAPE0 PTASE2 PTASE1 PTASE0 PTADD2 PTADD1 PTADD0 PTBD3 PTBD2 PTBD1 PTBD0 PTBPE2 PTBPE1 PTBPE0 ...

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... PTGD4 PTGPE6 PTGPE5 PTGPE4 PTGSE6 PTGSE5 PTGSE4 PTGDD6 PTGDD5 PTGDD4 RANGE REFS CLKS MFD CLKST REFST LOLS MC9S08GB60A Data Sheet, Rev. 1.02 Chapter 4 Memory CPOL CPHA SSOE BIDIROE 0 SPISWAI 0 SPR2 SPR1 ...

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... CH3IE MS3B MS3A CH4IE MS4B MS4A — — — — — — MC9S08GB60A Data Sheet, Rev. 1. PRS ATDCH ATDPE3 ATDPE2 ATDPE1 ATDPE0 — — — — — — ICR TXAK RSTA ...

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... FPDIS FPS2 FPS1 FCCF FPVIOL FACCERR FCMD6 FCMD5 FCMD4 — — — — — — Table 4-4, are located in the flash memory. These registers include MC9S08GB60A Data Sheet, Rev. 1.02 Chapter 4 Memory ICG LVD BKGDPE — — — — ...

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... Comparison Key — — — — — — FPDIS FPS2 FPS1 — — — FNORED 0 0 ;point one past RAM ;SP<-(H:X-1) MC9S08GB60A Data Sheet, Rev. 1. — — — — — — FPS0 0 0 — — — SEC01 Section 4.5, “ ...

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... Features Features of the flash memory include: • Flash Size — MC9S08GB60A/MC9S08GT60A — 61268 bytes (120 pages of 512 bytes each) — MC9S08GB32A/MC9S08GT32A— 32768 bytes (64 pages of 512 bytes each) • Single power supply program and erase • Command interface for fast program and erase operation • ...

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... The command sequence must be completed by clearing FCBEF to launch the command. burst programming. The FCDIV register must be initialized before using any flash commands. This must be done only once following a reset. 50 NOTE Figure 4 flowchart for executing all of the commands except for MC9S08GB60A Data Sheet, Rev. 1.02 Freescale Semiconductor ...

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... TO BUFFER ADDRESS AND DATA WRITE COMMAND TO FCMD WRITE 1 TO FCBEF (2) Wait at least four bus cycles before TO LAUNCH COMMAND checking FCBEF or FCCF. (2) AND CLEAR FCBEF YES FPVIO OR FACCERR ? NO 0 FCCF ? 1 DONE MC9S08GB60A Data Sheet, Rev. 1.02 Chapter 4 Memory (1) Only required once after reset. ERROR EXIT 51 ...

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... Wait at least four bus cycles before TO LAUNCH COMMAND checking FCBEF or FCCF. (2) AND CLEAR FCBEF YES FPVIO OR FACCERR ? NO NEW BURST COMMAND ? NO 0 FCCF ? 1 DONE Figure 4-3. Flash Burst Program Flowchart MC9S08GB60A Data Sheet, Rev. 1.02 Only required once after reset. ERROR EXIT Freescale Semiconductor ...

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... One use for block protection is to block protect an area of flash memory for a bootloader program. This bootloader program then can be used to erase the rest of the flash memory and reprogram it. Because the bootloader is protected, it remains intact even if MCU power is lost in the middle of an erase and reprogram operation. Freescale Semiconductor MC9S08GB60A Data Sheet, Rev. 1.02 Chapter 4 Memory NVPROT)”). 53 ...

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... Writing 1 to KEYACC in the FCNFG register. This makes the flash module interpret writes to the backdoor comparison key locations (NVBACKKEY through NVBACKKEY+7) as values to be compared against the key rather than as the first step in a flash program or erase command. 54 MC9S08GB60A Data Sheet, Rev. 1.02 Freescale Semiconductor ...

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... Bit 7 of this register is a read-only status flag. Bits 6 through 0 may be read at any time but can be written only one time. Before any erase or programming operations are possible, write to this register to set the frequency of the clock for the nonvolatile memory system within acceptable limits. Freescale Semiconductor Table 4-3 MC9S08GB60A Data Sheet, Rev. 1.02 Chapter 4 Memory and Table 4-4 for the absolute ...

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... FCLK (Decimal) 12 192.3 kHz 49 200 kHz 39 200 kHz 19 200 kHz 9 200 kHz 4 200 kHz 0 200 kHz 0 150 kHz MC9S08GB60A Data Sheet, Rev. 1. DIV2 DIV1 DIV0 0 0 Eqn. 4-1 Eqn. 4-2 (5 μs Min, 6.7 μs Max) 5.2 μs 5 μs 5 μs 5 μs 5 μs 5 μs 5 μs 6.7 μs ...

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... SEC0[1:0] changes to 10 after successful backdoor key entry or a successful blank check of flash. Freescale Semiconductor Figure 4-5. Flash Options Register (FOPT) Table 4-8. FOPT Field Descriptions Description Section 4.5, MC9S08GB60A Data Sheet, Rev. 1.02 Chapter 4 Memory SEC01 SEC00 “Security.” 57 ...

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... Any flash location, not otherwise block protected or secured, may be erased or programmed KEYACC Table 4-9. FCNFG Field Descriptions Description Section 4. FPS2 FPS1 FPS0 (1) (1) (1) Table 4-10. FPROT Field Descriptions Description MC9S08GB60A Data Sheet, Rev. 1. “Security.” Freescale Semiconductor ...

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... MC9S08GB60A Data Sheet, Rev. 1.02 Chapter 4 Memory 1,2 Redirected Vectors 0xFDC0–0xFDFD 0xFBC0–0xFBFD 0xF7C0–0xF7FD 0xEFC0–0xEFFD 0xDFC0–0xDFFD 3 0xBFC0–0xBFFD 4 0x7FC0– ...

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... After a blank check command is completed and FCCF = 1, FBLANK = 1 indicates the flash array is completely erased (all 0xFF FPVIOL FACCERR Figure 4-8. Flash Status Register (FSTAT) Table 4-12. FSTAT Field Descriptions Description MC9S08GB60A Data Sheet, Rev. 1. FBLANK Section 4.4.5, “Access Errors.” FACCERR Freescale Semiconductor ...

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... FCMD4 FCMD3 Table 4-13. FCMD Field Descriptions Description Table 4-14. Flash Commands FCMD Equate File Label 0x05 mBlank 0x20 mByteProg 0x25 mBurstProg 0x40 mPageErase 0x41 mMassErase MC9S08GB60A Data Sheet, Rev. 1.02 Chapter 4 Memory Table 4-14. Refer FCMD2 FCMD1 FCMD0 ...

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... Chapter 4 Memory 62 MC9S08GB60A Data Sheet, Rev. 1.02 Freescale Semiconductor ...

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... SP is forced to 0x00FF at reset. The MC9S08GBxxA/GTxxA has seven sources for reset: • Power-on reset (POR) • Low-voltage detect (LVD) • Computer operating properly (COP) timer Freescale Semiconductor MC9S08GB60A Data Sheet, Rev. 1.02 Table 5-1) 63 ...

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... If an event occurs in an enabled interrupt source, an associated read-only status flag will become set. The CPU will not respond until and unless the local interrupt enable is set enable the interrupt. The I bit 64 selected. The reset pin is driven low for 34 Self_reset Section 5.8.4, “System Options Register MC9S08GB60A Data Sheet, Rev. 1.02 (SOPT)” for Freescale Semiconductor ...

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... CCR was saved. The PC value that is stacked is the address of the instruction in the main program that would have executed next if the interrupt had not occurred. Freescale Semiconductor Chapter 5 Resets, Interrupts, and System Configuration NOTE MC9S08GB60A Data Sheet, Rev. 1.02 65 ...

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... INDEX REGISTER (LOW BYTE X) PROGRAM COUNTER HIGH PROGRAM COUNTER LOW ² ² TOWARD HIGHER ADDRESSES ² * High byte (H) of index register is not automatically stacked. Figure 5-1. Interrupt Stack Frame NOTE MC9S08GB60A Data Sheet, Rev. 1.02 SP AFTER INTERRUPT STACKING SP BEFORE THE INTERRUPT – 0 All DD Freescale Semiconductor ...

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... CCR the CPU will finish the current instruction, stack the PCL, PCH and CCR CPU registers, set the I bit, and then fetch the interrupt vector for the highest priority pending interrupt. Processing then continues in the interrupt service routine. Freescale Semiconductor Chapter 5 Resets, Interrupts, and System Configuration MC9S08GB60A Data Sheet, Rev. 1.02 67 ...

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... LVDF control Virq IRQ IRQF Vswi Core SWI Instruction Vreset System COP control LVD RESET pin Illegal opcode MC9S08GB60A Data Sheet, Rev. 1.02 Enable Description RTIE Real-time interrupt IICIE IIC control AIEN AD conversion complete KBIE Keyboard pins TIE SCI2 transmit TCIE ILIE ...

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... When using the external oscillator in stop3 mode, it must be enabled in stop (OSCSTEN = 1) and Freescale Semiconductor Chapter 5 Resets, Interrupts, and System Configuration level. Both the POR bit and the LVD bit in SRS are set LVDL LVWH MC9S08GB60A Data Sheet, Rev. 1.02 LVDH level, the POR ) and one low (V ). The trip ...

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... Some control bits in the SOPT and SPMSC2 registers are related to modes of operation. Although brief descriptions of these bits are provided here, the related functions are discussed in greater detail in Chapter 3, “Modes of Operation.” 70 Chapter 4, “Memory” of this data sheet for the absolute MC9S08GB60A Data Sheet, Rev. 1.02 (SRTISC),” for detailed Freescale Semiconductor ...

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... IRQ event on falling edges and low levels or on rising edges and high levels. Freescale Semiconductor Chapter 5 Resets, Interrupts, and System Configuration IRQF IRQEDG IRQPE Table 5-2. IRQSC Field Descriptions Description Sensitivity” MC9S08GB60A Data Sheet, Rev. 1. IRQIE IRQMOD IRQACK 0 0 for more details ...

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... COP ILOP Writing any value to SIMRS address clears COP watchdog timer (1) (1) Note Note Figure 5-3. System Reset Status (SRS) Table 5-3. SRS Field Descriptions Description MC9S08GB60A Data Sheet, Rev. 1. ICG LVD (1) 0 Note 0 Freescale Semiconductor ...

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... Writing 1 to this bit forces an MCU reset. This bit cannot be written from a user program. Freescale Semiconductor Chapter 5 Resets, Interrupts, and System Configuration Description Table 5-4. SBDFR Field Descriptions Description MC9S08GB60A Data Sheet, Rev. 1. BDFR ...

Page 74

... BKGD/MS. When the bit is clear, the pin will function as PTG0, which is an output-only general-purpose I/O. This pin always defaults to BKGD/MS function after any reset. 0 BKGD pin disabled. 1 BKGD pin enabled STOPE Table 5-5. SOPT Field Descriptions Description 13 cycles of BUSCLK). 18 cycles of BUSCLK). MC9S08GB60A Data Sheet, Rev. 1. BKGDPE Freescale Semiconductor ...

Page 75

... Chapter 5 Resets, Interrupts, and System Configuration REV1 REV0 ID11 (1) ( Table 5-6. SDIDH Field Descriptions Description ID5 ID4 ID3 Table 5-7. SDIDL Field Descriptions Description MC9S08GB60A Data Sheet, Rev. 1. ID10 ID9 ID8 Table 5- ID2 ID1 ID0 Table 5-6. 75 ...

Page 76

... Table 5-9. Real-Time Interrupt Period 1 Internal Clock Source ( ms, Nominal) RTI Disable periodic wakeup timer 128 ms 256 ms 512 ms 1.024 s Characteristics,” for the tolerance on these values. MC9S08GB60A Data Sheet, Rev. 1. RTIS2 RTIS RTIS External Clock Source Period = t ...

Page 77

... Low-Voltage Detect Enable — This read/write bit enables low-voltage detect logic and qualifies the operation LVDE of other bits in this register. 0 LVD logic disabled. 1 LVD logic enabled. Freescale Semiconductor Chapter 5 Resets, Interrupts, and System Configuration LVDIE LVDRE LVDSE Table 5-10. SPMSC1 Field Descriptions Description MC9S08GB60A Data Sheet, Rev. 1. (1) (1) LVDE ...

Page 78

... U = Unaffected by reset transitions below the trip point or after reset and V Supply Table 5-11. SPMSC2 Field Descriptions Description = V ). LVD LVDL = V ). LVD LVDH = V ). LVW LVWL = V ). LVW LVWH MC9S08GB60A Data Sheet, Rev. 1. PPDF PDC PPDACK already below V Supply ). LVD ...

Page 79

... Freescale Semiconductor Connections,” for more information about the logic and NOTE MC9S08GB60A Data Sheet, Rev. 1.02 79 ...

Page 80

... SERIAL PERIPHERAL INTERFACE MODULE (SPI1) SERIAL COMMUNICATIONS INTERFACE MODULE (SCI1) Table 2-2 Block Diagaram Symbol Key: = Not connected in 48-, and 44-pin packages = Not connected in 44--pin packages MC9S08GB60A Data Sheet, Rev. 1. PTA7/KBI1P7– PTA0/KBI1P0 8 8 PTB7/AD1P7– PTB0/AD1P0 PTC7 PTC6 ...

Page 81

... I/O control. Freescale Semiconductor PTA6/ PTA5/ PTA4/ PTA3/ KBI1P6 KBI1P5 KBI1P4 KBI1P3 Figure 6-2. Port A Pin Names MC9S08GB60A Data Sheet, Rev. 1.02 Chapter 6 Parallel Input/Output Chapter 2, “Pins 2 1 Bit 0 PTA2/ PTA1/ PTA0/ KBI1P2 KBI1P1 KBI1P0 Section 6.4, “Parallel 81 ...

Page 82

... Figure 6-3. Port B Pin Names (S08ATDV3),” PTC3/ PTC6 PTC5 PTC4 SCL1 Figure 6-4. Port C Pin Names Chapter 11, “Serial Communications Interface Chapter 13, “Inter-Integrated Circuit MC9S08GB60A Data Sheet, Rev. 1.02 Chapter 9, “Keyboard Interrupt 2 1 Bit 0 PTB2/ PTB1/ PTB0/ AD1P2 AD1P1 AD1P0 Section 6.4, “Parallel for more information 2 ...

Page 83

... PTE5/ PTE4/ PTE3/ PTE6 SPSCK1 MOSI1 MISO1 Figure 6-6. Port E Pin Names Chapter 11, “Serial Communications Interface Chapter 12, “Serial Peripheral Interface (S08SPIV3) MC9S08GB60A Data Sheet, Rev. 1.02 Chapter 6 Parallel Input/Output 2 1 Bit 0 PTD2/ PTD1/ PTD0/ TPM1CH2 TPM1CH1 TPM1CH0 Section 6.4, “Parallel (S08TPMV1)” for more (S08TPMV1)” ...

Page 84

... PTG6 PTG5 PTG4 PTG3 Figure 6-8. Port G Pin Names Chapter 3, “Modes of Configuration”, and Chapter 15, “Development (S08IICV1)” for more information about using these pins as MC9S08GB60A Data Sheet, Rev. 1. Bit 0 PTF2 PTF1 PTF0 Section 6.4, “Parallel 2 1 Bit 0 PTG2/ PTG1/ ...

Page 85

... Not all peripheral modules’ outputs have slew rate control; refer to Chapter 2, “Pins and rate control. Freescale Semiconductor Connections” for more information about which pins have slew MC9S08GB60A Data Sheet, Rev. 1.02 Chapter 6 Parallel Input/Output 85 ...

Page 86

... If the KBI takes control of a port A pin, the corresponding PTASE bit is ignored since the pin functions as an input. As long as PTADD is 0, the PTAPE controls the pullup enable for the KBI function. Reads of PTAD will return the logic value of the corresponding pin, provided PTADD MC9S08GB60A Data Sheet, Rev. 1.02 Freescale Semiconductor ...

Page 87

... PTAD4 PTAD3 Figure 6-9. Port A Data Register (PTAD) Table 6-1. PTAD Field Descriptions Description PTAPE5 PTAPE4 PTAPE3 Table 6-2. PTAPE Field Descriptions Description MC9S08GB60A Data Sheet, Rev. 1.02 Chapter 6 Parallel Input/Output PTAD2 PTAD1 PTAD0 PTAPE2 PTAPE1 PTAPE0 ...

Page 88

... Output driver enabled for port A bit n and PTAD reads return the contents of PTADn PTASE5 PTASE4 PTASE3 Table 6-3. PTASE Field Descriptions Description PTADD5 PTADD4 PTADD3 Table 6-4. PTADD Field Descriptions Description MC9S08GB60A Data Sheet, Rev. 1. PTASE2 PTASE1 PTASE0 PTADD2 PTADD1 PTADD0 Freescale Semiconductor ...

Page 89

... PTBD4 PTBD3 Figure 6-13. Port B Data Register (PTBD) Table 6-5. PTBD Field Descriptions Description PTBPE5 PTBPE4 PTBPE3 Table 6-6. PTBPE Field Descriptions Description MC9S08GB60A Data Sheet, Rev. 1.02 Chapter 6 Parallel Input/Output PTBD2 PTBD1 PTBD0 PTBPE2 PTBPE1 PTBPE0 ...

Page 90

... Output driver enabled for port B bit n and PTBD reads return the contents of PTBDn PTBSE5 PTBSE4 PTBSE3 Table 6-7. PTBSE Field Descriptions Description PTBDD5 PTBDD4 PTBDD3 Table 6-8. PTBDD Field Descriptions Description MC9S08GB60A Data Sheet, Rev. 1. PTBSE2 PTBSE1 PTBSE0 PTBDD2 PTBDD1 PTBDD0 Freescale Semiconductor ...

Page 91

... Reset forces PTCD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures all port pins as high-impedance inputs with pullups disabled. Freescale Semiconductor PTCD5 PTCD4 PTCD3 Figure 6-17. Port C Data Register (PTCD) Table 6-9. PTCD Field Descriptions Description MC9S08GB60A Data Sheet, Rev. 1.02 Chapter 6 Parallel Input/Output PTCD2 PTCD1 PTCD0 ...

Page 92

... Table 6-10. PTCPE Field Descriptions Description PTCSE5 PTCSE4 PTCSE3 Table 6-11. PTCSE Field Descriptions Description PTCDD5 PTCDD4 PTCDD3 Table 6-12. PTCDD Field Descriptions Description MC9S08GB60A Data Sheet, Rev. 1. PTCPE2 PTCPE1 PTCPE0 PTCSE2 PTCSE1 PTCSE0 PTCDD2 PTCDD1 ...

Page 93

... PTDD4 PTDD3 Figure 6-21. Port D Data Register (PTDD) Table 6-13. PTDD Field Descriptions Description PTDPE5 PTDPE4 PTDPE3 Table 6-14. PTDPE Field Descriptions Description MC9S08GB60A Data Sheet, Rev. 1.02 Chapter 6 Parallel Input/Output PTDD2 PTDD1 PTDD0 PTDPE2 PTDPE1 PTDPE0 ...

Page 94

... Output driver enabled for port D bit n and PTDD reads return the contents of PTDDn PTDSE5 PTDSE4 PTDSE3 Table 6-15. PTDSE Field Descriptions Description PTDDD5 PTDDD4 PTDDD3 Table 6-16. PTDDD Field Descriptions Description MC9S08GB60A Data Sheet, Rev. 1. PTDSE2 PTDSE1 PTDSE0 PTDDD2 PTDDD1 PTDDD0 Freescale Semiconductor ...

Page 95

... Reset forces PTED to all 0s, but these 0s are not driven out the corresponding pins because reset also configures all port pins as high-impedance inputs with pullups disabled. Freescale Semiconductor PTED5 PTED4 PTED3 Figure 6-25. Port E Data Register (PTED) Table 6-17. PTED Field Descriptions Description MC9S08GB60A Data Sheet, Rev. 1.02 Chapter 6 Parallel Input/Output PTED2 PTED1 PTED0 ...

Page 96

... Table 6-18. PTEPE Field Descriptions Description PTESE5 PTESE4 PTESE3 Table 6-19. PTESE Field Descriptions Description PTEDD5 PTEDD4 PTEDD3 Table 6-20. PTEDD Field Descriptions Description MC9S08GB60A Data Sheet, Rev. 1. PTEPE2 PTEPE1 PTEPE0 PTESE2 PTESE1 PTESE0 PTEDD2 PTEDD1 ...

Page 97

... PTFD5 PTFD4 PTFD3 0 0 Figure 6-29. Port PTF Data Register (PTFD) Table 6-21. PTFD Field Descriptions Description 5 4 PTFPE5 PTFPE4 PTFPE3 0 0 Table 6-22. PTFPE Field Descriptions Description MC9S08GB60A Data Sheet, Rev. 1.02 Chapter 6 Parallel Input/Output PTFD2 PTFD1 PTFPE2 PTFPE1 ...

Page 98

... Reads of PTGD will return the logic value of the corresponding pin, provided PTGDD PTFSE5 PTFSE4 PTFSE3 Table 6-23. PTFSE Field Descriptions Description PTFDD5 PTFDD4 PTFDD3 Table 6-24. PTFDD Field Descriptions Description MC9S08GB60A Data Sheet, Rev. 1. PTFSE2 PTFSE1 PTFSE0 PTFDD2 PTFDD1 PTFDD0 Freescale Semiconductor ...

Page 99

... PTGD5 PTGD4 PTGD3 0 0 Figure 6-33. Port PTG Data Register (PTGD) Table 6-25. PTGD Field Descriptions Description 5 4 PTGPE5 PTGPE4 PTGPE3 0 0 Table 6-26. PTGPE Field Descriptions Description MC9S08GB60A Data Sheet, Rev. 1.02 Chapter 6 Parallel Input/Output PTGD2 PTGD1 PTGPE2 PTGPE1 ...

Page 100

... Output driver enabled for port G bit n and PTGD reads return the contents of PTGDn. 100 PTGSE5 PTGSE4 PTGSE3 Table 6-27. PTGSE Field Descriptions Description PTGDD5 PTGDD4 PTGDD3 Table 6-28. PTGDD Field Descriptions Description MC9S08GB60A Data Sheet, Rev. 1. PTGSE2 PTGSE1 PTGSE0 PTGDD2 PTGDD1 PTGDD0 Freescale Semiconductor ...

Page 101

... Freescale Semiconductor and V are internally derived from the MCU’s V DDA SSA Appendix A, “Electrical TPM1 TPM2 RTI BUSCLK BDC NOTE MC9S08GB60A Data Sheet, Rev. 1.02 DD Characteristics.” IIC1 SCI1 SCI2 SPI1 RAM FLASH ATD1 ATD has min and max Flash has frequency frequency requirements ...

Page 102

... SERIAL PERIPHERAL INTERFACE MODULE (SPI1) SERIAL COMMUNICATIONS INTERFACE MODULE (SCI1) Table 2-2 Block Diagaram Symbol Key: = Not connected in 48- and 44--pin packages = Not connected in 44-pin packages MC9S08GB60A Data Sheet, Rev. 1. PTA7/KBI1P7– PTA0/KBI1P0 8 8 PTB7/AD1P7– PTB0/AD1P0 PTC7 PTC6 PTC5 ...

Page 103

... AND CLOCK DETECTOR IRG ICGIRCLK TYP 243 kHz 8 MHz LOCAL CLOCK FOR OPTIONAL USE WITH BDC RG for specific use of ICGOUT, FFE, ICGLCLK, ICGERCLK for specifics. Figure 7-3. ICG Block Diagram MC9S08GB60A Data Sheet, Rev. 1.02 Introduction CLOCK SELECT OUTPUT CLOCK ICGDCLK /R SELECT ICGOUT ...

Page 104

... Post-FLL divider selects bus rate divisors (/1 through /128) • Separate self-clocked source for real-time interrupt • Trimmable internal clock source supports SCI communications without additional external components • Automatic FLL engagement after lock is acquired • Selectable low-power/high-gain oscillator modes 104 Section 7.4, “Initialization/Application MC9S08GB60A Data Sheet, Rev. 1.02 Freescale Semiconductor ...

Page 105

... XTAL— Oscillator Output If upon the first write to ICGC1, either FEE mode or FBE mode is selected, this pin functions as the output of the oscillator circuit. If upon the first write to ICGC1, either FEI mode or SCM mode is selected, this Freescale Semiconductor MC9S08GB60A Data Sheet, Rev. 1.02 Oscillator Pins 105 ...

Page 106

... Recommended component values are listed in Figure 7-5. External Frequency Reference Connection 106 ICG EXTAL V SS CLOCK INPUT Figure 7-4. External Clock Connections Appendix A, “Electrical ICG EXTAL CRYSTAL OR RESONATOR MC9S08GB60A Data Sheet, Rev. 1.02 Figure 7-4. XTAL NOT CONNECTED Characteristics.” XTAL R S Freescale Semiconductor ...

Page 107

... Exiting from off mode when CLKS does not equal 10. If CLKS = X1, the ICG enters this state temporarily until the DCO is stable (DCOS = 1). • CLKS bits are written from X1 to 00. • CLKS = 1X and ICGERCLK is not detected (both ERCS = 0 and LOCS = 1). Freescale Semiconductor MC9S08GB60A Data Sheet, Rev. 1.02 Functional Description 107 ...

Page 108

... CONTROLLED LOOP OSCILLATOR FILTER FLL ANALOG CLKST PULSE COUNTER RESET AND INTERRUPT CONTROL LOCD LOCS ERCS ICGIF LOLRE LOCRE MC9S08GB60A Data Sheet, Rev. 1.02 which is nominally 8 MHz. If this RFD REDUCED ICGOUT FREQUENCY DIVIDER (R) ICGDCLK 1x 2x FREQUENCY- LOCKED LOOP (FLL) ICG2DCLK IRQ RESET ...

Page 109

... The DCO stabilizes (DCOS = 1) while in SCM upon exiting the off state with CLKS = 11. Freescale Semiconductor or less than the minimum n unlock (max) and greater than nlock (min) for a given number of samples, as MC9S08GB60A Data Sheet, Rev. 1.02 Functional Description , as required by the unlock or less than lock / R ...

Page 110

... As soon as the FLL has locked, Δn (min) and n lock lock (max) to remain locked. If Δn goes outside this range unlock MC9S08GB60A Data Sheet, Rev. 1.02 or less than lock / (2×R). This ICGDCLK (max) and greater lock /R ...

Page 111

... Forced Low 0 Forced Low 1 1 Real-Time X Forced Low 0 Forced High 1 Real-Time X Real-Time X Forced Low X Real-Time 0 Forced High 1 Real-Time X Real-Time MC9S08GB60A Data Sheet, Rev. 1.02 Functional Description Table 7-1). Provided DCO Clock Clock Monitored? Monitored (1) No Yes 2 No Yes (2) No Yes (2) Yes Yes ...

Page 112

... ICGIRCLK ICGIRCLK 0 — ICGERCLK/R 0 — ICGERCLK/R f 2/f ICGDCLK/R ICGERCLK ICGERCLK f 128/f ICGDCLK/R ICGERCLK ICGERCLK MC9S08GB60A Data Sheet, Rev. 1.02 shows the relationship between CLKS, 1 Conditions for ICGOUT CLKS = CLKST 0 — 0 — Not switching from ICGDCLK/R FBE to SCM ICGDCLK/R — ICGDCLK/R — DCOS = 0 or ICGDCLK/R — ...

Page 113

... For other applications, lowest power consumption may be the chief clock consideration. Still others may have lowest cost as the primary goal. The ICG allows great flexibility in choosing which is best for any application. Freescale Semiconductor Table Table 7-5). MC9S08GB60A Data Sheet, Rev. 1.02 Initialization/Application Information 7-4), N and R are determined by 113 ...

Page 114

... R IRG Range = ext Range = does not exceed f ICGOUT MC9S08GB60A Data Sheet, Rev. 1.02 Clock Reference Source = External < 20 MHz Bus range <= 8 MHz when crystal or resonator is P Note Typical f ICGOUT NA 8 MHz out of reset NA 64 ...

Page 115

... REFS CLKS MFD LOCRE REFST LOLS LOCK FLT TRIM Figure 7-7. ICG Register Set MC9S08GB60A Data Sheet, Rev. 1.02 Initialization/Application Information Division Factor (R) ÷1 ÷2 ÷4 ÷8 ÷16 ÷32 ÷64 ÷128 Bit 0 OSCSTEN LOCD RFD LOCS ERCS ...

Page 116

... Oscillator using crystal or resonator is requested FLL engaged, external reference clock mode Oscillator disabled in stop modes Loss-of-clock detection enabled Unimplemented or reserved, always reads zero Generates an interrupt request on loss of lock Generates an interrupt request on loss of clock MC9S08GB60A Data Sheet, Rev. 1.02 ). Bus = 32 kHz Freescale Semiconductor Eqn. 7-1 Eqn. 7-2 ...

Page 117

... Configures oscillator for high-frequency range; FLL prescale factor is 1 Requests an oscillator FLL engaged, external reference clock mode Disables the oscillator in stop modes Loss-of-clock detection enabled Unimplemented or reserved, always reads zero MC9S08GB60A Data Sheet, Rev. 1.02 Initialization/Application Information MINIMUM CURRENT DRAW IN STOP RECOVERY FROM STOP3 OSCSTEN = 0 CHECK NO FLL LOCK STATUS ...

Page 118

... Figure 7-9. ICG Initialization and Stop Recovery for Example #2 118 Generates an interrupt request on loss of lock Generates an interrupt request on loss of clock RECOVERY FROM STOP3 INITIALIZE ICG SERVICE INTERRUPT ICG1 = $7A ICG2 = $30 SOURCE (f CHECK NO LOCK = 1? FLL LOCK STATUS LOCK = 1? YES CONTINUE CONTINUE MC9S08GB60A Data Sheet, Rev. 1. MHz) Bus CHECK NO YES Freescale Semiconductor ...

Page 119

... Loss-of-clock detection enabled Unimplemented or reserved, always reads zero Generates an interrupt request on loss of lock Generates an interrupt request on loss of clock Only need to write when trimming internal oscillator; done in separate operation (see example #4) MC9S08GB60A Data Sheet, Rev. 1.02 Initialization/Application Information ). Bus = 243 kHz Eqn. 7-5 Eqn ...

Page 120

... This section outlines one example of trimming the internal oscillator. Many other possible trimming procedures are valid and can be used. 120 NO YES NOTE: THIS WILL REQUIRE THE INTERAL REFERENCE CLOCK TO START AND STABILIZE. MC9S08GB60A Data Sheet, Rev. 1.02 RECOVERY FROM STOP3 CHECK NO FLL LOCK STATUS. LOCK = 1? ...

Page 121

... ICGTRM + 128 / (2**n) (INCREASING ICGTRM DECREASES THE FREQUENCY YES IS n > Figure 7-11. Trim Procedure Chapter 4, “Memory” of this data sheet for the absolute MC9S08GB60A Data Sheet, Rev. 1.02 ICG Registers and Control Bits STORE ICGTRM VALUE IN NON-VOLATILE MEMORY CONTINUE Figure 7-11 while the 121 ...

Page 122

... Oscillator enabled when ICG is in off mode, CLKS = 1X and REFST = 1. 1 Loss of Clock Disable LOCD 0 Loss of clock detection enabled. 1 Loss of clock detection disabled. 122 5 4 REFS CLKS 0 0 Figure 7-12. ICG Control Register 1 (ICGC1) Table 7-6. ICGC1 Field Descriptions Description MC9S08GB60A Data Sheet, Rev. 1. OSCSTEN LOCD Freescale Semiconductor ...

Page 123

... Division Factor ( 110 Division Factor ( 111 Division Factor (R) = 128 Freescale Semiconductor 5 4 MFD LOCRE 0 0 Figure 7-13. ICG Control Register 2 (ICGC2) Table 7-7. ICGC2 Field Descriptions Description MC9S08GB60A Data Sheet, Rev. 1.02 ICG Registers and Control Bits RFD 123 ...

Page 124

... Writing ICGIF has no effect ICG interrupt request is pending ICG interrupt request is pending. 124 REFST LOLS LOCK Figure 7-14. ICG Status Register 1 (ICGS1) Table 7-8. ICGS1 Field Descriptions Description MC9S08GB60A Data Sheet, Rev. 1. ICG LOCS ERCS Freescale Semiconductor ...

Page 125

... Table 7-9. ICGS2 Field Descriptions Description for two consecutive samples and the DCO clock is not static. This bit is unlock Table 7-10. ICGFLTU Field Descriptions Description MC9S08GB60A Data Sheet, Rev. 1.02 ICG Registers and Control Bits DCOS ...

Page 126

... FLT Table 7-11. ICGFLTL Field Descriptions Description TRIM Unaffected by MCU reset Figure 7-18. ICG Trim Register (ICGTRM) Table 7-12. ICGTRM Field Descriptions Description MC9S08GB60A Data Sheet, Rev. 1. Freescale Semiconductor ...

Page 127

... Overflow, half-carry, negative, zero, and carry condition codes support conditional branching on the results of signed, unsigned, and binary-coded decimal (BCD) operations • Efficient bit manipulation instructions • Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions • STOP and WAIT instructions to invoke low-power operating modes Freescale Semiconductor MC9S08GB60A Data Sheet, Rev. 1.02 127 ...

Page 128

... ACCUMULATOR A 16-BIT INDEX REGISTER H:X INDEX REGISTER (LOW STACK POINTER PROGRAM COUNTER CCR CARRY ZERO NEGATIVE INTERRUPT MASK HALF-CARRY (FROM BIT 3) TWO’S COMPLEMENT OVERFLOW Figure 8-1. CPU Registers MC9S08GB60A Data Sheet, Rev. 1.02 Freescale Semiconductor ...

Page 129

... For a more detailed explanation of how each instruction sets the CCR bits, refer to the HCS08 Family Reference Manual, volume 1, Freescale Semiconductor document order number HCS08RMv1. Freescale Semiconductor MC9S08GB60A Data Sheet, Rev. 1.02 Chapter 8 Central Processor Unit (S08CPUV2) 129 ...

Page 130

... No carry out of bit 7 1 Carry out of bit 7 130 CCR CARRY ZERO NEGATIVE INTERRUPT MASK HALF-CARRY (FROM BIT 3) TWO’S COMPLEMENT OVERFLOW Figure 8-2. Condition Code Register Table 8-1. CCR Register Field Descriptions Description MC9S08GB60A Data Sheet, Rev. 1.02 Freescale Semiconductor ...

Page 131

... This is faster and more memory efficient than specifying a complete 16-bit address for the operand. Freescale Semiconductor MC9S08GB60A Data Sheet, Rev. 1.02 Chapter 8 Central Processor Unit (S08CPUV2) 131 ...

Page 132

... SP-Relative, 8-Bit Offset (SP1) This variation of indexed addressing uses the 16-bit value in the stack pointer (SP) plus an unsigned 8-bit offset included in the instruction as the address of the operand needed to complete the instruction. 132 MC9S08GB60A Data Sheet, Rev. 1.02 Freescale Semiconductor ...

Page 133

... After the CCR contents are pushed onto the stack, the I bit in the CCR is set to prevent other interrupts while in the interrupt service routine. Although it is possible to clear the I bit with an instruction in the Freescale Semiconductor Resets, Interrupts, and System Configuration MC9S08GB60A Data Sheet, Rev. 1.02 Chapter 8 Central Processor Unit (S08CPUV2) 133 ...

Page 134

... MCU even stop mode. Recovery from stop mode depends on the particular HCS08 and whether the oscillator was stopped in stop mode. Refer to the Modes of Operation 134 chapter for more details. MC9S08GB60A Data Sheet, Rev. 1.02 Freescale Semiconductor ...

Page 135

... Software-based breakpoints can be set by replacing an opcode at the desired breakpoint address with the BGND opcode. When the program reaches this breakpoint address, the CPU is forced to active background mode rather than continuing the user program. Freescale Semiconductor MC9S08GB60A Data Sheet, Rev. 1.02 Chapter 8 Central Processor Unit (S08CPUV2) 135 ...

Page 136

... Two’s complement overflow indicator, bit Half carry, bit Interrupt mask, bit Negative indicator, bit Zero indicator, bit Carry/borrow, bit 0 (carry out of bit CCR activity notation Bit not affected – = 136 MC9S08GB60A Data Sheet, Rev. 1.02 Table 8-2. Freescale Semiconductor ...

Page 137

... Address modes Inherent (no operands) INH = 8-bit or 16-bit immediate IMM = 8-bit direct DIR = 16-bit extended EXT = Freescale Semiconductor MC9S08GB60A Data Sheet, Rev. 1.02 Chapter 8 Central Processor Unit (S08CPUV2) 137 ...

Page 138

... IMM M is sign extended to a 16-bit value A ← (A) & (M) 0 – – Branch if ( – – – – – – REL MC9S08GB60A Data Sheet, Rev. 1.02 Effect on CCR IMM A9 ii DIR B9 dd EXT IX2 ...

Page 139

... Branch if ( – – – – – – Branch if ( – – – – – – Branch if ( – – – – – – No Test MC9S08GB60A Data Sheet, Rev. 1.02 Chapter 8 Central Processor Unit (S08CPUV2) Effect on CCR DIR (b0 DIR (b1) ...

Page 140

... A ← (A) = 0xFF – (A) X ← (X) = 0xFF – (X) 0 – – M ← (M) = 0xFF – (M) M ← (M) = 0xFF – (M) M ← (M) = 0xFF – (M) (H:X) – (M:M + 0x0001) (CCR Updated But Operands Not Changed) MC9S08GB60A Data Sheet, Rev. 1.02 Effect on CCR DIR (b0 DIR (b1 ...

Page 141

... Push (PCL); SP ← (SP) – 0x0001 – – – – – – Push (PCH); SP ← (SP) – 0x0001 PC ← Unconditional Address A ← (M) 0 – – H:X ← (M:M + 0x0001) 0 – – MC9S08GB60A Data Sheet, Rev. 1.02 Chapter 8 Central Processor Unit (S08CPUV2) Effect on CCR IMM A3 ii DIR ...

Page 142

... SP ← (SP + 0x0001); Pull (A) – – – – – – SP ← (SP + 0x0001); Pull (H) – – – – – – SP ← (SP + 0x0001); Pull (X) – – – – – – MC9S08GB60A Data Sheet, Rev. 1.02 Effect on CCR IMM AE ii DIR BE dd EXT ...

Page 143

... Push (A); SP ← (SP) – 0x0001 – – 1 – – – Push (CCR); SP ← (SP) – 0x0001 I ← 1; PCH ← Interrupt Vector High Byte PCL ← Interrupt Vector Low Byte MC9S08GB60A Data Sheet, Rev. 1.02 Chapter 8 Central Processor Unit (S08CPUV2) Effect on CCR DIR 36 dd ...

Page 144

... H:X ← (SP) + 0x0001 – – – – – – A ← (X) – – – – – – SP ← (H:X) – 0x0001 – – – – – – I bit ← 0; Halt CPU – – 0 – – – MC9S08GB60A Data Sheet, Rev. 1.02 Effect on CCR INH 84 INH 97 INH ...

Page 145

... IX 1 INH 1 SP1 Stack Pointer, 8-Bit Offset SP2 Stack Pointer, 16-Bit Offset IX+ Indexed, No Offset with Post Increment IX1+ Indexed, 1-Byte Offset with Post Increment MC9S08GB60A Data Sheet, Rev. 1.02 Chapter 8 Central Processor Unit (S08CPUV2) Register/Memory BGE SUB SUB ...

Page 146

... TST 3 SP1 9E6F 6 CLR 3 SP1 SP1 Stack Pointer, 8-Bit Offset SP2 Stack Pointer, 16-Bit Offset IX+ Indexed, No Offset with Post Increment IX1+ Indexed, 1-Byte Offset with Post Increment MC9S08GB60A Data Sheet, Rev. 1.02 Register/Memory 9ED0 5 9EE0 SUB 4 SP2 3 9ED1 5 9EE1 CMP 4 SP2 3 9ED2 5 ...

Page 147

... Capable of waking up the MCU from stop3 or wait mode Freescale Semiconductor Connections” for more information about the logic and hardware aspects PTA6/ PTA5/ PTA4/ KBI1P6 KBI1P5 KBI1P4 Figure 9-1. Port A Pin Names MC9S08GB60A Data Sheet, Rev. 1.02 PTA3/ PTA2/ PTA1/ PTA0/ KBI1P3 KBI1P2 KBI1P1 KBI1P0 147 ...

Page 148

... SERIAL PERIPHERAL INTERFACE MODULE (SPI1) SERIAL COMMUNICATIONS INTERFACE MODULE (SCI1) Table 2-2 Block Diagaram Symbol Key: = Not connected in 48- and 44--pin packages = Not connected in 44-pin packages MC9S08GB60A Data Sheet, Rev. 1. PTA7/KBI1P7– PTA0/KBI1P0 8 8 PTB7/AD1P7– PTB0/AD1P0 PTC7 PTC6 PTC5 ...

Page 149

... Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. Freescale Semiconductor V DD CLR KEYBOARD INTERRUPT FF KBIMOD Figure 9-3. KBI Block Diagram MC9S08GB60A Data Sheet, Rev. 1.02 Keyboard Interrupt (S08KBIV1) BUSCLK KBACK RESET KBF SYNCHRONIZER STOP BYPASS STOP KEYBOARD INTERRUPT REQUEST KBIE ...

Page 150

... Rising edges-only or rising edges and high levels (KBEDGn = 1) • Falling edges-only or falling edges and low levels (KBEDGn = 0) 0 Edge-only detection 1 Edge-and-level detection 150 KBF KBEDG5 KBEDG4 Description MC9S08GB60A Data Sheet, Rev. 1. KBIE KBIMOD KBACK Freescale Semiconductor ...

Page 151

... In stop mode, KBI inputs act as asynchronous level-sensitive inputs so they can wake the MCU from stop mode. Freescale Semiconductor KBIPE5 KBIPE4 KBIPE3 Description MC9S08GB60A Data Sheet, Rev. 1.02 Keyboard Interrupt (S08KBIV1 KBIPE2 KBIPE1 KBIPE0 151 ...

Page 152

... When KBIMOD = 0 (selecting edge-only operation), KBF is always cleared by writing 1 to KBACK. When KBIMOD = 1 (selecting edge-and-level operation), KBF cannot be cleared as long as any keyboard input is at its asserted level. 152 MC9S08GB60A Data Sheet, Rev. 1.02 Freescale Semiconductor ...

Page 153

... Timer system enable • One interrupt per channel plus terminal count interrupt Freescale Semiconductor (Section 7.3.9, “Fixed Frequency MC9S08GB60A Data Sheet, Rev. 1.02 Clock”). Selecting XCLK as the clock 153 ...

Page 154

... SERIAL PERIPHERAL INTERFACE MODULE (SPI1) SERIAL COMMUNICATIONS INTERFACE MODULE (SCI1) Table 2-2 Block Diagaram Symbol Key: = Not connected in 48- and 44-pin packages = Not connected in 44-pin packages MC9S08GB60A Data Sheet, Rev. 1. PTA7/KBI1P7– PTA0/KBI1P0 8 8 PTB7/AD1P7– PTB0/AD1P0 PTC7 PTC6 PTC5 ...

Page 155

... CH0IE MS0B MS0A ELS1B ELS1A CH1F CH1IE MS1B MS1A ELSnB ELSnA CHnF CHnIE MSnA MSnB Figure 10-2. TPM Block Diagram MC9S08GB60A Data Sheet, Rev. 1.02 Timer/PWM (TPM) Block Description DIVIDE BY <st-blue> INTERRUPT LOGIC PORT TPMxCH0 LOGIC INTERRUPT LOGIC TPMxCH1 PORT LOGIC INTERRUPT LOGIC ...

Page 156

... TPM. Each TPM channel is optionally associated with an MCU pin and a maskable interrupt function. The TPM has center-aligned PWM capabilities controlled by the CPWMS control bit in TPMxSC. When CPWMS is set to 1, timer counter TPMxCNT changes to an up-/down-counter and all channels in the 156 Pins and Connections MC9S08GB60A Data Sheet, Rev. 1.02 chapter for additional information Freescale Semiconductor ...

Page 157

... This corresponds to the end of a PWM period. (The $0000 count value corresponds to the center of a period.) Freescale Semiconductor Section 10.7.1, “Timer x Status and Control for more information about clock source selection. MC9S08GB60A Data Sheet, Rev. 1.02 Timer/PWM (TPM) 157 ...

Page 158

... TPM are configured for input capture or output compare functions. The period of this PWM signal is determined by the setting in the modulus register (TPMxMODH:TPMxMODL). The duty cycle is determined by the setting in the timer channel value 158 MC9S08GB60A Data Sheet, Rev. 1.02 Freescale Semiconductor ...

Page 159

... Freescale Semiconductor OVERFLOW PERIOD PULSE WIDTH OUTPUT OUTPUT COMPARE COMPARE period = 2 x (TPMxMODH:TPMxMODL); for TPMxMODH:TPMxMODL = $0001–$7FFF MC9S08GB60A Data Sheet, Rev. 1.02 Timer/PWM (TPM) OVERFLOW OUTPUT COMPARE Eqn. 10-1 Eqn. 10-2 159 ...

Page 160

... Writing to TPMxCnSC cancels any values written to the channel value registers and resets the coherency mechanism for TPMxCnVH:TPMxCnVL. 160 COUNT = 0 OUTPUT OUTPUT COMPARE COMPARE (COUNT UP) (COUNT DOWN) PULSE WIDTH 2 x PERIOD 2 x MC9S08GB60A Data Sheet, Rev. 1.02 COUNT = TPMxMODH:TPMx Freescale Semiconductor ...

Page 161

... The flag is cleared by the 2-step sequence described in Section 10.6.1, “Clearing Timer Interrupt Freescale Semiconductor chapter for absolute interrupt vector addresses, priority, and local Flags.” Flags.” MC9S08GB60A Data Sheet, Rev. 1.02 Timer/PWM (TPM) Resets, 161 ...

Page 162

... TPM and which channel is being referenced. For example, TPMxCnSC refers to timer (TPM) x, channel n and TPM1C2SC is the status and control register for timer 1, channel 2. 162 Section 10.6.1, “Clearing Timer Interrupt Memory chapter of this data sheet for the absolute address MC9S08GB60A Data Sheet, Rev. 1.02 Flags.” Freescale Semiconductor ...

Page 163

... This prescaler is located after any clock source synchronization or clock source selection affects whatever clock source is selected to drive the TPM system. Freescale Semiconductor CPWMS CLKSB CLKSA Description Table 10-2, this 2-bit field is used to disable the TPM system or select one MC9S08GB60A Data Sheet, Rev. 1.02 Timer/PWM (TPM PS2 PS1 PS0 163 ...

Page 164

... Table 10-3. Prescale Divisor Selection Any write to TPMxCNTH clears the 16-bit counter Any write to TPMxCNTL clears the 16-bit counter MC9S08GB60A Data Sheet, Rev. 1. TPM Clock Source Divided- 128 ...

Page 165

... An alternative approach is to reset the TPM counter before writing to the TPM modulo registers to avoid confusion about when the first counter overflow will occur. Freescale Semiconductor MC9S08GB60A Data Sheet, Rev. 1.02 Timer/PWM (TPM Bit Bit 165 ...

Page 166

... MSnB MSnA ELSnB Description Table 10-5 Table 10-5, these bits select the polarity of the input edge that triggers an MC9S08GB60A Data Sheet, Rev. 1. ELSnA 0 0 Table 10-5. for a summary of channel mode and setup Freescale Semiconductor ...

Page 167

... Low-true pulses (set output on compare) 10 High-true pulses (clear output on compare-up) Center-aligned PWM X1 Low-true pulses (set output on compare-up MC9S08GB60A Data Sheet, Rev. 1.02 Timer/PWM (TPM) Configuration Bit Bit 167 ...

Page 168

... When both bytes have been written, they are transferred as a coherent 16-bit value into the timer channel value registers. This latching mechanism may be manually reset by writing to the TPMxCnSC register. This latching mechanism allows coherent 16-bit writes in either order, which is friendly to various compiler implementations. 168 MC9S08GB60A Data Sheet, Rev. 1.02 Freescale Semiconductor ...

Page 169

... This SCI system offers many advanced features not commonly found on other asynchronous serial I/O peripherals on other embedded controllers. The receiver employs an advanced data sampling technique that ensures reliable communication and noise detection. Hardware parity, receiver wakeup, and double buffering on transmit and receive are also included. Freescale Semiconductor MC9S08GB60A Data Sheet, Rev. 1.02 169 ...

Page 170

... SERIAL PERIPHERAL INTERFACE MODULE (SPI1) SERIAL COMMUNICATIONS INTERFACE MODULE (SCI1) Table 2-2 Block Diagaram Symbol Key: = Not connected in 48- and 44--pin packages = Not connected in 44-pin packages MC9S08GB60A Data Sheet, Rev. 1. PTA7/KBI1P7– PTA0/KBI1P0 8 8 PTB7/AD1P7– PTB0/AD1P0 PTC7 PTC6 PTC5 ...

Page 171

... Section 11.3, “Functional Description,” for a detailed description of SCI operation in the different modes. • 8- and 9- bit data modes • Stop modes — SCI is halted during all stop modes • Loop modes Freescale Semiconductor MC9S08GB60A Data Sheet, Rev. 1.02 Serial Communications Interface (S08SCIV1) 171 ...

Page 172

... SHIFT DIRECTION T8 PARITY GENERATION TRANSMIT CONTROL TDRE TIE TC TCIE Figure 11-2. SCI Transmitter Block Diagram MC9S08GB60A Data Sheet, Rev. 1.02 shows the receiver portion of the SCI.) LOOPS RSRC LOOP TO RECEIVE CONTROL DATA IN TO TxD PIN SCI CONTROLS TxD TO TxD PIN LOGIC ...

Page 173

... WAKE WAKEUP LOGIC ILT RDRF RIE IDLE ILIE OR ORIE FE FEIE NF NEIE PARITY PF CHECKING PEIE Figure 11-3. SCI Receiver Block Diagram MC9S08GB60A Data Sheet, Rev. 1.02 Serial Communications Interface (S08SCIV1 SHIFT DIRECTION RWU Rx INTERRUPT REQUEST ERROR INTERRUPT REQUEST 173 ...

Page 174

... When 8191, the SCI baud rate = BUSCLK/(16×BR). See also BR bits in 174 Memory chapter of this data sheet for the absolute address SBR12 SBR11 Description SBR5 SBR4 SBR3 Description MC9S08GB60A Data Sheet, Rev. 1. SBR10 SBR9 SBR8 Table 11- SBR2 SBR1 SBR0 Table 11-1. Freescale Semiconductor ...

Page 175

... Even parity. 1 Odd parity. Freescale Semiconductor RSRC M WAKE Description Section 11.3.3.2, “Receiver Wakeup Wakeup” for more information. MC9S08GB60A Data Sheet, Rev. 1.02 Serial Communications Interface (S08SCIV1 ILT Operation” for more 175 ...

Page 176

... Receiver Enable — When the SCI receiver is off, the RxD pin reverts to being a general-purpose port I/O pin LOOPS = 1 , the RxD pin reverts to being a general-purpose I/O pin even Receiver off. 1 Receiver on. 176 RIE ILIE Description Idle,” for more details. MC9S08GB60A Data Sheet, Rev. 1. RWU SBK Freescale Semiconductor ...

Page 177

... Description Section 11.3.3.2, “Receiver Wakeup Section 11.3.2.1, “Send Break and Queued 5 4 RDRF IDLE Figure 11-8. SCI Status Register 1 (SCIxS1) Description MC9S08GB60A Data Sheet, Rev. 1.02 Serial Communications Interface (S08SCIV1) Operation,” for more details. Idle,” for more details ...

Page 178

... Parity Error Flag — set at the same time as RDRF when parity is enabled ( and the parity bit in PF the received character does not agree with the expected parity value. To clear PF, read SCIxS1 and then read the SCI data register (SCIxD parity error. 1 Parity error. 178 Description MC9S08GB60A Data Sheet, Rev. 1.02 Freescale Semiconductor ...

Page 179

... TxD pin is an input in single-wire mode. 1 TxD pin is an output in single-wire mode. Freescale Semiconductor Figure 11-9. SCI Status Register 2 (SCIxS2) Description TXDIR ORIE 0 0 Description MC9S08GB60A Data Sheet, Rev. 1.02 Serial Communications Interface (S08SCIV1 NEIE FEIE ...

Page 180

... SCI status flags Reset 0 0 180 Description Figure 11-11. SCI Data Register (SCIxD) MC9S08GB60A Data Sheet, Rev. 1. Freescale Semiconductor ...

Page 181

... When the transmit shift register is available for a new SCI character, the value waiting in Freescale Semiconductor DIVIDE BY 16 SBR12:SBR0 Rx SAMPLING CLOCK (16 × BAUD RATE) BAUD RATE = [SBR12:SBR0] × 16 Figure 11-12. SCI Baud Rate Generation MC9S08GB60A Data Sheet, Rev. 1.02 Serial Communications Interface (S08SCIV1) Tx BAUD RATE BUSCLK (Figure 11-2), as well as 181 ...

Page 182

... If RDRF was already set indicating the receive data register (buffer) was already full, the overrun (OR) status flag is set and the new data is lost. Because the SCI receiver is double-buffered, the 182 Modes.” For the remainder of this discussion, we assume the SCI MC9S08GB60A Data Sheet, Rev. 1.02 Freescale Semiconductor ...

Page 183

... At the end of a message the beginning of the next message, all receivers automatically force RWU all receivers wake up in time to look at the first character(s) of the next message. Freescale Semiconductor MC9S08GB60A Data Sheet, Rev. 1.02 Serial Communications Interface (S08SCIV1) Section 11.3.4, 183 ...

Page 184

... TIE or TCIE local interrupt masks are 0s. When a program detects that the receive data register is full (RDRF = 1), it gets the data from the receive data register by reading SCIxD. The RDRF flag is cleared by reading SCIxS1 while RDRF = 1 and then reading SCIxD. 184 MC9S08GB60A Data Sheet, Rev. 1.02 Freescale Semiconductor ...

Page 185

... Because the clocks are halted, the SCI module will resume operation upon exit from stop (only in stop3 mode). Software should ensure stop mode is not entered while there is a character being transmitted out of or received into the SCI module. Freescale Semiconductor MC9S08GB60A Data Sheet, Rev. 1.02 Serial Communications Interface (S08SCIV1) 185 ...

Page 186

... TxD1 pin so an external device can send serial data to the receiver. When TXDIR = 1, the TxD1 pin is an output driven by the transmitter. In single-wire mode, the internal loop back connection from the transmitter to the receiver causes the receiver to receive characters that are sent out by the transmitter. 186 MC9S08GB60A Data Sheet, Rev. 1.02 Freescale Semiconductor ...

Page 187

... SPI functionality are shared with port E pins 2–5. See the Characteristics,” appendix for SPI electrical parametric information. When the SPI is enabled, the direction of pins is controlled by module configuration. If the SPI is disabled, all four pins can be used as general-purpose I/O. Freescale Semiconductor MC9S08GB60A Data Sheet, Rev. 1.02 Appendix A, “Electrical 187 ...

Page 188

... SERIAL PERIPHERAL INTERFACE MODULE (SPI1) SERIAL COMMUNICATIONS INTERFACE MODULE (SCI1) Table 2-2 Block Diagaram Symbol Key: = Not connected in 48 44-pin packages = Not connected in 44-pin packages MC9S08GB60A Data Sheet, Rev. 1. PTA7/KBI1P7– PTA0/KBI1P0 8 8 PTB7/AD1P7– PTB0/AD1P0 PTC7 PTC6 PTC5 ...

Page 189

... In this system, the master device has configured its SS pin as an optional slave select output. MASTER SPI SHIFTER CLOCK GENERATOR Freescale Semiconductor MOSI MOSI MISO MISO SPSCK SPSCK SS SS Figure 12-2. SPI System Connections MC9S08GB60A Data Sheet, Rev. 1.02 SLAVE SPI SHIFTER 189 ...

Page 190

... MISO, and the shifter input is routed from the MOSI pin. In the external SPI system, simply connect all SPSCK pins to each other, all MISO pins together, and all MOSI pins together. Peripheral devices often use slightly different names for these pins. 190 MC9S08GB60A Data Sheet, Rev. 1.02 Freescale Semiconductor ...

Page 191

... Rx BUFFER (READ SPI1D) SHIFT Rx BUFFER Tx BUFFER FULL CLOCK EMPTY CLOCK LOGIC MODE FAULT DETECTION SPTEF SPRF SPTIE MODF SPIE Figure 12-3. SPI Module Block Diagram MC9S08GB60A Data Sheet, Rev. 1.02 PIN CONTROL SPC0 BIDIROE MASTER CLOCK M SLAVE CLOCK S MASTER/ SLAVE MODFEN SSOE SPI ...

Page 192

... PRESCALER CLOCK RATE DIVIDER DIVIDE 16, 32, 64, 128, or 256 SPPR2:SPPR1:SPPR0 SPR2:SPR1:SPR0 Figure 12-4. SPI Baud Rate Generation MC9S08GB60A Data Sheet, Rev. 1.02 MASTER DIVIDE BY SPI BIT RATE Freescale Semiconductor ...

Page 193

... Interrupts from SPTEF inhibited (use polling) 1 When SPTEF is 1, hardware interrupt requested Freescale Semiconductor Memory chapter of this data sheet for the absolute address SPTIE MSTR CPOL Table 12-1. SPI1C1 Field Descriptions Description MC9S08GB60A Data Sheet, Rev. 1. CPHA SSOE LSBFE 193 ...

Page 194

... General-purpose I/O (not SPI) General-purpose I/O (not SPI) SS input for mode fault Automatic SS output NOTE MODFEN BIDIROE MC9S08GB60A Data Sheet, Rev. 1.02 Table 12-2. Slave Mode Slave select input Slave select input Slave select input Slave select input SPISWAI SPC0 ...

Page 195

... The input to this divider comes from the SPI baud rate prescaler (see divider is the SPI bit rate clock for master mode. Freescale Semiconductor Description SPPR1 SPPR0 Description Figure 12-4). MC9S08GB60A Data Sheet, Rev. 1. SPR2 SPR1 SPR0 Figure 12-4). The output of this 195 ...

Page 196

... Table 12-5. SPI Baud Rate Prescaler Divisor Prescaler Divisor 0:0:0 0:0:1 0:1:0 0:1:1 1:0:0 1:0:1 1:1:0 1:1:1 Table 12-6. SPI Baud Rate Divisor 0:0:0 0:0:1 0:1:0 0:1:1 1:0:0 1:0:1 1:1:0 1:1 SPTEF MODF 1 0 Figure 12-8. SPI Status Register (SPI1S) MC9S08GB60A Data Sheet, Rev. 1. Rate Divisor 128 256 ...

Page 197

... Freescale Semiconductor Description Figure 12-9. SPI Data Register (SPI1D) MC9S08GB60A Data Sheet, Rev. 1. Bit 197 ...

Page 198

... LSBFE. Both variations of SPSCK polarity are shown, but only one of these waveforms applies for a specific transfer, depending on the value in CPOL. The SAMPLE IN waveform applies to the MOSI input of a slave or the MISO input of a master. The MOSI waveform applies to the 198 MC9S08GB60A Data Sheet, Rev. 1.02 Freescale Semiconductor ...

Page 199

... SPSCK edge. The MSB first and LSB first lines show the order of SPI data bits depending on the setting Freescale Semiconductor 1 2 ... BIT 7 BIT 6 ... BIT 0 BIT 1 ... Figure 12-10. SPI Clock Formats (CPHA = 1) MC9S08GB60A Data Sheet, Rev. 1. BIT 2 BIT 1 BIT 0 BIT 5 BIT 6 BIT 7 199 ...

Page 200

... MOSI and MISO outputs of the master and slave, respectively. When CPHA = 0, the slave’s SS input must go to its inactive high level between transfers. 200 2 ... 6 BIT 6 ... BIT 2 BIT 1 BIT 5 ... Figure 12-11. SPI Clock Formats (CPHA = 0) MC9S08GB60A Data Sheet, Rev. 1. BIT 1 BIT 0 BIT 6 BIT 7 Freescale Semiconductor ...

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