MC9S08GT16ACFBE Freescale Semiconductor, MC9S08GT16ACFBE Datasheet
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MC9S08GT16A MC9S08GT8A Data Sheet HCS08 Microcontrollers MC9S08GT16A Rev. 1 7/2006 freescale.com ...
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MC9S08GT16A/GT8A Features 8-Bit HCS08 Central Processor Unit (CPU) • 40-MHz HCS08 CPU • HC08 instruction set with added BGND instruction • Support for interrupt/reset sources Memory Options • FLASH read/program/erase down to 1.8 V • ...
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... MC9S08GT16A/GT8A Data Sheet Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. © Freescale Semiconductor, Inc., 2006. All rights reserved. Covers: MC9S08GT16A MC9S08GT8A MC9S08GT16A Rev. 1 7/2006 ...
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... The following revision history table summarizes changes contained in this document. Revision Revision Number Date 1 07/17/2006 Initial public release © Freescale Semiconductor, Inc., 2006. All rights reserved. This product incorporates SuperFlash Description of Changes ® Technology licensed from SST. ...
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... Serial Communications Interface (S08SCIV1)..................... 169 Chapter 12 Serial Peripheral Interface (S08SPIV3) ................................ 187 Chapter 13 Inter-Integrated Circuit (S08IICV1) ....................................... 205 Chapter 14 Analog-to-Digital Converter (S08ATDV3) ............................ 221 Chapter 15 Development Support ........................................................... 237 Appendix A Electrical Characteristics...................................................... 259 Appendix B Ordering Information and Mechanical Drawings................ 285 Freescale Semiconductor MC9S08GT16A/GT8A Data Sheet, Rev ...
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... Wait Mode .......................................................................................................................................34 3.5 Stop Modes ......................................................................................................................................35 3.5.1 Stop1 Mode .......................................................................................................................35 3.5.2 Stop2 Mode .......................................................................................................................35 3.5.3 Stop3 Mode .......................................................................................................................36 3.5.4 Active BDM Enabled in Stop Mode .................................................................................37 3.5.5 LVD Enabled in Stop Mode ..............................................................................................37 3.5.6 On-Chip Peripheral Modules in Stop Modes ....................................................................38 Freescale Semiconductor Contents Title Chapter 1 Device Overview Chapter 2 Pins and Connections , — ...
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... Interrupt Vectors, Sources, and Local Masks ....................................................................67 5.5 Low-Voltage Detect (LVD) System ................................................................................................69 5.5.1 Power-On Reset Operation ...............................................................................................69 5.5.2 LVD Reset Operation ........................................................................................................69 5.5.3 LVD Interrupt Operation ...................................................................................................69 5.5.4 Low-Voltage Warning (LVW) ...........................................................................................69 5.6 Real-Time Interrupt (RTI) ...............................................................................................................69 5.7 Register Definition ..........................................................................................................................70 10 Title Chapter 4 Memory Chapter 5 MC9S08GT16A/GT8A Data Sheet, Rev. 1 Page Freescale Semiconductor ...
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... Introduction .....................................................................................................................................99 7.1.1 Port A and Keyboard Interrupt Pins ..................................................................................99 7.1.2 Features .............................................................................................................................99 7.1.3 KBI Block Diagram ........................................................................................................101 7.2 Register Definition ........................................................................................................................101 7.2.1 KBI Status and Control Register (KBISC) .....................................................................102 Freescale Semiconductor Title Chapter 6 Parallel Input/Output Chapter 7 Keyboard Interrupt (S08KBIV1) MC9S08GT16A/GT8A Data Sheet, Rev. 1 Page ...
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... Special Operations .........................................................................................................................111 8.4.1 Reset Sequence ...............................................................................................................111 8.4.2 Interrupt Sequence ..........................................................................................................111 8.4.3 Wait Mode Operation ......................................................................................................112 8.4.4 Stop Mode Operation ......................................................................................................112 8.4.5 BGND Instruction ...........................................................................................................113 8.5 HCS08 Instruction Set Summary ..................................................................................................114 12 Title Chapter 8 MC9S08GT16A/GT8A Data Sheet, Rev. 1 Page Freescale Semiconductor ...
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... Example #1: External Crystal = 32 kHz, Bus Frequency = 4.19 MHz ...........................145 9.5.3 Example #2: External Crystal = 4 MHz, Bus Frequency = 20 MHz ..............................147 9.5.4 Example #3: No External Crystal Connection, 5.4 MHz Bus Frequency ......................149 9.5.5 Example #4: Internal Clock Generator Trim ..................................................................151 Freescale Semiconductor Title Chapter 9 MC9S08GT16A/GT8A Data Sheet, Rev. 1 ...
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... SCI Control Register 2 (SCIxC2) ...................................................................................176 11.2.4 SCI Status Register 1 (SCIxS1) ......................................................................................177 11.2.5 SCI Status Register 2 (SCIxS2) ......................................................................................179 11.2.6 SCI Control Register 3 (SCIxC3) ...................................................................................179 11.2.7 SCI Data Register (SCIxD) .............................................................................................180 14 Title Chapter 10 Timer/PWM (S08TPMV2) Chapter 11 MC9S08GT16A/GT8A Data Sheet, Rev. 1 Page Freescale Semiconductor ...
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... SPI Status Register (SPIS) ..............................................................................................196 12.4.5 SPI Data Register (SPID) ................................................................................................197 12.5 Functional Description ..................................................................................................................198 12.5.1 SPI Clock Formats ..........................................................................................................198 12.5.2 SPI Interrupts ..................................................................................................................201 12.5.3 Mode Fault Detection .....................................................................................................201 12.6 Initialization/Application Information ..........................................................................................201 Freescale Semiconductor Title Chapter 12 MC9S08GT16A/GT8A Data Sheet, Rev. 1 Page 15 ...
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... Byte Transfer Interrupt ....................................................................................................219 13.6.2 Address Detect Interrupt .................................................................................................219 13.6.3 Arbitration Lost Interrupt ................................................................................................219 Analog-to-Digital Converter (S08ATDV3) 14.1 Introduction ...................................................................................................................................223 14.1.1 Features ...........................................................................................................................223 14.1.2 Modes of Operation ........................................................................................................223 14.1.2.1 Stop Mode .....................................................................................................223 16 Title Chapter 13 Chapter 14 MC9S08GT16A/GT8A Data Sheet, Rev. 1 Page Freescale Semiconductor ...
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... BDC Breakpoint Match Register (BDCBKPT) ............................................253 15.4.2 System Background Debug Force Reset Register (SBDFR) ..........................................253 15.4.3 DBG Registers and Control Bits .....................................................................................254 15.4.3.1 Debug Comparator A High Register (DBGCAH) ........................................254 Freescale Semiconductor Title — ATD Reference Pins .........................................................................225 — ATD Supply Pins ............................................................................225 ...
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... A.10.2 Timer/PWM (TPM) Module Timing ..............................................................................278 A.10.3 SPI Timing ......................................................................................................................280 A.11 FLASH Specifications ...................................................................................................................283 Ordering Information and Mechanical Drawings B.1 Ordering Information ....................................................................................................................285 B.1.1 Device Numbering Scheme ............................................................................................285 B.2 Mechanical Drawings ....................................................................................................................285 18 Title Appendix A Electrical Characteristics Appendix B MC9S08GT16A/GT8A Data Sheet, Rev. 1 Page Freescale Semiconductor ...
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... Table 1-1. Devices in the MC9S08GT16A/GT8A Series Device FLASH MC9S08GT16A 16K MC9S08GT8A 8K 1.1.2 MCU Block Diagram This block diagrams show the structure of the MC9S08GT16A/GT8A MCUs. Freescale Semiconductor RAM TPM (1) 3-ch, (1) 2-ch, 16-bit (2) 2-ch, 16-bit 2K (2) 2-ch, 16-bit (1) 2-ch, (1) 1-ch, 16-bit 1K (1) 3-ch, (1) 2-ch, 16-bit ...
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... PTB0/ADP0 PTC7 PTC6 PTC5 PTC4 NOTE 5 SCL PTC3/SCL SDA PTC2/SDA RXD2 PTC1/RxD2 TXD2 PTC0/TxD2 CH1 PTD4/TPM2CH1 CH0 PTD3/TPM2CLK/TPM2CH0 CH0 PTD2/TPM1CH2 CH1 PTD1/TPM1CH1 CH2 PTD0/TPM1CLK/TPM1CH0 SPSCK PTE5/SPSCK MOSI PTE4/MOSI MISO PTE3/MISO SS PTE2/SS RXD1 PTE1/RxD1 TXD1 PTE0/TxD1 PTG3 PTG2/EXTAL PTG1/XTAL PTG0/BKGD/ Freescale Semiconductor ...
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... ICGOUT ÷ 2 ICGLCLK* CPU * ICGLCLK is the alternate BDC clock source for the MC9S08GT16A/GT8A. Figure 1-2. System Clock Distribution Diagram Freescale Semiconductor Table 1-2. Block Versions Module Analog-to-Digital Converter (ATD) Internal Clock Generator (ICG) Inter-Integrated Circuit (IIC) Keyboard Interrupt (KBI) Serial Peripheral Interface (SPI) ...
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... ICGLCLK — Development tools can select this internal self-clocked source (~ 8 MHz) to speed up BDC communications in systems where the bus clock is slow. • ICGERCLK — External reference clock can be selected as the real-time interrupt clock source. 22 MC9S08GT16A/GT8A Data Sheet, Rev. 1 Figure 1-2 shows a simplified clock Freescale Semiconductor ...
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... Device Pin Assignment RESET 1 PTC0/TxD2 2 PTC1/RxD2 3 PTC2/SDA 4 PTC3/SCL 5 PTC4 6 PTC5 7 PTC6 8 PTC7 9 PTE0/TxD1 10 11 PTE1/RxD1 IRQ 12 Figure 2-1. MC9S08GT16A/GT8A in 48-Pin QFN Package Freescale Semiconductor MC9S08GT16A/GT8A Data Sheet, Rev. 1 PTA1/KBIP1 36 PTA0/KBIP0 REFL V 33 REFH PTB7/ADP7 32 PTB6/ADP6 31 PTB5/ADP5 30 PTB4/ADP4 29 PTB3/ADP3 28 PTB2/ADP2 27 PTB1/ADP1 26 PTB0/ADP0 ...
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... Pins and Connections RESET PTC0/TxD2 PTC1/RxD2 PTC2/SDA PTC3/SCL PTC4 PTC5 PTC6 PTE0/TxD1 PTE1/RxD1 IRQ 11 Figure 2-2. MC9S08GT16A/GT8A in 44-Pin QFP Package MC9S08GT16A/GT8A Data Sheet, Rev. 1 PTA1/KBIP1 33 PTA0/KBIP0 REFL V 30 REFH PTB7/ADP7 29 PTB6/ADP6 28 PTB5/ADP5 27 PTB4/ADP4 26 PTB3/ADP3 25 PTB2/ADP2 24 PTB1/ADP1 23 Freescale Semiconductor ...
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... PTG0/BKGD/MS PTG1/XTAL PTG2/EXTAL PTC0/TxD2 PTC1/RXD2 PTC2/SDA PTC3/SCL PTE0/TxD1 PTE1/RxD1 PTE2/SS PTE3/MISO PTE4/MOSI PTE5/SPSCK PTD0/TPM1CLK/TPM1CH0 Figure 2-3. MC9S08GT16A/GT8A in 42-Pin SDIP Package Freescale Semiconductor V 1 DDAD V 2 SSAD RESET PTC4 IRQ MC9S08GT16A/GT8A Data Sheet, Rev. 1 Pins and Connections PTA7/KBIP7 42 PTA6/KBIP6 41 PTA5/KBIP5 40 PTA4/KBIP4 39 PTA3/KBIP3 ...
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... Pins and Connections RESET PTC0/TxD2 PTC1/RxD2 PTC2/SDA PTC3/SCL PTE0/TxD1 PTE1/RxD1 IRQ Figure 2-4. MC9S08GT16A/GT8A in 32-Pin QFN Package MC9S08GT16A/GT8A Data Sheet, Rev PTA4/KBIP4 23 V REFL 22 V REFH 21 PTB3/ADP3 20 PTB2/ADP2 19 PTB1/ADP1 18 PTB0/ADP0 17 PTD3/TPM2CLK/TPM2CH0 Freescale Semiconductor ...
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... INPUT PTG0/BKDG/MS PTG1/XTAL PTG2/EXTAL PTG3 NOTE NOTES: 1. Not required if using the internal oscillator option. 2. The 48-pin QFN has filters on RESET and IRQ are recommended for EMC-sensitive applications and systems. Freescale Semiconductor V REFH V DDAD MC9S08GT16A C BYAD 0.1 µF V SSAD V REFL ...
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... — Power and Voltage SSAD REFH REFL NOTE and V DDAD SSAD Chapter 9, “Internal Clock Generator (when used) and R S MC9S08GT16A/GT8A Data Sheet, Rev. 1 with the shortest traces possible. ), that Self_reset (S08ICGV4).” should be low-inductance F Freescale Semiconductor ...
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... Small capacitances from cables and the absolute value of the internal pullup device play almost no role in determining rise and fall times on the BKGD pin. Freescale Semiconductor , released, and sampled again approximately Self_reset MC9S08GT16A/GT8A Data Sheet, Rev ...
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... Chapter 10, “Timer/PWM (S08TPMV2)” Chapter 12, “Serial Peripheral Interface (S08SPIV3)” Chapter 11, “Serial Communications Interface (S08SCIV1)” Chapter 9, “Internal Clock Generator (S08ICGV4)” Chapter 15, “Development Support” MC9S08GT16A/GT8A Data Sheet, Rev. 1 Section 5.4.2, “IRQ — Figure 2-5 for Chapter 6, “Parallel 1 Reference Freescale Semiconductor ...
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... PTA3/KBIP3 I/O PTA4/KBIP4 I/O PTA5/KBIP5 I/O PTA6/KBIP6 I/O PTA7/KBIP7 I/O PTB0/ADP0 I/O PTB1/ADP1 I/O PTB2/ADP2 I/O Freescale Semiconductor Chapter 6, “Parallel Input/Output,” for details. Table 2-2. Signal Properties High Current Output Pull-Up 1 Pin Slew — — — — — — — ...
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... SWC Pullup enabled and slew rate disabled when SWC BDM function enabled. Pullup and slew rate disabled when XTAL SWC pin function. Pullup and slew rate disabled when EXTAL SWC pin function. SWC Not available on 32-pin, 42-, or 44-pin pkg Freescale Semiconductor ...
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... Active background mode is entered in any of five ways: • When the BKGD/MS pin is low at the rising edge of reset • When a BACKGROUND command is received through the BKGD pin • When a BGND instruction is executed • When encountering a BDC breakpoint • When encountering a DBG breakpoint Freescale Semiconductor MC9S08GT16A/GT8A Data Sheet, Rev ...
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... The active background mode is used to program a bootloader or user application program into the FLASH program memory before the MCU is operated in run mode for the first time. When the MC9S08GT16A/GT8A is shipped from the Freescale Semiconductor factory, the FLASH program memory is erased by default unless specifically noted so there is no program that could be executed in run mode until the FLASH memory is initially programmed ...
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... The stop2 mode provides very low standby power consumption and maintains the contents of RAM and the current state of all of the I/O pins. Stop2 can be entered only if the LVD circuit is not enabled in stop modes (either LVDE or LVDSE not set). Freescale Semiconductor Table 3-1. Stop Mode Behavior RAM ...
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... Exit by means of an asynchronous interrupt or the real-time interrupt will result in the MCU taking the appropriate interrupt vector. A separate self-clocked source (≈1 kHz) for the real-time interrupt allows a wakeup from stop2 or stop3 mode with no external components. When RTIS2:RTIS1:RTIS0 = 0:0:0, the real-time interrupt function 36 MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor ...
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... PPDC Peripherals, FLASH Stop3 Don’t Don’t Standby care care 1 Either ATD stop mode or power-down mode depending on the state of ATDPU. Freescale Semiconductor Chapter 15, “Development Support,” section of this data sheet. If ENBDM RAM ICG Standby Active Disabled RAM ICG Standby Standby Disabled MC9S08GT16A/GT8A Data Sheet, Rev ...
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... If the MCU is configured to go into stop2 or stop1 mode, the SPI module will be reset upon wake-up from stop and must be reinitialized. 38 Section 3.5.3, “Stop3 Mode,” for specific information on system MC9S08GT16A/GT8A Data Sheet, Rev. 1 Section 3.5.1, “Stop1 . No conversion Freescale Semiconductor ...
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... If the MCU is configured to go into stop2 or stop1 mode, the IIC module will be reset upon wake-up from stop and must be reinitialized. Voltage Regulator — The voltage regulator enters a low-power standby state when the MCU enters any of the stop modes unless the LVD is enabled in stop mode or BDM is enabled. Freescale Semiconductor MC9S08GT16A/GT8A Data Sheet, Rev. 1 Modes of Operation 39 ...
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... Modes of Operation 40 MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor ...
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... DIRECT PAGE REGISTERS RAM 2048 BYTES UNIMPLEMENTED 3968 BYTES HIGH PAGE REGISTERS UNIMPLEMENTED 42964 BYTES FLASH 16384 BYTES MC9S08GT16A Figure 4-1. MC9S08GT16A/GT8A Memory Map Freescale Semiconductor 0x0000 DIRECT PAGE REGISTERS 0x007F 0x0080 RAM 1024 BYTES Reserved 1024 BYTES 0x087F 0x0880 UNIMPLEMENTED UNIMPLEMENTED ...
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... TPM1 Channel 0 ICG Low Voltage Detect IRQ SWI Reset MC9S08GT16A/GT8A Data Sheet, Rev. 1 Chapter 5, “Resets, Vector Name Vrti Viic Vatd Vkeyboard Vsci2tx Vsci2rx Vsci2err Vsci1tx Vsci1rx Vsci1err Vspi Vtpm2ovf Vtpm2ch1 Vtpm2ch0 Vtpm1ovf Vtpm1ch2 Vtpm1ch1 Vtpm1ch0 Vicg Vlvd Virq Vswi Vreset Freescale Semiconductor ...
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... Cells that are not associated with named bits are shaded. A shaded cell with a 0 indicates this unused bit always reads Shaded cells with dashes indicate unused or reserved bit locations that could read 0s. Freescale Semiconductor can use the more efficient direct addressing mode which only and Table 4-4 the whole address in column one is shown in bold ...
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... SBR9 SBR3 SBR2 SBR1 WAKE ILT RWU ORIE NEIE FEIE SBR11 SBR10 SBR9 SBR3 SBR2 SBR1 WAKE ILT RWU ORIE NEIE FEIE Freescale Semiconductor Bit 0 PTAD0 PTBD0 PTED0 — SBR8 SBR0 PT SBK PF RAF PEIE Bit 0 SBR8 SBR0 PT SBK PF RAF PEIE Bit 0 ...
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... ICGC2 LOLRE 0x004A ICGS1 0x004B ICGS2 0 0x004C ICGFLTU 0 0x004D ICGFLTL 0x004E ICGTRM 0x004F Reserved 0 0x0050 ATDC ATDPU 0x0051 ATDSC CCF 0x0052 ATDRH Bit 7 0x0053 ATDRL Bit 7 Freescale Semiconductor SPE SPTIE MSTR 0 0 MODFEN SPPR2 SPPR1 SPPR0 0 SPTEF MODF TOIE CPWMS ...
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... ID11 ID10 ID9 ID3 ID2 ID1 0 RTIS2 RTIS1 LVDSE LVDE 0 PPDF PPDACK PDC — — — — — — Freescale Semiconductor Bit 0 — — RXAK — — PS0 Bit 8 Bit 0 Bit 8 Bit 0 0 Bit 8 Bit 0 0 Bit 8 Bit 0 — — Bit 0 0 BDFR — ...
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... This key mechanism can be accessed only through user code running in secure memory. (A security key cannot be entered directly through background debug commands.) This security key can be disabled completely by programming the KEYEN bit the security key is disabled, the Freescale Semiconductor 6 5 ...
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... FLASH erase and programming operations, in-application programming is also possible through other software-controlled communication paths. For a more detailed discussion of in-circuit and in-application programming, refer to the HCS08 Family Reference Manual, Volume I, Freescale Semiconductor document order number HCS08RMV1/D. 4.4.1 Features Features of the FLASH memory include: • ...
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... FLASH to be erased. For mass erase and blank check commands, the address can be any address in the FLASH memory. Whole pages of 512 bytes are the smallest blocks of FLASH that may be erased. Freescale Semiconductor = 1/f FCLK ...
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... The command sequence must be completed by clearing FCBEF to launch the command. burst programming. The FCDIV register must be initialized before using any FLASH commands. This must be done only once following a reset. 50 NOTE Figure 4 flowchart for executing all of the commands except for MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor ...
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... A5 through A0. A new row begins when addresses A5 through A0 are all zero. The first byte of a series of sequential bytes being programmed in burst mode will take the same amount of time to program as a byte programmed in standard mode. Subsequent bytes will program in the burst Freescale Semiconductor (Note 1) WRITE TO FCDIV ...
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... WRITE 1 TO FCBEF TO LAUNCH COMMAND (Note 2) AND CLEAR FCBEF YES FPVIO OR FACCERR ? NO YES NEW BURST COMMAND ? NO 0 FCCF ? 1 DONE MC9S08GT16A/GT8A Data Sheet, Rev. 1 Note 1: Required only once after reset. Note 2: Wait at least four bus cycles before checking FCBEF or FCCF. ERROR EXIT Freescale Semiconductor ...
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... For example, in order to protect the last 8192 bytes of memory (addresses 0xE000 through 0xFFFF), the FPS bits must be set to 1101 111 which results in the value 0xDFFF as the last address of unprotected memory. In addition to programming the FPS bits to the appropriate value, FPDIS (bit 0 of Freescale Semiconductor NVPROT)”). MC9S08GT16A/GT8A Data Sheet, Rev. 1 Memory Section 4.6.4, “ ...
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... NVOPT location which can be done at the same time the FLASH memory is programmed. The 1:0 state disengages security while the other three combinations engage security. Notice the erased state (1: A12 A11 A10 A9 A8 Figure 4-4. Block Protection Mechanism MC9S08GT16A/GT8A Data Sheet, Rev Freescale Semiconductor ...
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... Mass erase FLASH, if necessary. 3. Blank check FLASH. Provided FLASH is completely erased, security is disengaged until the next reset. To avoid returning to secure mode after the next reset, program NVOPT so SEC01:SEC00 = 1:0. Freescale Semiconductor MC9S08GT16A/GT8A Data Sheet, Rev. 1 Memory 55 ...
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... Table 4-7 ÷ ([DIV5:DIV0 FCLK Bus ÷ (8 × ([DIV5:DIV0 FCLK Bus MC9S08GT16A/GT8A Data Sheet, Rev. 1 Table 4-3 and Table 4-4 for the 2 1 DIV2 DIV1 DIV0 0 0 shows the appropriate values for PRDIV8 and Eqn. 4-1 Eqn. 4-2 Freescale Semiconductor 0 0 ...
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... No backdoor key access allowed user firmware writes an 8-byte value that matches the nonvolatile backdoor key (NVBACKKEY through NVBACKKEY+7, in that order), security is temporarily disengaged until the next MCU reset. Freescale Semiconductor Table 4-7. FLASH Clock Divider Settings DIV5:DIV0 f ...
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... During reset, the contents of the nonvolatile location NVPROT are copied from FLASH into FPROT. This register may be read at any time, but user program writes have no meaning or effect. Background debug commands can write to FPROT. 58 Description KEYACC Table 4-9. FCNFG Field Descriptions Description Section 4.5, MC9S08GT16A/GT8A Data Sheet, Rev “Security.” Freescale Semiconductor ...
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... FLASH Command Complete Flag — FCCF is set automatically when the command buffer is empty and no FCCF command is being processed. FCCF is cleared automatically when a new command is started (by writing 1 to FCBEF to register a command). Writing to FCCF has no meaning or effect. 0 Command in progress 1 All commands complete Freescale Semiconductor 5 4 FPS5 FPS4 FPS3 ...
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... FLASH Command Bits -- See FCMD[7:0] 60 Description Execution” for a detailed discussion of FLASH FCMD5 FCMD4 FCMD3 Table 4-12. FCMD Field Descriptions Description Table 4-13 for a description of FCMD[7:0]. MC9S08GT16A/GT8A Data Sheet, Rev. 1 Section 4.4.5, “Access Errors.” FACCERR Table 4-13. Refer FCMD2 FCMD1 FCMD0 Freescale Semiconductor ...
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... Mass erase (all FLASH) All other command codes are illegal and generate an access error not necessary to perform a blank check command after a mass erase operation. Blank check is required only as part of the security unlocking mechanism. Freescale Semiconductor Table 4-13. FLASH Commands FCMD Equate File Label ...
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... Memory 62 MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor ...
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... SP is forced to 0x00FF at reset. The MC9S08GT16A/GT8A has eight sources for reset: • Power-on reset (POR) • Low-voltage detect (LVD) Freescale Semiconductor MC9S08GT16A/GT8A Data Sheet, Rev. 1 Table 5-1) 63 ...
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... IRQ pin or a timer-overflow event. The debug module can also generate an SWI under certain circumstances. 64 selected. The reset pin is driven low for 34 Self_reset Section 5.7.4, “System Options Register MC9S08GT16A/GT8A Data Sheet, Rev. 1 (SOPT)” for Freescale Semiconductor ...
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... SP points at the next available location on the stack which is the address that is one less than the address where the CCR was saved. The PC value that is stacked is the address of the instruction in the main program that would have executed next if the interrupt had not occurred. Freescale Semiconductor NOTE MC9S08GT16A/GT8A Data Sheet, Rev. 1 Resets, Interrupts, and System Confi ...
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... ACCUMULATOR * INDEX REGISTER (LOW BYTE X) PROGRAM COUNTER HIGH PROGRAM COUNTER LOW TOWARD HIGHER ADDRESSES * High byte (H) of index register is not automatically stacked. Figure 5-1. Interrupt Stack Frame NOTE . DD MC9S08GT16A/GT8A Data Sheet, Rev AFTER INTERRUPT STACKING SP BEFORE THE INTERRUPT – Freescale Semiconductor ...
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... CCR the CPU will finish the current instruction, stack the PCL, PCH and CCR CPU registers, set the I bit, and then fetch the interrupt vector for the highest priority pending interrupt. Processing then continues in the interrupt service routine. Freescale Semiconductor MC9S08GT16A/GT8A Data Sheet, Rev. 1 Resets, Interrupts, and System Configuration ...
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... CH0IE TPM2 channel 0 TOIE TPM1 overflow CH2IE TPM1 channel 2 CH1IE TPM1 channel 1 CH0IE TPM1 channel 0 LOLRE/LOCRE ICG LVDIE Low-voltage detect IRQIE IRQ pin — Software interrupt COPE Watchdog timer LVDRE Low-voltage detect — External pin — Illegal opcode Freescale Semiconductor ...
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... In run and wait modes, only the external clock can be used as the RTI's clock source. In stop2 mode, only the internal RTI clock can be used. In stop3, either the external clock or internal RTI clock can be used. Freescale Semiconductor level. Both the POR bit and the LVD bit in SRS are set LVDL MC9S08GT16A/GT8A Data Sheet, Rev ...
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... Some control bits in the SOPT and SPMSC2 registers are related to modes of operation. Although brief descriptions of these bits are provided here, the related functions are discussed in greater detail in Chapter 3, “Modes of Operation.” 70 Chapter 4, “Memory” of this data sheet for the absolute MC9S08GT16A/GT8A Data Sheet, Rev. 1 (SRTISC),” for detailed Freescale Semiconductor ...
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... The IRQEDG control bit determines the polarity of edges and levels that are detected as interrupt request events. See Section 5.4.2.2, “Edge and Level 0 IRQ event on falling edges or rising edges only. 1 IRQ event on falling edges and low levels or on rising edges and high levels. Freescale Semiconductor IRQF ...
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... Reset caused by an illegal opcode COP ILOP Writing any value to SIMRS address clears COP watchdog timer (1) (1) Note Note Figure 5-3. System Reset Status (SRS) Table 5-3. SRS Field Descriptions Description MC9S08GT16A/GT8A Data Sheet, Rev ILAD ICG LVD (1) 0 Note 0 Freescale Semiconductor ...
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... Figure 5-4. System Background Debug Force Reset Register (SBDFR) Field 0 Background Debug Force Reset — A serial background mode command such as WRITE_BYTE allows an BDFR external debug host to force a target system reset. Writing 1 to this bit forces an MCU reset. This bit cannot be written from a user program. Freescale Semiconductor Description ...
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... BKGD/MS. When the bit is clear, the pin will function as PTG0, which is an output-only general-purpose I/O. This pin always defaults to BKGD/MS function after any reset. 0 BKGD pin disabled. 1 BKGD pin enabled STOPE Table 5-5. SOPT Field Descriptions Description 13 cycles of BUSCLK). 18 cycles of BUSCLK). MC9S08GT16A/GT8A Data Sheet, Rev BKGDPE Freescale Semiconductor ...
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... Unimplemented or Reserved Figure 5-7. System Device Identification Register Low (SDIDL) Field 7:0 Part Identification Number — Each derivative in the HCS08 Family has a unique identification number. The ID[7:0] MC9S08GT16A/GT8A is hard coded to the value 0x00D. See also ID bits in Freescale Semiconductor ID11 Table 5-6 ...
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... Characteristics,” for the tolerance on these values. MC9S08GT16A/GT8A Data Sheet, Rev RTIS2 RTIS RTIS External Clock Source Period = t ext Disable periodic wakeup timer t x 256 ext t x 1024 2048 4096 8192 ext t x 16384 ext t x 32768 ex Table A-11 for details. Freescale Semiconductor ...
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... Low-voltage detect disabled during stop mode. 1 Low-voltage detect enabled during stop mode. 2 Low-Voltage Detect Enable — This read/write bit enables low-voltage detect logic and qualifies the operation LVDE of other bits in this register. 0 LVD logic disabled. 1 LVD logic enabled. Freescale Semiconductor LVDRE LVDSE LVDIE (1) ...
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... U = Unaffected by reset transitions below the trip point or after reset and V Supply Table 5-11. SPMSC2 Field Descriptions Description = V ). LVD LVDL = V ). LVD LVDH = V ). LVW LVWL = V ). LVW LVWH MC9S08GT16A/GT8A Data Sheet, Rev PPDF PDC PPDACK already below V Supply ). LVD LVW Freescale Semiconductor 0 PPDC LVW ). ...
Page 79
... A total of 39 general-purpose I/O pins in six ports (PTG0 is output only) • High-current drivers on port C pins • Hysteresis input buffers • Software-controlled pullups on each input pin • Software-controlled slew rate output buffers • Eight port A pins shared with KBI Freescale Semiconductor NOTE MC9S08GT16A/GT8A Data Sheet, Rev ...
Page 80
... Eight high-current port C pins shared with SCI2 and IIC • Five port D pins shared with TPM1 and TPM2 • Six port E pins shared with SCI1 and SPI • Four port G pins shared with EXTAL, XTAL, and BKGD/MS 80 MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor ...
Page 81
... IRQ does not have a clamp diode to VDD. IRQ should not be driven above VDD. 4. Pin contains integrated pullup device. 5. High current drive 6. Pins PTA[7:4] contain both pullup and pulldown devices. Pulldown available when KBI enabled (KBIPn = 1). Figure 6-1. Block Diagram Highlighting Parallel Input/Output Pins Freescale Semiconductor 8-BIT KEYBOARD INTERRUPT (KBI) BKGD 10-BIT ...
Page 82
... ADP3 Figure 6-3. Port B Pin Names MC9S08GT16A/GT8A Data Sheet, Rev. 1 Chapter Bit 0 PTA2/ PTA1/ PTA0/ KBIP2 KBIP1 KBIP0 Section 6.3, “Parallel Chapter 7, “Keyboard Interrupt Bit 0 PTB2/ PTB1/ PTB0/ ADP2 ADP1 ADP0 Section 6.3, “Parallel (S08ATDV3),” for more information Freescale Semiconductor ...
Page 83
... Refer to information about using PTD4–PTD3 as timer pins. The TPM1 module can be configured to use PTD2–PTD0 as either input capture, output compare, PWM, or external clock input pins (PTD0 only). Refer to information about using PTD2–PTD0 as timer pins. Freescale Semiconductor PTC6 ...
Page 84
... Chapter 15, “Development MC9S08GT16A/GT8A Data Sheet, Rev Bit 0 PTE2/ PTE1/ PTE0/ SS RxD1 TxD1 Section 6.3, “Parallel (S08SCIV1)” Bit 0 PTG2/ PTG1/ PTG0/ EXTAL XTAL BKGD/MS Section 6.3, “Parallel Operation,”, Chapter 5, “Resets, Support,” for more information Freescale Semiconductor for for ...
Page 85
... Not all peripheral modules’ outputs have slew rate control; refer to Chapter 2, “Pins and rate control. Freescale Semiconductor (S08ICGV4),” for more information about using these pins Connections,” for more information about which pins have slew MC9S08GT16A/GT8A Data Sheet, Rev. 1 ...
Page 86
... If the KBI takes control of a port A pin, the corresponding PTASE bit is ignored since the pin functions as an input. As long as PTADD is 0, the PTAPE controls the pullup enable for the KBI function. Reads of PTAD will return the logic value of the corresponding pin, provided PTADD MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor ...
Page 87
... When any of bits 7 through 4 of port A are enabled as KBI inputs and are configured to detect rising edges/high levels, the pullup enable bits enable pulldown rather than pullup devices. 0 Internal pullup device disabled. 1 Internal pullup device enabled. Freescale Semiconductor PTAD5 ...
Page 88
... Output driver enabled for port A bit n and PTAD reads return the contents of PTADn PTASE5 PTASE4 PTASE3 Table 6-3. PTASE Field Descriptions Description PTADD5 PTADD4 PTADD3 Table 6-4. PTADD Field Descriptions Description MC9S08GT16A/GT8A Data Sheet, Rev PTASE2 PTASE1 PTASE0 PTADD2 PTADD1 PTADD0 Freescale Semiconductor ...
Page 89
... Pullup Enable for Port B Bits — For port B pins that are inputs, these read/write control bits determine whether PTBPE[7:0] internal pullup devices are enabled. For port B pins that are configured as outputs, these bits are ignored and the internal pullup devices are disabled. 0 Internal pullup device disabled. 1 Internal pullup device enabled. Freescale Semiconductor PTBD5 PTBD4 ...
Page 90
... Output driver enabled for port B bit n and PTBD reads return the contents of PTBDn PTBSE5 PTBSE4 PTBSE3 Table 6-7. PTBSE Field Descriptions Description PTBDD5 PTBDD4 PTBDD3 Table 6-8. PTBDD Field Descriptions Description MC9S08GT16A/GT8A Data Sheet, Rev PTBSE2 PTBSE1 PTBSE0 PTBDD2 PTBDD1 PTBDD0 Freescale Semiconductor ...
Page 91
... Writes are latched into all bits of this register. For port C pins that are configured as outputs, the logic level is driven out the corresponding MCU pin. Reset forces PTCD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures all port pins as high-impedance inputs with pullups disabled. Freescale Semiconductor ...
Page 92
... PTCPE4 PTCPE3 Table 6-10. PTCPE Field Descriptions Description PTCSE5 PTCSE4 PTCSE3 Table 6-11. PTCSE Field Descriptions Description PTCDD5 PTCDD4 PTCDD3 Table 6-12. PTCDD Field Descriptions Description MC9S08GT16A/GT8A Data Sheet, Rev PTCPE2 PTCPE1 PTCPE0 PTCSE2 PTCSE1 PTCSE0 PTCDD2 PTCDD1 PTCDD0 Freescale Semiconductor ...
Page 93
... Pullup Enable for Port D Bits — For port D pins that are inputs, these read/write control bits determine whether PTDPE[4:0] internal pullup devices are enabled. For port D pins that are configured as outputs, these bits are ignored and the internal pullup devices are disabled. 0 Internal pullup device disabled. 1 Internal pullup device enabled. Freescale Semiconductor PTDD4 ...
Page 94
... Output driver enabled for port D bit n and PTDD reads return the contents of PTDDn PTDSE4 PTDSE3 Table 6-15. PTDSE Field Descriptions Description PTDDD4 PTDDD3 Table 6-16. PTDDD Field Descriptions Description MC9S08GT16A/GT8A Data Sheet, Rev PTDSE2 PTDSE1 PTDSE0 PTDDD2 PTDDD1 PTDDD0 Freescale Semiconductor ...
Page 95
... Writes are latched into all bits in this register. For port E pins that are configured as outputs, the logic level is driven out the corresponding MCU pin. Reset forces PTED to all 0s, but these 0s are not driven out the corresponding pins because reset also configures all port pins as high-impedance inputs with pullups disabled. Freescale Semiconductor ...
Page 96
... PTEPE4 PTEPE3 Table 6-18. PTEPE Field Descriptions Description PTESE5 PTESE4 PTESE3 Table 6-19. PTESE Field Descriptions Description PTEDD5 PTEDD4 PTEDD3 Table 6-20. PTEDD Field Descriptions Description MC9S08GT16A/GT8A Data Sheet, Rev PTEPE2 PTEPE1 PTEPE0 PTESE2 PTESE1 PTESE0 PTEDD2 PTEDD1 PTEDD0 Freescale Semiconductor ...
Page 97
... Pullup Enable for Port G Bits — For port G pins that are inputs, these read/write control bits determine whether PTGPE[3:0] internal pullup devices are enabled. For port G pins that are configured as outputs, these bits are ignored and the internal pullup devices are disabled. 0 Internal pullup device disabled. 1 Internal pullup device enabled. Freescale Semiconductor PTGD3 ...
Page 98
... Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port G bit n and PTGD reads return the contents of PTGDn PTGSE3 Table 6-23. PTGSE Field Descriptions Description PTGDD3 Table 6-24. PTGDD Field Descriptions Description MC9S08GT16A/GT8A Data Sheet, Rev PTGSE2 PTGSE1 PTGSE0 PTGDD0 PTGDD2 PTGDD1 (1) Note Freescale Semiconductor ...
Page 99
... Four falling-edge/low-level or rising-edge/high-level sensitive — Choice of edge-only or edge-and-level sensitivity — Common interrupt flag and interrupt enable control — Capable of waking up the MCU from stop3 or wait mode Freescale Semiconductor Connections,” for more information about the logic and hardware aspects PTA6/ PTA5/ ...
Page 100
... PTB0/ADP0 PTC7 PTC6 PTC5 PTC4 NOTE 5 SCL PTC3/SCL SDA PTC2/SDA RXD2 PTC1/RxD2 TXD2 PTC0/TxD2 CH1 PTD4/TPM2CH1 CH0 PTD3/TPM2CLK/TPM2CH0 CH0 PTD2/TPM1CH2 CH1 PTD1/TPM1CH1 CH2 PTD0/TPM1CLK/TPM1CH0 SPSCK PTE5/SPSCK MOSI PTE4/MOSI MISO PTE3/MISO SS PTE2/SS RXD1 PTE1/RxD1 TXD1 PTE0/TxD1 PTG3 PTG2/EXTAL PTG1/XTAL PTG0/BKGD/MS Freescale Semiconductor ...
Page 101
... Refer to the direct-page register summary in the Memory chapter of this data sheet for the absolute address assignments for all KBI registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. Freescale Semiconductor V DD CLR ...
Page 102
... Rising edges-only or rising edges and high levels (KBEDGn = 1) • Falling edges-only or falling edges and low levels (KBEDGn = 0) 0 Edge-only detection 1 Edge-and-level detection 102 KBF KBEDG5 KBEDG4 Description MC9S08GT16A/GT8A Data Sheet, Rev KBIE KBIMOD KBACK Freescale Semiconductor ...
Page 103
... When the MCU enters stop mode, the synchronous edge-detection logic is bypassed (because clocks are stopped). In stop mode, KBI inputs act as asynchronous level-sensitive inputs so they can wake the MCU from stop mode. Freescale Semiconductor 5 4 KBIPE5 ...
Page 104
... When KBIMOD = 0 (selecting edge-only operation), KBF is always cleared by writing 1 to KBACK. When KBIMOD = 1 (selecting edge-and-level operation), KBF cannot be cleared as long as any keyboard input is at its asserted level. 104 MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor ...
Page 105
... This section provides summary information about the registers, addressing modes, and instruction set of the CPU of the HCS08 Family. For a more detailed discussion, refer to the HCS08 Family Reference Manual, volume 1, Freescale Semiconductor document order number HCS08RMV1/D. The HCS08 CPU is fully source- and object-code-compatible with the M68HC08 CPU. Several instructions and enhanced addressing modes were added to improve C compiler effi ...
Page 106
... For compatibility with the earlier M68HC05 Family forced to 0x00 during reset. Reset has no effect on the contents of X. 106 7 0 ACCUMULATOR A 16-BIT INDEX REGISTER H:X INDEX REGISTER (LOW STACK POINTER PROGRAM COUNTER CCR CARRY ZERO NEGATIVE INTERRUPT MASK HALF-CARRY (FROM BIT 3) TWO’S COMPLEMENT OVERFLOW Figure 8-1. CPU Registers MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor ...
Page 107
... For a more detailed explanation of how each instruction sets the CCR bits, refer to the HCS08 Family Reference Manual, volume 1, Freescale Semiconductor document order number HCS08RMv1. Freescale Semiconductor MC9S08GT16A/GT8A Data Sheet, Rev. 1 Central Processor Unit (S08CPUV2) ...
Page 108
... No carry out of bit 7 1 Carry out of bit 7 108 CCR CARRY ZERO NEGATIVE INTERRUPT MASK HALF-CARRY (FROM BIT 3) TWO’S COMPLEMENT OVERFLOW Figure 8-2. Condition Code Register Table 8-1. CCR Register Field Descriptions Description MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor ...
Page 109
... This is faster and more memory efficient than specifying a complete 16-bit address for the operand. Freescale Semiconductor MC9S08GT16A/GT8A Data Sheet, Rev. 1 Central Processor Unit (S08CPUV2) ...
Page 110
... SP-Relative, 8-Bit Offset (SP1) This variation of indexed addressing uses the 16-bit value in the stack pointer (SP) plus an unsigned 8-bit offset included in the instruction as the address of the operand needed to complete the instruction. 110 MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor ...
Page 111
... After the CCR contents are pushed onto the stack, the I bit in the CCR is set to prevent other interrupts while in the interrupt service routine. Although it is possible to clear the I bit with an instruction in the Freescale Semiconductor Resets, Interrupts, and System Configuration MC9S08GT16A/GT8A Data Sheet, Rev. 1 ...
Page 112
... MCU even stop mode. Recovery from stop mode depends on the particular HCS08 and whether the oscillator was stopped in stop mode. Refer to the Modes of Operation 112 chapter for more details. MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor ...
Page 113
... Software-based breakpoints can be set by replacing an opcode at the desired breakpoint address with the BGND opcode. When the program reaches this breakpoint address, the CPU is forced to active background mode rather than continuing the user program. Freescale Semiconductor MC9S08GT16A/GT8A Data Sheet, Rev. 1 Central Processor Unit (S08CPUV2) ...
Page 114
... Condition code register (CCR) bits V = Two’s complement overflow indicator, bit Half carry, bit Interrupt mask, bit Negative indicator, bit Zero indicator, bit Carry/borrow, bit 0 (carry out of bit 7) CCR activity notation – = Bit not affected 114 MC9S08GT16A/GT8A Data Sheet, Rev. 1 Table 8-2. Freescale Semiconductor ...
Page 115
... Address modes INH = Inherent (no operands) IMM = 8-bit or 16-bit immediate DIR = 8-bit direct EXT = 16-bit extended Freescale Semiconductor MC9S08GT16A/GT8A Data Sheet, Rev. 1 Central Processor Unit (S08CPUV2) 115 ...
Page 116
... SP2 9ED4 ee ff SP1 9EE4 ff DIR 38 dd INH 48 INH 58 ↕ – – ↕ ↕ ↕ IX1 SP1 9E68 ff DIR 37 dd INH 47 INH 57 ↕ – – ↕ ↕ ↕ IX1 SP1 9E67 ff – – – – – – REL 24 rr Freescale Semiconductor ...
Page 117
... Branch if Minus Branch if Interrupt Mask BMS rel Set BNE rel Branch if Not Equal BPL rel Branch if Plus BRA rel Branch Always Freescale Semiconductor Description Mn ← 0 Branch if ( Branch if ( Branch if (N ⊕ Waits For and Processes BDM Commands Until GO, TRACE1, or TAGGO Branch if ( ⊕ ...
Page 118
... B1 dd EXT IX2 ↕ ↕ ↕ ↕ – – IX1 SP2 9ED1 ee ff SP1 9EE1 ff DIR 33 dd INH 43 INH 53 ↕ ↕ 0 – – 1 IX1 SP1 9E63 ff EXT IMM 65 jj ↕ ↕ ↕ ↕ – – DIR 75 dd SP1 9EF3 ff Freescale Semiconductor ...
Page 119
... LDA oprx8,SP LDHX #opr16i LDHX opr8a LDHX opr16a Load Index Register (H:X) LDHX ,X from Memory LDHX oprx16,X LDHX oprx8,X LDHX oprx8,SP Freescale Semiconductor Description (X) – (M) (CCR Updated But Operands Not Changed) (A) 10 Decrement Branch if (result) ≠ 0 DBNZX Affects X Not H M ← (M) – 0x01 A ← ...
Page 120
... INH 89 – – – – – – INH 86 – – – – – – INH 8A – – – – – – INH 88 DIR 39 dd INH 49 INH 59 ↕ ↕ ↕ ↕ – – IX1 SP1 9E69 ff Freescale Semiconductor ...
Page 121
... SUB opr8a SUB opr16a SUB oprx16,X Subtract SUB oprx8,X SUB ,X SUB oprx16,SP SUB oprx8,SP SWI Software Interrupt Freescale Semiconductor Description ← 0xFF (High Byte Not Affected) SP ← (SP) + 0x0001; Pull (CCR) SP ← (SP) + 0x0001; Pull (A) SP ← (SP) + 0x0001; Pull (X) SP ← (SP) + 0x0001; Pull (PCH) SP ← ...
Page 122
... DIR 3D dd INH 4D INH 5D ↕ ↕ 0 – – – IX1 SP1 9E6D ff – – – – – – INH 95 – – – – – – INH 9F – – – – – – INH 94 – – 0 – – – INH 8F Freescale Semiconductor ...
Page 123
... IMM Immediate IX Indexed, No Offset DIR Direct IX1 Indexed, 8-Bit Offset EXT Extended IX2 Indexed, 16-Bit Offset DD DIR to DIR IMD IMM to DIR IX+D IX+ to DIR DIX+ DIR to IX+ Freescale Semiconductor Table 8-3. Opcode Map (Sheet Read-Modify-Write Control NEGX NEG NEG RTI 1 INH ...
Page 124
... IX 4 IX2 3 IX1 4 SP2 3 9EDF 5 9EEF STX 4 SP2 3 Prebyte (9E) and Opcode in 9E60 6 HCS08 Cycles Hexadecimal NEG Instruction Mnemonic Addressing Mode Number of Bytes 3 SP1 Freescale Semiconductor 4 SUB SP1 4 CMP SP1 4 SBC SP1 4 9EF3 6 CPX CPHX SP1 3 SP1 4 AND SP1 4 BIT SP1 4 LDA ...
Page 125
... ICGLCLK is the alternate BDC clock source for the MC9S08GT16A/GT8A. Figure 9-1. System Clock Distribution Diagram Freescale Semiconductor programs a factory trim value for ICGTRM into the FLASH location $FFBE (NVICGTRM). Leaving this address for the ICGTRM value also allows debugger and programmer vendors to perform a manual trim operation and store the resultant ICGTRM value into NVICGTRM for users to access at a later time ...
Page 126
... PTB0/ADP0 PTC7 PTC6 PTC5 PTC4 NOTE 5 SCL PTC3/SCL SDA PTC2/SDA RXD2 PTC1/RxD2 TXD2 PTC0/TxD2 CH1 PTD4/TPM2CH1 CH0 PTD3/TPM2CLK/TPM2CH0 CH0 PTD2/TPM1CH2 CH1 PTD1/TPM1CH1 CH2 PTD0/TPM1CLK/TPM1CH0 SPSCK PTE5/SPSCK MOSI PTE4/MOSI MISO PTE3/MISO SS PTE2/SS RXD1 PTE1/RxD1 TXD1 PTE0/TxD1 PTG3 PTG2/EXTAL PTG1/XTAL PTG0/BKGD/MS Freescale Semiconductor ...
Page 127
... Frequency-locked loop (FLL) generates 8 MHz to 40 MHz (for bus rates MHz) — Uses external or internal clock as reference frequency • Automatic lockout of non-running clock sources • Reset or interrupt on loss of clock or loss of FLL lock Freescale Semiconductor Section 9.5, “Initialization/Application MC9S08GT16A/GT8A Data Sheet, Rev. 1 Internal Clock Generator (S08ICGV4) 127 ...
Page 128
... The FLL DCO frequency is off target and the FLL is adjusting the DCO to match the target frequency. — FLL engaged external locked is a state which occurs when the FLL detects that the DCO is locked to a multiple of the internal reference. 128 MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor ...
Page 129
... XTAL — Oscillator Output If upon the first write to ICGC1, either the FEE mode or FBE mode is selected, this pin functions as the output of the oscillator circuit. If upon the first write to ICGC1, either the FEI mode or SCM mode is Freescale Semiconductor ICG SELECT ICGERCLK ...
Page 130
... Recommended component values are listed in the Figure 9-5. External Frequency Reference Connection 130 ICG EXTAL V SS CLOCK INPUT Figure 9-4. External Clock Connections ICG EXTAL CRYSTAL OR RESONATOR MC9S08GT16A/GT8A Data Sheet, Rev. 1 Figure 9-4. XTAL NOT CONNECTED Electrical Characteristics chapter. XTAL R S Freescale Semiconductor ...
Page 131
... The CLKS bits are writable at any time, unless the first write after a reset was CLKS = 0X, the CLKS bits cannot be written to 1X until after the next reset (because the EXTAL pin was not reserved). Freescale Semiconductor Memory chapter of this data sheet for the absolute address ...
Page 132
... Oscillator disabled when ICG is in off mode unless ENABLE is high, CLKS = 10, and REFST = 1. 1 Oscillator enabled when ICG is in off mode, CLKS = 1X and REFST = 1. 1 Loss of Clock Disable LOCD 0 Loss of clock detection enabled. 1 Loss of clock detection disabled. 132 Description MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor ...
Page 133
... Writes to the RFD bits will not take effect if a previous write is not complete. 000 Division factor = 1 001 Division factor = 2 010 Division factor = 4 011 Division factor = 8 100 Division factor = 16 101 Division factor = 32 110 Division factor = 64 111 Division factor = 128 Freescale Semiconductor MFD LOCRE Figure 9-7 ...
Page 134
... Writing a logic 0 to ICGIF has no effect ICG interrupt request is pending ICG interrupt request is pending. 134 REFST LOLS LOCK Figure 9-8. ICG Status Register 1 (ICGS1) Description MC9S08GT16A/GT8A Data Sheet, Rev LOCS ERCS ICGIF Freescale Semiconductor ...
Page 135
... FLT read only except when the CLKS bits are programmed to self-clocked mode (CLKS = 00). In self-clocked mode, any write to ICGFLTU updates the current 12-bit filter value. Writes to the ICGFLTU register will not affect FLT if a previous latch sequence is not complete. Freescale Semiconductor ...
Page 136
... When using the FLL, configure the ICG so that the frequency of ICGDCLK does not exceed its maximum value to ensure proper MCU operation. 136 FLT Description TRIM Figure 9-12. ICG Trim Register (ICGTRM) Description MC9S08GT16A/GT8A Data Sheet, Rev Freescale Semiconductor ...
Page 137
... FLL engaged external (either by programming CLKS or due to a loss of external reference clock), f will maintain the previous frequency, but ICGOUT will double if the FLL was unlocked. ICGDCLK If this mode is entered from off mode, f Freescale Semiconductor will default to f ICGDCLK Self_reset will maintain the previous frequency.If this mode ...
Page 138
... DIGITAL DIGITALLY CONTROLLED LOOP OSCILLATOR FILTER FLL ANALOG CLKST PULSE COUNTER RESET AND INTERRUPT CONTROL LOCS ERCS LOCD ICGIF LOLRE MC9S08GT16A/GT8A Data Sheet, Rev. 1 RFD REDUCED ICGOUT FREQUENCY DIVIDER (R) ICGDCLK 1x 2x FREQUENCY- LOCKED LOOP (FLL) ICG2DCLK IRQ RESET LOCRE Freescale Semiconductor ...
Page 139
... MHz in FEE mode to prevent over-clocking the DCO. The minimum multiplier for the FLL, from operational limit of the DCO, the reference clock cannot be any faster than 10 MHz. Freescale Semiconductor or less than the minimum n unlock (max) and greater than n ...
Page 140
... If ∆n goes outside this range unexpectedly, unlock MC9S08GT16A/GT8A Data Sheet, Rev less than lock / (2×R) This ICGDCLK (max) and greater lock /R. In FLL engaged external ICGDCLK (max). After the FLL has locked, ∆n must Freescale Semiconductor ...
Page 141
... If ENABLE is high (waiting for external crystal start-up after exiting stop). 2 DCO clock will not be monitored until DCOS = 1 upon entering SCM from off or FLL bypassed external mode. Freescale Semiconductor and f , respectively, the LOCS status bit will be set to indicate the error. LOD ...
Page 142
... SCM ICGDCLK/R — ICGDCLK/R — DCOS = 0 or ICGDCLK/R — ICGDCLK/R DCOS = 1 ICGDCLK/R — ERCS = 1 — ERCS = 1 and 3 DCOS = 1 ERCS = 1 and (2) DCOS = 1 Freescale Semiconductor Reason CLKS1 ≠ CLKST — ERCS = 0 — DCOS = 0 ERCS = 0 ERCS = 0 — ERCS = 0 — LOCS = 1 & ERCS = 1 — — ...
Page 143
... ICG. For some applications, the serial communication link may dictate the accuracy of the clock reference. For other applications, lowest power consumption may be the chief clock consideration. Still others may have lowest cost as the primary goal. The ICG allows great flexibility in choosing which is best for any application. Freescale Semiconductor Table Table 9-12). ...
Page 144
... MC9S08GT16A/GT8A Data Sheet, Rev. 1 Clock Reference Source = External < 20 MHz Bus range ≤ 8 MHz when crystal or resonator is P Note NA Typical f ICGOUT immediately after reset NA 64 Typical f = 243 kHz IRG . Division Factor (R) ÷1 ÷2 ÷4 ÷8 ÷16 Freescale Semiconductor = 8 MHz ...
Page 145
... This is read only; should read DCOS = 1 before performing any time critical tasks ICGFLTLU/L = $xx Only needed in self-clocked mode; FLT will be adjusted by loop to give 8.38 MHz DCO clock Bits 15:12 unused 0000 Freescale Semiconductor Table 9-12. MFD and RFD Decode Table 101 110 111 = ...
Page 146
... CHECK NO FLL LOCK STATUS. LOCK = 1? YES CONTINUE NOTE: THIS WILL REQUIRE THE OSCILLATOR TO START AND STABILIZE. ACTUAL TIME IS DEPENDENT ON CRYSTAL /RESONATOR AND EXTERNAL CIRCUITRY. MC9S08GT16A/GT8A Data Sheet, Rev. 1 RECOVERY FROM STOP OSCSTEN = 0 CHECK NO FLL LOCK STATUS. LOCK = 1? YES CONTINUE Freescale Semiconductor ...
Page 147
... This is read only except for clearing interrupt flag ICGS2 = $xx This is read only. Should read DCOS before performing any time critical tasks ICGFLTLU/L = $xx Not used in this example ICGTRM Not used in this example Freescale Semiconductor = 4.00 MHz ext ext Configures oscillator for low power Configures oscillator for high-frequency range ...
Page 148
... FLL LOCK STATUS Figure 9-15. ICG Initialization and Stop Recovery for Example #2 148 RECOVERY RESET FROM STOP INITIALIZE ICG SERVICE INTERRUPT ICGC1 = $7A ICGC2 = $30 SOURCE (f CHECK NO LOCK = 1? FLL LOCK STATUS LOCK = 1? YES CONTINUE CONTINUE MC9S08GT16A/GT8A Data Sheet, Rev MHz) Bus CHECK NO YES Freescale Semiconductor ...
Page 149
... This is read only except for clearing interrupt flag ICGS2 = $xx This is read only; good idea to read this before performing time critical operations ICGFLTLU/L = $xx Not used in this example Freescale Semiconductor / 64, f IRG IRG Configures oscillator for low power Configures oscillator for low-frequency range; FLL prescale factor is 64 Oscillator using crystal or resonator requested (bit is really a don’ ...
Page 150
... Only need to write when trimming internal oscillator; done in separate operation (see example #4) NO YES NOTE: THIS WILL REQUIRE THE INTERAL REFERENCE CLOCK TO START AND STABILIZE. MC9S08GT16A/GT8A Data Sheet, Rev. 1 RECOVERY FROM STOP CHECK NO FLL LOCK STATUS. LOCK = 1? YES CONTINUE Freescale Semiconductor ...
Page 151
... If the intended bus frequency is near the maximum allowed for the device recommended to trim using a reduction divisor (R) twice the final value. After the trim procedure is complete, the reduction divisor can be restored. This will prevent accidental overshoot of the maximum clock frequency. Freescale Semiconductor START TRIM PROCEDURE ICGTRM = $80 ...
Page 152
... Internal Clock Generator (S08ICGV4) 152 MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor ...
Page 153
... Prescale taps for divide 16, 32, 64, or 128 • 16-bit free-running or up/down (CPWM) count operation • 16-bit modulus register to control counter range • Timer system enable • One interrupt per channel plus terminal count interrupt Freescale Semiconductor MC9S08GT16A/GT8A Data Sheet, Rev. 1 153 ...
Page 154
... PTB0/ADP0 PTC7 PTC6 PTC5 PTC4 NOTE 5 SCL PTC3/SCL SDA PTC2/SDA RXD2 PTC1/RxD2 TXD2 PTC0/TxD2 CH1 PTD4/TPM2CH1 CH0 PTD3/TPM2CLK/TPM2CH0 CH0 PTD2/TPM1CH2 CH1 PTD1/TPM1CH1 CH2 PTD0/TPM1CLK/TPM1CH0 SPSCK PTE5/SPSCK MOSI PTE4/MOSI MISO PTE3/MISO SS PTE2/SS RXD1 PTE1/RxD1 TXD1 PTE0/TxD1 PTG3 PTG2/EXTAL PTG1/XTAL PTG0/BKGD/MS Freescale Semiconductor ...
Page 155
... Set, clear, or toggle output compare action — Selectable polarity on PWM outputs 10.1.3 Block Diagram Figure 10-2 shows the structure of a TPM. Some MCUs include more than one TPM, with various numbers of channels. Freescale Semiconductor MC9S08GT16A/GT8A Data Sheet, Rev. 1 Timer/Pulse-Width Modulator (S08TPMV2) 155 ...
Page 156
... MSnB Figure 10-2. TPM Block Diagram MC9S08GT16A/GT8A Data Sheet, Rev. 1 PRESCALE AND SELECT DIVIDE 16, 32, 64, or 128 PS2 PS1 PS0 TOF INTERRUPT LOGIC TOIE PORT TPMxCH0 LOGIC INTERRUPT LOGIC TPMxCH1 PORT LOGIC INTERRUPT LOGIC TPMxCHn PORT LOGIC INTERRUPT LOGIC Freescale Semiconductor ...
Page 157
... A 16-bit channel value register (TPMxCnVH:TPMxCnVL) Refer to the direct-page register summary in the assignments for all TPM registers. This section refers to registers and control bits only by their names. A Freescale Semiconductor Pins and Connections Memory chapter of this data sheet for the absolute address MC9S08GT16A/GT8A Data Sheet, Rev ...
Page 158
... This prescaler is located after any clock source synchronization or clock source selection affects whatever clock source is selected to drive the TPM system. 158 CPWMS CLKSB CLKSA Description Table 10-2, this 2-bit field is used to disable the TPM system or select one MC9S08GT16A/GT8A Data Sheet, Rev PS2 PS1 PS0 Freescale Semiconductor ...
Page 159
... Bit Reset 0 0 Figure 10-4. Timer x Counter Register High (TPMxCNTH) Freescale Semiconductor Table 10-2. TPM Clock Source Selection TPM Clock Source to Prescaler Input No clock selected (TPMx disabled) Bus rate clock (BUSCLK) Fixed system clock (XCLK) External source (TPMxCLK) Table 10-3. Prescale Divisor Selection ...
Page 160
... An alternative approach is to reset the TPM counter before writing to the TPM modulo registers to avoid confusion about when the first counter overflow will occur. 160 Any write to TPMxCNTL clears the 16-bit counter MC9S08GT16A/GT8A Data Sheet, Rev Bit Bit Bit Freescale Semiconductor ...
Page 161
... Setting ELSnB:ELSnA to 0:0 configures the related timer pin as a general-purpose I/O pin unrelated to any timer channel functions. This function is typically used to temporarily disable an input capture channel or to make the timer pin available as a general-purpose I/O pin when the associated timer channel is set software timer that does not require the use of a pin. Freescale Semiconductor ...
Page 162
... Toggle output on compare 10 Clear output on compare 11 Set output on compare 10 Edge-aligned High-true pulses (clear output on compare) PWM X1 Low-true pulses (set output on compare) 10 Center-aligned High-true pulses (clear output on compare-up) PWM X1 Low-true pulses (set output on compare-up MC9S08GT16A/GT8A Data Sheet, Rev. 1 Configuration Bit Bit Freescale Semiconductor ...
Page 163
... Otherwise, the counter operates as a simple up-counter up-counter, the main 16-bit counter counts from 0x0000 through its terminal count and then continues with 0x0000. The terminal count is 0xFFFF or a modulus value in TPMxMODH:TPMxMODL. Freescale Semiconductor Section 10.3.1, “Timer x Status and Control Register MC9S08GT16A/GT8A Data Sheet, Rev. 1 Timer/Pulse-Width Modulator (S08TPMV2) (TPMxSC)” ...
Page 164
... When either byte of the 16-bit capture register is read, both bytes are latched into a buffer to support coherent 16-bit accesses regardless of order. The coherency sequence can be manually reset by writing to the channel status/control register (TPMxCnSC). An input capture event sets a flag bit (CHnF) that can optionally generate a CPU interrupt request. 164 MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor ...
Page 165
... TPMxCnVH or TPMxCnVL, write to buffer registers. In edge-PWM mode, values are transferred to the corresponding timer channel registers only after both 8-bit bytes of a 16-bit register have been written and the value in the TPMxCNTH:TPMxCNTL counter is 0x0000. (The new duty cycle does not take effect until the next full period.) Freescale Semiconductor OVERFLOW PERIOD PULSE ...
Page 166
... TPMxMODH, TPMxMODL, TPMxCnVH, and TPMxCnVL, actually write to buffer registers. Values are 166 period = 2 x (TPMxMODH:TPMxMODL); for TPMxMODH:TPMxMODL = 0x0001–0x7FFF COUNT = 0 OUTPUT OUTPUT COMPARE COMPARE (COUNT UP) (COUNT DOWN) PULSE WIDTH 2 x PERIOD 2 x MC9S08GT16A/GT8A Data Sheet, Rev. 1 Eqn. 10-1 Eqn. 10-2 COUNT = TPMxMODH:TPMx Freescale Semiconductor ...
Page 167
... This corresponds to the end of a PWM period. (The 0x0000 count value corresponds to the center of a period.) Freescale Semiconductor chapter for absolute interrupt vector addresses, priority, and local MC9S08GT16A/GT8A Data Sheet, Rev ...
Page 168
... The flag is cleared by the 2-step sequence described in 168 Flags.” Flags.” Section 10.5.1, “Clearing Timer Interrupt MC9S08GT16A/GT8A Data Sheet, Rev. 1 Flags.” Freescale Semiconductor ...
Page 169
... This SCI system offers many advanced features not commonly found on other asynchronous serial I/O peripherals on other embedded controllers. The receiver employs an advanced data sampling technique that ensures reliable communication and noise detection. Hardware parity, receiver wakeup, and double buffering on transmit and receive are also included. Freescale Semiconductor MC9S08GT16A/GT8A Data Sheet, Rev. 1 169 ...
Page 170
... PTB0/ADP0 PTC7 PTC6 PTC5 PTC4 NOTE 5 SCL PTC3/SCL SDA PTC2/SDA RXD2 PTC1/RxD2 TXD2 PTC0/TxD2 CH1 PTD4/TPM2CH1 CH0 PTD3/TPM2CLK/TPM2CH0 CH0 PTD2/TPM1CH2 CH1 PTD1/TPM1CH1 CH2 PTD0/TPM1CLK/TPM1CH0 SPSCK PTE5/SPSCK MOSI PTE4/MOSI MISO PTE3/MISO SS PTE2/SS RXD1 PTE1/RxD1 TXD1 PTE0/TxD1 PTG3 PTG2/EXTAL PTG1/XTAL PTG0/BKGD/MS Freescale Semiconductor ...
Page 171
... Section 11.3, “Functional Description,” for a detailed description of SCI operation in the different modes. • 8- and 9- bit data modes • Stop modes — SCI is halted during all stop modes • Loop modes Freescale Semiconductor MC9S08GT16A/GT8A Data Sheet, Rev. 1 Serial Communications Interface (S08SCIV1) 171 ...
Page 172
... TRANSMIT CONTROL TDRE TIE TC TCIE Figure 11-2. SCI Transmitter Block Diagram MC9S08GT16A/GT8A Data Sheet, Rev. 1 shows the receiver portion of the SCI.) LOOPS RSRC LOOP TO RECEIVE CONTROL DATA IN TO TxD PIN SCI CONTROLS TxD TO TxD PIN LOGIC TxD DIRECTION Tx INTERRUPT REQUEST Freescale Semiconductor ...
Page 173
... SCI. INTERNAL BUS 16 × BAUD RATE CLOCK FROM RxD PIN DATA RECOVERY LOOPS SINGLE-WIRE LOOP CONTROL RSRC FROM TRANSMITTER PE PT Freescale Semiconductor (READ-ONLY) SCID – Rx BUFFER DIVIDE 11-BIT RECEIVE SHIFT REGISTER WAKE WAKEUP LOGIC ILT RDRF ...
Page 174
... When 8191, the SCI baud rate = BUSCLK/(16×BR). See also BR bits in 174 Memory chapter of this data sheet for the absolute address SBR12 SBR11 Description SBR5 SBR4 SBR3 Description MC9S08GT16A/GT8A Data Sheet, Rev SBR10 SBR9 SBR8 Table 11- SBR2 SBR1 SBR0 Table 11-1. Freescale Semiconductor ...
Page 175
... Parity Type — Provided parity is enabled (PE = 1), this bit selects even or odd parity. Odd parity means the total PT number the data character, including the parity bit, is odd. Even parity means the total number the data character, including the parity bit, is even. 0 Even parity. 1 Odd parity. Freescale Semiconductor RSRC M ...
Page 176
... I/O pin. 2 Receiver Enable — When the SCI receiver is off, the RxD pin reverts to being a general-purpose port I/O pin Receiver off. 1 Receiver on. 176 RIE ILIE Description Idle,” for more details. MC9S08GT16A/GT8A Data Sheet, Rev RWU SBK Freescale Semiconductor ...
Page 177
... TC is cleared automatically by reading SCIxS1 with and then doing one of the following three things: • Write to the SCI data register (SCIxD) to transmit new data • Queue a preamble by changing TE from • Queue a break character by writing 1 to SBK in SCIxC2 Freescale Semiconductor Description Section 11.3.3.2, “Receiver Wakeup Section 11.3.2.1, “Send Break and Queued ...
Page 178
... Parity Error Flag — set at the same time as RDRF when parity is enabled ( and the parity bit in PF the received character does not agree with the expected parity value. To clear PF, read SCIxS1 and then read the SCI data register (SCIxD parity error. 1 Parity error. 178 Description MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor ...
Page 179
... TxD Pin Direction in Single-Wire Mode — When the SCI is configured for single-wire half-duplex operation TXDIR (LOOPS = RSRC = 1), this bit determines the direction of data at the TxD pin. 0 TxD pin is an input in single-wire mode. 1 TxD pin is an output in single-wire mode. Freescale Semiconductor ...
Page 180
... Reads and writes of this register are also involved in the automatic flag clearing mechanisms for the SCI status flags Reset 0 0 180 Description Figure 11-11. SCI Data Register (SCIxD) MC9S08GT16A/GT8A Data Sheet, Rev Freescale Semiconductor ...
Page 181
... For a Freescale Semiconductor SCI system whose bus frequency is driven by a crystal, the allowed baud rate mismatch is about ±4.5 percent for 8-bit data format and about ± ...
Page 182
... This action queues a break character to be sent as soon as the shifter is available. If SBK is still 1 when the queued break moves into the shifter (synchronized to the baud rate clock), an additional break character is queued. If the receiving device is another Freescale Semiconductor SCI, the break characters will be received all eight data bits and a framing error ( occurs. ...
Page 183
... At the end of a message the beginning of the next message, all receivers automatically force RWU all receivers wake up in time to look at the first character(s) of the next message. Freescale Semiconductor MC9S08GT16A/GT8A Data Sheet, Rev. 1 Serial Communications Interface (S08SCIV1) Section 11 ...
Page 184
... TCIE local interrupt masks are 0s. When a program detects that the receive data register is full (RDRF = 1), it gets the data from the receive data register by reading SCIxD. The RDRF flag is cleared by reading SCIxS1 while RDRF = 1 and then reading SCIxD. 184 MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor ...
Page 185
... Because the clocks are halted, the SCI module will resume operation upon exit from stop (only in stop3 mode). Software should ensure stop mode is not entered while there is a character being transmitted out of or received into the SCI module. Freescale Semiconductor MC9S08GT16A/GT8A Data Sheet, Rev. 1 Serial Communications Interface (S08SCIV1) ...
Page 186
... TxD1 pin so an external device can send serial data to the receiver. When TXDIR = 1, the TxD1 pin is an output driven by the transmitter. In single-wire mode, the internal loop back connection from the transmitter to the receiver causes the receiver to receive characters that are sent out by the transmitter. 186 MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor ...
Page 187
... SPI functionality are shared with port E pins 2–5. See the Characteristics,” appendix for SPI electrical parametric information. When the SPI is enabled, the direction of pins is controlled by module configuration. If the SPI is disabled, all four pins can be used as general-purpose I/O. Freescale Semiconductor MC9S08GT16A/GT8A Data Sheet, Rev. 1 Appendix A, “Electrical 187 ...
Page 188
... PTB0/ADP0 PTC7 PTC6 PTC5 PTC4 NOTE 5 SCL PTC3/SCL SDA PTC2/SDA RXD2 PTC1/RxD2 TXD2 PTC0/TxD2 CH1 PTD4/TPM2CH1 CH0 PTD3/TPM2CLK/TPM2CH0 CH0 PTD2/TPM1CH2 CH1 PTD1/TPM1CH1 CH2 PTD0/TPM1CLK/TPM1CH0 SPSCK PTE5/SPSCK MOSI PTE4/MOSI MISO PTE3/MISO SS PTE2/SS RXD1 PTE1/RxD1 TXD1 PTE0/TxD1 PTG3 PTG2/EXTAL PTG1/XTAL PTG0/BKGD/MS Freescale Semiconductor ...
Page 189
... Serial clock phase and polarity options • Slave select output • Selectable MSB-first or LSB-first shifting Freescale Semiconductor Module Initialization (Slave): to configure interrupts, set primary SPI options, slave mode select, and system enable. to configure optional SPI features Module Initialization (Master): to confi ...
Page 190
... SPID). Pin multiplexing logic controls connections between MCU pins and the SPI module. 190 MOSI MOSI MISO MISO SPSCK SPSCK SS SS Figure 12-3. SPI System Connections MC9S08GT16A/GT8A Data Sheet, Rev. 1 SLAVE SPI SHIFTER Freescale Semiconductor ...
Page 191
... SPI baud rate generator is the bus clock. The three prescale bits (SPPR2:SPPR1:SPPR0) choose a prescale divisor The three rate select bits (SPR2:SPR1:SPR0) divide the output of the prescaler stage 16, 32, 64, 128, or 256 to get the internal SPI master mode bit-rate clock. Freescale Semiconductor Tx BUFFER (WRITE SPID) SHIFT SPI SHIFT REGISTER ...
Page 192
... PRESCALER CLOCK RATE DIVIDER DIVIDE 16, 32, 64, 128, or 256 SPPR2:SPPR1:SPPR0 SPR2:SPR1:SPR0 Figure 12-5. SPI Baud Rate Generation MC9S08GT16A/GT8A Data Sheet, Rev. 1 MASTER DIVIDE BY SPI BIT RATE Freescale Semiconductor ...
Page 193
... SPI Transmit Interrupt Enable — This is the interrupt enable bit for SPI transmit buffer empty (SPTEF). SPTIE 0 Interrupts from SPTEF inhibited (use polling) 1 When SPTEF is 1, hardware interrupt requested Freescale Semiconductor Memory chapter of this data sheet for the absolute address 5 4 SPTIE ...
Page 194
... SS input for mode fault Automatic SS output MODFEN BIDIROE 0 0 Figure 12-7. SPI Control Register 2 (SPIC2) MC9S08GT16A/GT8A Data Sheet, Rev. 1 for more details. Slave Mode Slave select input Slave select input Slave select input Slave select input SPISWAI Freescale Semiconductor Table 12-2. 0 SPC0 0 ...
Page 195
... SPI Baud Rate Divisor — This 3-bit field selects one of eight divisors for the SPI baud rate divider as shown in SPR[2:0] Table 12-6. The input to this divider comes from the SPI baud rate prescaler (see divider is the SPI bit rate clock for master mode. Freescale Semiconductor Description ...
Page 196
... Table 12-6. SPI Baud Rate Divisor 0:0:0 0:0:1 0:1:0 0:1:1 1:0:0 1:0:1 1:1:0 1:1 SPTEF MODF 1 0 Figure 12-9. SPI Status Register (SPIS) MC9S08GT16A/GT8A Data Sheet, Rev Rate Divisor 128 256 Freescale Semiconductor ...
Page 197
... Data may be read from SPID any time after SPRF is set and before another transfer is finished. Failure to read the data out of the receive data buffer before a new transfer ends causes a receive overrun condition and the data from the new transfer is lost. Freescale Semiconductor Description 5 ...
Page 198
... LSBFE. Both variations of SPSCK polarity are shown, but only one of these waveforms applies for a specific transfer, depending on the value in CPOL. The SAMPLE IN waveform applies to the MOSI input of a slave or the MISO input of a master. The MOSI waveform applies to the MOSI output 198 MC9S08GT16A/GT8A Data Sheet, Rev. 1 Freescale Semiconductor ...
Page 199
... CPHA = 0. At the top of the figure, the eight bit times are shown for reference with bit 1 starting as the slave is selected (SS IN goes low), and bit 8 ends at the last SPSCK edge. The MSB first and LSB first lines show the order of SPI data bits depending on the setting Freescale Semiconductor 1 2 ...
Page 200
... MOSI and MISO outputs of the master and slave, respectively. When CPHA = 0, the slave’s SS input must go to its inactive high level between transfers. 200 2 ... 6 BIT 6 ... BIT 2 BIT 1 BIT 5 ... Figure 12-12. SPI Clock Formats (CPHA = 0) MC9S08GT16A/GT8A Data Sheet, Rev BIT 1 BIT 0 BIT 6 BIT 7 Freescale Semiconductor ...