MC9S12DP512CPV Freescale Semiconductor, MC9S12DP512CPV Datasheet
MC9S12DP512CPV
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... Freescale Semiconductor MC9S12DT512, MC9S12DJ512, Original Release Date: 27 Nov 2001 © Freescale Semiconductor, Inc., 2004. All rights reserved. MC9S12DP512 Device Guide V01.25 Covers also MC9S12A512 Revised: 05 Jul 2005 Freescale Semiconductor, Inc. DOCUMENT NUMBER 9S12DP512DGV1/D 1 ...
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Revision History Version Revision Effective Number Date Date 27 Nov 11 Feb V01.00 2001 2002 13 Mar 13 Mar V01.01 2002 2002 02 Apr 02 Apr V01.02 2002 2002 15 Apr 15 Apr V01.03 2002 2002 06 Jun 06 Jun ...
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Version Revision Effective Number Date Date 24 Jul 24 Jul V01.06 2002 2002 29 Jul 05 Aug V01.07 2002 2002 21 Aug 21 Aug V01.08 2002 2002 24 Sep 24 Sep V01.09 2002 2002 18 Oct 18 Oct V01.10 2002 ...
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MC9S12DP512 Device Guide V01.25 Version Revision Effective Number Date Date 31 Mar 31 Mar V01.16 2003 2003 30 May 30 May V01.17 2003 2003 23 Jul 23 Jul V01.18 2003 2003 24 Jul 24 Jul V01.19 2003 2003 01 Sep ...
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Table of Contents Section 1 Introduction 1.1 Overview ...
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MC9S12DP512 Device Guide V01.25 2.3.20 PE0 / XIRQ — Port E Input Pin ...
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PS1 / TXD0 — Port S I/O Pin ...
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MC9S12DP512 Device Guide V01.25 6.1 CPU12 Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Section 20 Port Integration Module (PIM) Block Description Section 21 Voltage Regulator (VREG) Block Description Section 22 Printed Circuit Board Layout Proposal Appendix A Electrical Characteristics A.1 General ...
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MC9S12DP512 Device Guide V01.25 Appendix B Package Information B.1 General ...
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List of Figures Figure 0-1 Order Part Number Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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MC9S12DP512 Device Guide V01.25 ...
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List of Tables Table 0-1 Derivative Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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MC9S12DP512 Device Guide V01.25 $01C0 - $01FF CAN2 (Freescale Scalable CAN - FSCAN .44 $0200 - ...
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Derivative Differences and Document References Derivative Differences Table 0-1 shows the availability of peripheral modules on the various derivatives. For details about the compatibility within the MC9S12D-Family refer also to engineering bulletin EB386. Modules MC9S12DP512 # of CANs ✓ CAN0 ...
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MC9S12DP512 Device Guide V01.25 The following items should be considered when using a derivative (Table 0-1): • Registers – Do not write or read CAN0 registers (after reset: address range $0140 - $017F), if using a derivative without CAN0. – ...
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The CAN4 pin functionality (TXCAN4, RXCAN4) is not available on port PJ7, PJ6, PM7, PM6, PM5 and PM4, if using a derivative without CAN0. – The BDLC pin functionality (TXB, RXB) is not available on port PM1 and PM0, ...
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MC9S12DP512 Device Guide V01.25 NOTES: 1. Reused due to functional equivalence. ...
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Section 1 Introduction 1.1 Overview The MC9S12DP512 microcontroller unit (MCU 16-bit device composed of standard on-chip peripherals including a 16-bit central processing unit (HCS12 CPU), 512K bytes of Flash EEPROM, 14K bytes of RAM, 4K bytes of EEPROM, ...
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MC9S12DP512 Device Guide V01.25 – Digital filtering – Programmable rising or falling edge trigger • Memory – 512K Flash EEPROM – 4K byte EEPROM – 14K byte RAM • Two 8-channel Analog-to-Digital Converters – 10-bit resolution – External conversion trigger ...
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Inter-IC Bus (IIC) 2 – Compatible with I C Bus standard – Multi-master operation – Software programmable for one of 256 different serial clock frequencies • 112-Pin LQFP package – I/O lines with 5V input and drive capability – ...
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MC9S12DP512 Device Guide V01.25 1.4 Block Diagram Figure 1-1 shows a block diagram of the MC9S12DP512 device. ...
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Figure 1-1 MC9S12DP512 Block Diagram 512K Byte Flash EEPROM 14K Byte RAM 4K Byte EEPROM VDDR VSSR Voltage Regulator VREGEN VDD1,2 VSS1,2 Single-wire Background BKGD CPU12 Debug Module XFC Clock and VDDPLL Reset PLL Periodic Interrupt VSSPLL Generation COP Watchdog ...
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MC9S12DP512 Device Guide V01.25 1.5 Device Memory Map Table 1-1 and Figure 1-2 show the device memory map of the MC9S12DP512 after reset. Note that after reset the bottom 1k of the EEPROM ($0000 - $03FF) are hidden by the ...
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Table 1-1 Device Memory Map Address $8000 - $BFFF Flash EEPROM Page Window Fixed Flash EEPROM array $C000 - $FFFF incl. 2K, 4K 16K Protected Sector at end and 256 bytes of Vector Space at $FF80 - $FFFF ...
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MC9S12DP512 Device Guide V01.25 Figure 1-2 MC9S12DP512 Memory Map $0000 $0400 $0800 $4000 $8000 EXTERN $C000 $FF00 VECTORS VECTORS $FFFF EXPANDED* NORMAL SINGLE CHIP * Assuming that a ‘0’ was driven onto port K bit 7 during MCU is reset ...
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Detailed Register Map $0000 - $000F Address Name Read: $0000 PORTA Write: Read: $0001 PORTB Write: Read: $0002 DDRA Write: Read: $0003 DDRB Write: $0004 - Read: Reserved $0007 Write: Read: $0008 PORTE Write: Read: $0009 DDRE Write: Read: ...
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MC9S12DP512 Device Guide V01.25 $0015 - $0016 Address Name Read: $0015 ITCR Write: Read: $0016 ITEST Write: $0017 - $0019 Address Name Read: $0017- Reserved $0019 Write: $001A - $001B Address Name Read: $001A PARTIDH Write: Read: $001B PARTIDL Write: ...
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BKP (HCS12 Breakpoint) Address Name Bit 7 Read: $0028 BKPCT0 BKEN Write: Read: $0029 BKPCT1 BK0MBH BK0MBL BK1MBH BK1MBL BK0RWE BK0RW BK1RWE BK1RW Write: Read: $002A BKP0X Write: Read: $002B BKP0H Bit 15 Write: Read: $002C BKP0L ...
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MC9S12DP512 Device Guide V01.25 $0034 - $003F Address Name Read: $0039 CLKSEL Write: Read: $003A PLLCTL Write: Read: $003B RTICTL Write: Read: $003C COPCTL Write: Read: FORBYP $003D Test Only Write: Read: CTCTL $003E Test Only Write: Read: $003F ARMCOP ...
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ECT (Enhanced Capture Timer 16 Bit 8 Channels) Address Name Bit 7 Read: $004F TFLG2 TOF Write: Read: $0050 TC0 (hi) Bit 15 Write: Read: $0051 TC0 (lo) Bit 7 Write: Read: $0052 TC1 (hi) Bit 15 ...
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MC9S12DP512 Device Guide V01.25 $0040 - $007F Address Name Read: $0068 ICPAR Write: Read: $0069 DLYCT Write: Read: $006A ICOVW Write: Read: $006B ICSYS Write: Read: $006C Reserved Write: Read: TIMTST $006D Test Only Write: Read: $006E - Reserved $006F ...
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ATD0 (Analog to Digital Converter 10 Bit 8 Channel) Address Name Bit 7 Read: $0080 ATD0CTL0 Write: Read: $0081 ATD0CTL1 Write: Read: $0082 ATD0CTL2 ADPU Write: Read: $0083 ATD0CTL3 Write: Read: $0084 ATD0CTL4 SRES8 Write: Read: $0085 ...
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MC9S12DP512 Device Guide V01.25 $0080 - $009F Address Name Read: $0099 ATD0DR4L Write: Read: $009A ATD0DR5H Write: Read: $009B ATD0DR5L Write: Read: $009C ATD0DR6H Write: Read: $009D ATD0DR6L Write: Read: $009E ATD0DR7H Write: Read: $009F ATD0DR7L Write: $00A0 - $00C7 ...
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PWM (Pulse Width Modulator 8 Bit 8 Channel) Address Name Bit 7 Read: Bit 7 $00AF PWMCNT3 Write: Read: Bit 7 $00B0 PWMCNT4 Write: Read: Bit 7 $00B1 PWMCNT5 Write: Read: Bit 7 $00B2 PWMCNT6 Write: Read: ...
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MC9S12DP512 Device Guide V01.25 $00C8 - $00CF Address Name Read: $00C8 SCI0BDH Write: Read: $00C9 SCI0BDL Write: Read: $00CA SC0CR1 Write: Read: $00CB SCI0CR2 Write: Read: $00CC SCI0SR1 Write: Read: $00CD SC0SR2 Write: Read: $00CE SCI0DRH Write: Read: $00CF SCI0DRL ...
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SPI0 (Serial Peripheral Interface) Address Name Bit 7 Read: $00DC Reserved Write: Read: $00DD SPI0DR Bit 7 Write: Read: $00DE - Reserved $00DF Write: $00E0 - $00E7 IIC (Inter IC Bus) Address Name Bit 7 Read: $00E0 ...
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MC9S12DP512 Device Guide V01.25 $00F0 - $00F7 Address Name Read: $00F0 SPI1CR1 Write: Read: $00F1 SPI1CR2 Write: Read: $00F2 SPI1BR Write: Read: $00F3 SPI1SR Write: Read: $00F4 Reserved Write: Read: $00F5 SPI1DR Write: Read: $00F6 - Reserved $00F7 Write: $00F8 ...
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Flash Control Register (fts512k4) Address Name Bit 7 Read: $0106 FCMD Write: Read: $0107 Reserved Write: Read: $0108 FADDRHI Bit 15 Write: Read: $0109 FADDRLO Bit 7 Write: Read: $010A FDATAHI Bit 15 Write: Read: $010B FDATALO ...
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MC9S12DP512 Device Guide V01.25 $0120 - $013F Address Name Read: $0120 ATD1CTL0 Write: Read: $0121 ATD1CTL1 Write: Read: $0122 ATD1CTL2 Write: Read: $0123 ATD1CTL3 Write: Read: $0124 ATD1CTL4 Write: Read: $0125 ATD1CTL5 Write: Read: $0126 ATD1STAT0 Write: Read: $0127 Reserved ...
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ATD1 (Analog to Digital Converter 10 Bit 8 Channel) Address Name Bit 7 Read: Bit 7 $0139 ATD1DR4L Write: Read: Bit 15 $013A ATD1DR5H Write: Read: Bit 7 $013B ATD1DR5L Write: Read: Bit 15 $013C ATD1DR6H Write: ...
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MC9S12DP512 Device Guide V01.25 $0140 - $017F Address Name Read: $0154 - CAN0IDMR0 - $0157 CAN0IDMR3 Write: Read: $0158 - CAN0IDAR4 - $015B CAN0IDAR7 Write: Read: $015C - CAN0IDMR4 - $015F CAN0IDMR7 Write: Read: $0160 - CAN0RXFG $016F Write: Read: ...
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Table 1-2 Detailed FSCAN Foreground Receive and Transmit Buffer Layout Address Name Bit 7 Extended ID Read: ID6 CANxTIDR3 Write: $xx13 Standard ID Read: Write: Read: $xx14 - CANxTDSR0 - DB7 $xx1B CANxTDSR7 Write: Read: $xx1C CANxTDLR Write: Read: $xx1D ...
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MC9S12DP512 Device Guide V01.25 $0180 - $01BF Address Name Read: $0194 - CAN1IDMR0 - $0197 CAN1IDMR3 Write: Read: $0198 - CAN1IDAR4 - $019B CAN1IDAR7 Write: Read: $019C - CAN1IDMR4 - $019F CAN1IDMR7 Write: Read: $01A0 - CAN1RXFG $01AF Write: Read: ...
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CAN2 (Freescale Scalable CAN - FSCAN) Address Name Bit 7 Read: $01D8 - CAN2IDAR4 - AC7 $01DB CAN2IDAR7 Write: Read: $01DC - CAN2IDMR4 - AM7 $01DF CAN2IDMR7 Write: Read: $01E0 - CAN2RXFG $01EF Write: Read: $01F0 - ...
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MC9S12DP512 Device Guide V01.25 $0200 - $023F Address Name Read: $021C - CAN3IDMR4 - $021F CAN3IDMR7 Write: Read: $0220 - CAN3RXFG $022F Write: Read: $0230 - CAN3TXFG $023F Write: $0240 - $027F Address Name Read: $0240 PTT Write: Read: $0241 ...
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PIM (Port Integration Module PIM_9DP256) Address Name Bit 7 Read: $0254 PERM PERM7 Write: Read: $0255 PPSM PPSM7 Write: Read: $0256 WOMM WOMM7 WOMM6 WOMM5 WOMM4 WOMM3 WOMM2 WOMM1 WOMM0 Write: Read: $0257 MODRR Write: Read: $0258 ...
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MC9S12DP512 Device Guide V01.25 $0240 - $027F Address Name Read: $026D PPSJ Write: Read: $026E PIEJ Write: Read: $026F PIFJ Write: $0270 - Reserved Read: $027F $0280 - $02BF Address Name Read: $0280 CAN4CTL0 Write: Read: $0281 CAN4CTL1 Write: Read: ...
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Address Name Read: $029C - CAN4IDMR4 - $029F CAN4IDMR7 Write: Read: $02A0 - CAN4RXFG $02AF Write: Read: $02B0 - CAN4TXFG $02BF Write: $02C0 - $03FF Address Name $02C0 - Read: Reserved $03FF Write: 1.6 Part ID Assignments ...
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MC9S12DP512 Device Guide V01.25 ...
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Section 2 Signal Description This section describes signals that connect off-chip. It includes a pinout diagram, a table of signal properties, and detailed discussion of signals built from the signal description sections of the Block Guides of the ...
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MC9S12DP512 Device Guide V01.25 2.1 Device Pinout The MC9S12DP512 is available in a 112-pin low profile quad flat pack (LQFP). Most pins perform two or more functions, as described in the Signal Descriptions. Figure 2-1 shows the pin assignments. SS1/PWM3/KWP3/PP3 ...
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Signal Properties Summary Table 2-1 summarizes the pin functionality. Pin Name Pin Name Pin Name Funct. 1 Funct. 2 Funct. 3 EXTAL — — XTAL — — RESET — — TEST — — VREGEN — — XFC — — ...
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MC9S12DP512 Device Guide V01.25 Pin Name Pin Name Pin Name Funct. 1 Funct. 2 Funct. 3 PH7 KWH7 SS2 PH6 KWH6 SCK2 PH5 KWH5 MOSI2 PH4 KWH4 MISO2 PH3 KWH3 SS1 PH2 KWH2 SCK1 PH1 KWH1 MOSI1 PH0 KWH0 MISO1 ...
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Pin Name Pin Name Pin Name Funct. 1 Funct. 2 Funct. 3 PS7 SS0 — PS6 SCK0 — PS5 MOSI0 — PS4 MISO0 — PS3 TXD1 — PS2 RXD1 — PS1 TXD0 — PS0 RXD0 — PT[7:0] IOC[7:0] — 2.3 ...
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MC9S12DP512 Device Guide V01.25 2.3.5 XFC — PLL Loop Filter Pin PLL loop filter. Please ask your Freescale representative for the interactive application note to compute PLL loop filter elements. Any current leakage on this pin must be avoided. Figure ...
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PA[7:0] / ADDR[15:8] / DATA[15:8] — Port A I/O Pins PA7-PA0 are general purpose input or output pins. In MCU expanded modes of operation, these pins are used for the multiplexed external address and data bus. 2.3.12 PB[7:0] / ...
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MC9S12DP512 Device Guide V01.25 MCU * Rs can be zero (shorted) when used with higher frequency crystals. Refer to manufacturer’s data. Figure 2-4 Pierce Oscillator Connections (PE7=0) MCU Figure 2-5 External Clock Connections (PE7=0) 2.3.14 PE6 / MODB / IPIPE1 ...
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PE3 / LSTRB / TAGLO — Port E I/O Pin 3 PE3 is a general purpose input or output pin. In MCU expanded modes of operation, LSTRB can be used for the low-byte strobe function to indicate the type ...
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MC9S12DP512 Device Guide V01.25 2.3.25 PH3 / KWH3 / SS1 — Port H I/O Pin 3 PH3 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or ...
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Flash EEPROM memory in the memory map (ROMCTL). At the rising edge of RESET, the state of this pin is latched to the ROMON bit. 2.3.33 PK[5:0] / XADDR[19:14] — Port K I/O Pins [5:0] PK5-PK0 ...
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MC9S12DP512 Device Guide V01.25 2.3.40 PM1 / TXCAN0 / TXB — Port M I/O Pin 1 PM1 is a general purpose input or output pin. It can be configured as the transmit pin TXCAN of the Freescale Scalable Controller Area ...
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PP2 / KWP2 / PWM2 / SCK1 — Port P I/O Pin 2 PP2 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. ...
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MC9S12DP512 Device Guide V01.25 2.3.55 PS2 / RXD1 — Port S I/O Pin 2 PS2 is a general purpose input or output pin. It can be configured as the receive pin RXD of Serial Communication Interface 1 (SCI1). 2.3.56 PS1 ...
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NOTE: All VSS pins must be connected together in the application. 2.4.1 VDDX,VSSX — Power & Ground Pins for I/O Drivers External power and ground for I/O drivers. Because fast signal transitions place high, short-duration current demands on the power ...
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MC9S12DP512 Device Guide V01.25 2.4.7 VREGEN — On Chip Voltage Regulator Enable Enables the internal 5V to 2.5V voltage regulator. If this pin is tied low, VDD1,2 and VDDPLL must be supplied externally. ...
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Section 3 System Clock Description 3.1 Overview The Clock and Reset Generator provides the internal clock signals for the core and all peripheral modules. Figure 3-1 shows the clock connections from the CRG to all modules. Consult the CRG Block ...
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MC9S12DP512 Device Guide V01.25 ...
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Section 4 Modes of Operation 4.1 Overview Eight possible modes determine the operating configuration of the MC9S12DP512. Each mode has an associated default memory map and external bus configuration controlled by a further pin. Three low power modes exist for ...
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MC9S12DP512 Device Guide V01.25 Table 4-2 Clock Selection Based on PE7 PE7 = XCLKS 1 0 Table 4-3 Voltage Regulator VREGEN VREGEN 1 0 4.3 Security The device will make available a security feature preventing the unauthorized read and write ...
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Executing from External Memory The user may wish to execute from external space with a secured microcontroller. This is accomplished by resetting directly into expanded mode. The internal FLASH and EEPROM will be disabled. BDM operations will be blocked. ...
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MC9S12DP512 Device Guide V01.25 4.4.4 Run Although this is not a low power mode, unused peripheral modules should not be enabled in order to save power. ...
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Section 5 Resets and Interrupts 5.1 Overview Consult the Exception Processing section of the CPU12 Reference Manual for information on resets and interrupts. 5.2 Vectors 5.2.1 Vector Table Table 5-1 lists interrupt sources and vectors in default order of priority. ...
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MC9S12DP512 Device Guide V01.25 $FFCA, $FFCB Modulus Down Counter underflow $FFC8, $FFC9 Pulse Accumulator B Overflow $FFC6, $FFC7 CRG PLL lock $FFC4, $FFC5 CRG Self Clock Mode $FFC2, $FFC3 $FFC0, $FFC1 $FFBE, $FFBF $FFBC, $FFBD $FFBA, $FFBB $FFB8, $FFB9 $FFB6, ...
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Memory Refer to Table 1-1 for locations of the memories depending on the operating mode after reset. The RAM array is not automatically initialized out of reset. MC9S12DP512 Device Guide V01.25 75 ...
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Section 6 HCS12 Core Block Description 6.1 CPU12 Block Description Consult the HCS12 CPU Reference Manual for information on the CPU. 6.1.1 Device-specific information When the HCS12 CPU Reference Manual refers to cycles this is equivalent to Bus Clock periods. ...
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MC9S12DP512 Device Guide V01.25 6.5 HCS12 Background Debug (BDM) Block Description Consult the BDM Block Guide for information on the HCS12 Background Debug module. 6.5.1 Device-specific information When the BDM Block Guide refers to alternate clock this is equivalent to ...
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There are two Analog to Digital Converters (ATD1 and ATD0) implemented on the MC9S12DP512. Consult the ATD_10B8C Block Guide for information about each Analog to Digital Converter module. When the ATD_10B8C Block Guide refers to freeze mode this is equivalent ...
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MC9S12DP512 Device Guide V01.25 The "S12 LRAE" generic Load RAM and Execute (LRAE) program which will be programmed into the flash memory of this device during manufacture. This LRAE program will provide greater programming flexibility to the end ...
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Section 22 Printed Circuit Board Layout Proposal Table 22-1 Suggested External Component Values Component C10 / C P C11 / ...
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MC9S12DP512 Device Guide V01.25 Figure 22-1 Recommended PCB Layout for 112LQFP Colpitts Oscillator VDD1 C1 VSS1 VSSA VSSX VSSR VDDR Q1 VSSPLL VDDPLL R1 C3 VDDA VSS2 C2 VDD2 ...
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Figure 22-2 Recommended PCB Layout for 112LQFP Pierce Oscillator VSSX VDD1 C1 VSS1 VSSR VDDR VDDPLL MC9S12DP512 Device Guide V01.25 VSSA C3 VSSPLL VDDA VSS2 C2 VDD2 83 ...
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Appendix A Electrical Characteristics A.1 General NOTE: The electrical characteristics given in this section are preliminary and should be used as a guide only. Values cannot be guaranteed by Freescale and are subject to change without notice. This supplement contains ...
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MC9S12DP512 Device Guide V01.25 The VDDX, VSSX, VDDR and VSSR pairs supply the I/O pins, VDDR supplies also the internal voltage regulator. VDD1, VSS1, VDD2 and VSS2 are the supply pins for the digital logic, VDDPLL, VSSPLL supply the oscillator ...
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A.1.4 Current Injection Power supply must maintain regulation within operating V operating maximum current conditions. If positive injection current (V injection current may flow out of VDD5 and could result in external power supply going out of regulation. Ensure external ...
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MC9S12DP512 Device Guide V01.25 2. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply. The absolute maximum ratings apply when the device is powered from an external source. 3. All ...
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A.1.7 Operating Conditions This chapter describes the operating conditions of the device. Unless otherwise noted those conditions apply to all the following data. NOTE: Please refer to the temperature rating of the device ( with regards to the ...
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MC9S12DP512 Device Guide V01. Junction Temperature Ambient Temperature Total Chip Power Dissipation, [W] = Package Thermal Resistance, [ C/W] JA The total power dissipation can be calculated ...
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Table A-5 Thermal Package Characteristics Num C Rating 1 T Thermal Resistance LQFP112, single sided PCB Thermal Resistance LQFP112, double sided PCB with 2 internal planes NOTES: 1. The values for thermal resistance are achieved by package ...
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MC9S12DP512 Device Guide V01.25 Conditions are shown in Table A-4 unless otherwise noted Num C Rating 1 P Input High Voltage T Input High Voltage 2 P Input Low Voltage T Input Low Voltage 3 C Input Hysteresis Input Leakage ...
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A.1.10.1 Measurement Conditions All measurements are without output loads. Unless otherwise noted the currents are measured in single chip mode, internal voltage regulator enabled and at 25MHz bus frequency using a 4MHz oscillator in Colpitts mode. Production testing is performed ...
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MC9S12DP512 Device Guide V01.25 NOTES: 1. PLL off 2. At those low power dissipation levels can be assumed J A ...
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A.2 ATD Characteristics This section describes the characteristics of the analog to digital converter. A.2.1 ATD Operating Characteristics The Table A-8 shows conditions under which the ATD operates. The following constraints exist to obtain full-scale, full range results ...
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MC9S12DP512 Device Guide V01.25 specifies results in an error of less than 1/2 LSB (2.5mV) at the maximum leakage current. If device or operating conditions are less than worst case or leakage-induced error is acceptable, larger values of source resistance ...
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A.2.3 ATD accuracy Table A-10 specifies the ATD conversion performance excluding any errors due to current injection, input capacitance and source resistance. Table A-10 ATD Conversion Performance Conditions are shown in Table A-4 unless otherwise noted ...
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MC9S12DP512 Device Guide V01.25 DNL LSB V i-1 $3FF $3FE $3FD $3FC $3FB $3FA $3F9 $3F8 $3F7 $3F6 $3F5 $3F4 $3F3 Figure A-1 ATD ...
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A.3 NVM, Flash and EEPROM NOTE: Unless otherwise noted the abbreviation NVM (Non Volatile Memory) is used for both Flash and EEPROM. A.3.1 NVM timing The time base for all NVM program or erase operations is derived from the oscillator. ...
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MC9S12DP512 Device Guide V01.25 The setup time can be ignored for this operation. A.3.1.4 Mass Erase Erasing a NVM block takes: The setup time can be ignored for this operation. A.3.1.5 Blank Check The time it takes to perform a ...
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A.3.2 NVM Reliability The reliability of the NVM blocks is guaranteed by stress test during qualification, constant process monitors and burn-in to screen early life failures. The program/erase cycle count on the sector is incremented every time a sector or ...
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MC9S12DP512 Device Guide V01.25 Figure A-2 Typical Endurance vs Temperature 500 450 400 350 300 250 200 150 100 50 0 -40 -20 ------ Flash ------ EEPROM Operating Temperature T J 120 100 140 [ ...
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A.4 Voltage Regulator The on-chip voltage regulator is intended to supply the internal logic and oscillator circuits. No external DC load is allowed. Table A-13 Voltage Regulator Recommended Load Capacitances Rating Load Capacitance on VDD1, 2 Load Capacitance on VDDPLL ...
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A.5 Reset, Oscillator and PLL This section summarizes the electrical characteristics of the various startup scenarios for Oscillator and Phase-Locked-Loop (PLL). A.5.1 Startup Table A-14 summarizes several startup characteristics explained in this section. Detailed description of the startup behavior can ...
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MC9S12DP512 Device Guide V01.25 A.5.1.5 Pseudo Stop and Wait Recovery The recovery from Pseudo STOP and Wait are essentially the same since the oscillator was not stopped in both modes. The controller can be woken up by internal or external ...
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NOTES: 1. Depending on the crystal a damping series resistor might be necessary 4MHz 22pF. osc 3. Maximum value is for extreme cases using high Q, low frequency crystals 4. Only valid if Pierce oscillator/external ...
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MC9S12DP512 Device Guide V01.25 The phase detector relationship is given by the current in tracking mode. ch The loop bandwidth f should be chosen to fulfill the Gardner’s stability criteria by at least a factor of 10, ...
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The relative deviation its maximum for one clock period, and decreases towards zero for larger nom number of clock periods (N). Defining the jitter as For ...
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MC9S12DP512 Device Guide V01.25 This is very important to notice with respect to timers, serial modules where a pre-scaler will eliminate the effect of the jitter to a large extent. Conditions are shown in Table A-4 unless otherwise noted Num ...
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A.6 MSCAN Table A-17 MSCAN Wake-up Pulse Characteristics Conditions are shown in Table A-4 unless otherwise noted Num C Rating 1 P MSCAN Wake-up dominant pulse filtered 2 P MSCAN Wake-up dominant pulse pass MC9S12DP512 Device Guide V01.25 Symbol Min ...
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A.7 SPI This section provides electrical parametrics and ratings for the SPI. In Table A-18 the measurement conditions are listed. Table A-18 Measurement Conditions Description Drive mode Load capacitance C LOAD, on all outputs Thresholds for delay measurement points A.7.1 ...
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MC9S12DP512 Device Guide V01. (OUTPUT SCK (CPOL 0) (OUTPUT) 4 SCK (CPOL 1) (OUTPUT) 5 MISO MSB IN (INPUT) 9 MOSI PORT DATA MASTER MSB OUT (OUTPUT) 1.If configured as output 2. LSBF = 0. For ...
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A.7.2 Slave Mode In Figure A-8 the timing diagram for slave mode with transmission format CPHA=0 is depicted. SS (INPUT) SCK (CPOL 0) (INPUT) 2 SCK (CPOL 1) 10 (INPUT) 7 MISO see SLAVE MSB (OUTPUT) note 5 MOSI MSB ...
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MC9S12DP512 Device Guide V01.25 SS (INPUT SCK (CPOL 0) (INPUT) 4 SCK (CPOL 1) (INPUT) 9 MISO see SLAVE note (OUTPUT MOSI MSB IN (INPUT) NOTE: Not defined! Figure A-9 SPI Slave Timing (CPHA=1) In Table ...
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A.8 External Bus Timing A timing diagram of the external multiplexed-bus is illustrated in Figure A-10 with the actual timing values shown on table Table A-21. All major bus signals are included in the diagram. While both a data write ...
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MC9S12DP512 Device Guide V01.25 ECLK PE4 5 9 Addr/Data data (read) PA, PB Addr/Data data (write) PA Non-Multiplexed Addresses PK5:0 ECS PK7 24 R/W PE2 27 LSTRB PE3 30 NOACC PE7 33 IPIPE0 IPIPE1, PE6,5 Figure A-10 General ...
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Table A-21 Expanded Bus Timing Characteristics Conditions are shown in Table A-4 unless otherwise noted, C Num C Rating 1 P Frequency of operation (E-clock Cycle time 3 D Pulse width, E low Pulse width, ...
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MC9S12DP512 Device Guide V01.25 Table A-21 Expanded Bus Timing Characteristics Conditions are shown in Table A-4 unless otherwise noted, C Num C Rating 32 D NOACC hold time 33 D IPIPE[1:0] delay time D IPIPE[1:0] valid time to E rise ...
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Appendix B Package Information B.1 General This section provides the physical dimensions of the MC9S12DP512 packages. MC9S12DP512 Device Guide V01.25 121 ...
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MC9S12DP512 Device Guide V01.25 B.2 112-pin LQFP package 0. PIN 1 112 IDENT 1 VIEW 0.050 C1 VIEW AB Figure B-1 112-pin LQFP mechanical dimensions (case ...
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User Guide End Sheet MC9S12DP512 Device Guide V01.25 123 ...
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