MCF5207 FREESCALE [Freescale Semiconductor, Inc], MCF5207 Datasheet
MCF5207
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MCF5207 Summary of contents
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... SDR/DDR SDRAM controller, a 16-channel DMA controller three UARTs, a queued SPI, a low-power management modeule, and other peripherals that enable the MCF5207 and MCF5208 for use in industrial control and connectivity applications. The MCF5208 device also features a 10/100 Mbps fast ethernet controller. ...
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... MCF5207/8 Device Configurations 1 MCF5207/8 Device Configurations The following table compares the two devices described in this document: Table 1. MCF5207 & MCF5208 Configurations Version 2 ColdFire Core with EMAC (Enhanced Multiply-Accumulate Unit) Core (System) Clock Peripheral and External Bus Clock (Core clock ÷ 2) Performance (Dhrystone/2.1 MIPS) ...
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... The primary functionality of a pin is not necessarily its default functionality. Pins that are muxed with GPIO will default to their GPIO functionality. Table 3. MCF5207/8 Signal Information and Muxing Signal Name GPIO Alternate 1 ...
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... Signal Descriptions Table 3. MCF5207/8 Signal Information and Muxing (continued) Signal Name GPIO Alternate 1 2 RCON — DRAMSEL — A[23:22] — FB_CS[5:4] A[21:16] — A[15:14] — SD_BA[1:0] A[13:11] — SD_A[13:11] A10 — A[9:0] — SD_A[9:0] D[31:16] — SD_D[31:16] D[15:0] — FB_D[31:16] BE/BWE[3:0] PBE[3:0] SD_DQM[3:0] OE PBUSCTL3 2 TA PBUSCTL2 R/W PBUSCTL1 TS PBUSCTL0 ...
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... Table 3. MCF5207/8 Signal Information and Muxing (continued) Signal Name GPIO Alternate 1 SD_A10 — SD_CKE — SD_CLK — SD_CLK — SD_CS0 — SD_DQS[3:2] — SD_SCAS — SD_SRAS — SD_SDR_DQS — SD_WE — IRQ7 PIRQ7 2 2 IRQ4 PIRQ4 2 2 IRQ1 PIRQ1 FEC_MDC ...
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... Signal Descriptions Table 3. MCF5207/8 Signal Information and Muxing (continued) Signal Name GPIO Alternate I2C_SCL PFECI2C1 DACK0 and DREQ0 do not have a dedicated bond pads. Please refer to the following pins for muxing: TS and QSPI_CS2 for DACK0, IRQ4 and QSPI_DIN for DREQ0. QSPI_CS2 ...
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... Table 3. MCF5207/8 Signal Information and Muxing (continued) Signal Name GPIO Alternate 1 PSTCLK — BKPT — DSI — DSO — DDATA[3:0] — PST[3:0] — ALLPST — 6 TEST — PLL_TEST — EVDD — IVDD — PLL_VDD — SD_VDD — VSS — PLL_VSS — ...
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... Mechanicals and Pinouts This section contains drawings showing the pinout and the packaging and mechanical characteristics of the MCF5207 and MCF5208 devices. The mechanical drawings are the latest revisions at the time of publication of this document. The most up-to-date mechanical drawings can be found at the product summary page located at http://www.freescale.com/coldfire. ...
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... D24 28 SD_SDR_DQS 29 IVDD 30 SD_CLK 31 SD_CLK 32 SD_VDD 33 FB_CLK 34 SD_VDD 35 VSS 36 Figure 1. MCF5207CAG166 Pinout Top View (144 LQFP) MCF5208 ColdFire Freescale Semiconductor ® Microprocessor Data Sheet, Rev. 0.5 Preliminary Mechanicals and Pinouts 108 A17 107 A16 106 A15 105 A14 104 A13 103 A12 ...
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... Mechanicals and Pinouts 4.2 Package Dimensions—144 LQFP Figure 2 and Figure 3 show MCF5207CAB166 package dimensions. Figure 2. MCF5207CAB166 Package Dimensions (Sheet MCF5208 ColdFire 10 ® Microprocessor Data Sheet, Rev. 0.5 Preliminary Freescale Semiconductor ...
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... View A Figure 3. MCF5207CAB166 Package Dimensions (Sheet MCF5208 ColdFire Freescale Semiconductor Section A-A Rotated 90× CW 144 Places View B ® Microprocessor Data Sheet, Rev. 0.5 Preliminary Mechanicals and Pinouts 11 ...
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... Mechanicals and Pinouts 4.3 Pinout—144 MAPBGA The pinout of the MCF5207CVM166 device is shown below SD_CS U1RTS DT0IN DT1IN B D14 D15 TS U1CTS C D12 D13 SD_CKE RCON D D10 D11 SD_WE IVDD BE/BWE1 U0CTS F D31 D30 SD_DQS1 BE/BWE3 G D29 D28 D26 SD_SDR_ ...
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... Package Dimensions—144 MAPBGA Figure 5 shows the MCF5207CAB166 package dimensions. Figure 5. MCF5207CAB166 Package Dimensions (144 MAPBGA) MCF5208 ColdFire Freescale Semiconductor ® Microprocessor Data Sheet, Rev. 0.5 Preliminary Mechanicals and Pinouts 13 ...
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Mechanicals and Pinouts 4.5 Pinout—160 QFP Figure 6 shows a pinout of the MCF5208CAB166 device. • VSS 1 EVDD 2 FEC_TXD0 3 FEC_TXD1 4 FEC_TXD2 5 FEC_TXD3 6 FEC_COL 7 FEC_CRS 8 EVDD 9 VSS 10 SD_VDD ...
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Package Dimensions—160 QFP The package dimensions of the MCF5208CAB166 device are shown in the figures below. Figure 7. MCF5208CAB166 Package Dimensions (Sheet MCF5208 ColdFire Freescale Semiconductor Top View ® Microprocessor Data Sheet, Rev. 0.5 Preliminary Mechanicals ...
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Mechanicals and Pinouts DETAIL A Figure 8. MCF5208CAB166 Package Dimensions (Sheet MCF5208 ColdFire 16 SECTION B-B ® Microprocessor Data Sheet, Rev. 0.5 Preliminary Freescale Semiconductor ...
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Pinout—196 MAPBGA Figure 6 shows a pinout of the MCF5208CVM166 device FEC_ FEC_ FEC_ A VSS TXEN TXER RXDV FEC_ FEC_ FEC_ FEC_ B TXD0 TXD1 TXCLK RXCLK FEC_ FEC_ FEC_ C RCON TXD3 TXD2 ...
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Preliminary Electrical Characteristics 4.8 Package Dimensions—196 MAPBGA The package dimensions for the MCF5208CVM166 device is shown below. Top View Bottom View Figure 10. MCF5208CVM166 Package Dimensions (196 MAPBGA) 5 Preliminary Electrical Characteristics The following electrical specifications are preliminary and are ...
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Table 4. Absolute Maximum Ratings 3 Digital Input Voltage Instantaneous Maximum Current Single pin limit (applies to all pins) Operating Temperature Range (Packaged) Storage Temperature Range NOTES: 1 Functional operating conditions are given in Absolute maximum ratings are stress ratings ...
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Preliminary Electrical Characteristics NOTES: θ and Ψ 1 parameters are simulated in conformance with EIA/JESD Standard 51-2 for natural convection. JMA jt Freescale recommends the use of θ device junction temperatures from exceeding the rated specification. System designers should be ...
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NOTES: 1 All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification ...
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Preliminary Electrical Characteristics Table 7. DC Electrical Specifications (continued) Characteristic 2 Input Capacitance All input-only pins All input/output (three-state) pins Core Operating Supply Current Master Mode LIMP mode STOP mode Low Power mode NOTES: 1 Refer to the signals section ...
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Notes should not exceed any time, including power-up. 2. Recommended that IV 0.9 V, then separate for completion of ramps. 3. Input voltage must not be greater than ...
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Preliminary Electrical Characteristics than 0.4 V during power down or there will be undesired high current in the ESD protection diodes. There are no requirements for the fall times of the power supplies. The recommended power down sequence is as ...
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The timings are also valid for inputs sampled on the negative clock edge. FB_CLK(75MHz) Input Setup And Hold Input Rise Time Input Fall Time FB_CLK FB4 Inputs Figure 13. General Input Timing Requirements 5.6.1 FlexBus A multi-function external bus ...
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Preliminary Electrical Characteristics Num Characteristic FB2 Data, and Control Output Valid (A[23:0], D[31:0], FB_CS[5:0], R/W, TS, BE/BWE[3:0] and OE) FB3 Data, and Control Output Hold ((A[23:0], D[31:0], FB_CS[5:0], R/W, TS, BE/BWE[3:0], and OE) FB4 Data Input Setup FB5 Data Input ...
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FB_CLK A[23:0] D[31:0] R/W TS FB_CSn, BE/BWEn OE TA 5.7 SDRAM Bus The SDRAM controller supports accesses to main SDRAM memory from any internal master. It supports either standard SDRAM or double data rate (DDR) SDRAM, but it does not ...
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Preliminary Electrical Characteristics Symbol Characteristic Frequency of Operation SD1 Clock Period ( SD2 Clock Skew ( SD3 Pulse Width High (t ) CKH SD4 Pulse Width Low (t ) CKL SD5 Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, ...
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SD2 SD1 SD_CLK0 SD2 SD_CLK1 SD_CSn, CMD SD_RAS, SD_CAS SD_WE, SD5 A[23:0], ROW SD_BA[1:0] SDDM D[31:0] MCF5208 ColdFire Freescale Semiconductor SD3 SD6 COL SD12 WD1 Figure 16. SDR Write Timing ® Microprocessor Data Sheet, Rev. 0.5 Preliminary Preliminary Electrical Characteristics ...
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Preliminary Electrical Characteristics SD2 SD_CLK0 SD2 SD_CLK1 SD_CSn, SD_RAS, CMD SD_CAS, SD_WE SD5 A[23:0], ROW SD_BA[1:0] SDDM (Measured at Output Pin) SD_DQS (Measured at Input Pin) SD_DDQS Delayed SD_CLK D[31:0] form Memories NOTE: Data driven from memories relative to delayed ...
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Num Characteristic DD5 Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_CS[1:0] - Output Hold DD6 Write Command to first DQS Latching Transition DD7 Data and Data Mask Output Setup (DQ-->DQS) Relative to DQS (DDR Write Mode) DD8 Data and Data Mask Output ...
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Preliminary Electrical Characteristics SD_CLK SD_CLK SD_CSn, SD_WE, SD_RAS, SD_CAS DD4 A[13:0] DM3/DM2 SD_DQS3/SD_DQS2 D[31:24]/D[23:16] MCF5208 ColdFire 32 DD1 DD2 DD5 CMD DD6 ROW COL WD1 WD2 WD3 WD4 Figure 18. DDR Write Timing ® Microprocessor Data Sheet, Rev. 0.5 Preliminary ...
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SD_CLK SD_CLK SD_CSn, SD_WE, SD_RAS, SD_CAS A[13:0] SD_DQS3/SD_DQS2 D[31:24]/D[23:16] SD_DQS3/SD_DQS2 D[31:24]/D[23:16] Figure 20 shows the DDR clock crossover specifications. SD_CLK SD_CLK 5.8 General Purpose I/O Timing Num G1 FB_CLK High to GPIO Output Valid G2 FB_CLK High to GPIO Output ...
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Preliminary Electrical Characteristics NOTES: 1 GPIO spec cover: IRQn, UART and Timer pins. 5.9 Reset and Configuration Override Timing Table 13. Reset and Configuration Override Timing Num Characteristic R1 RESET Input valid to FB_CLK High R2 FB_CLK High to RESET ...
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Refer to the MCF5208 Reference Manual for more information Input/Output Timing Specifications Table 14 and Table 15 list specifications for the I 2 Table 14 Input Timing Specifications between I2C_SCL and I2C_SDA Num I1 ...
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Preliminary Electrical Characteristics I2 I2C_SCL I1 I2C_SDA 5.11 Fast Ethernet AC Timing Specifications MII signals use TTL signal levels compatible with devices operating at either 5 3.3 V. 5.11.1 MII Receive Signal Timing (FEC_RXD[3:0], FEC_RXDV, FEC_RXER, and FEC_RXCLK) ...
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MII Transmit Signal Timing (FEC_TXD[3:0], FEC_TXEN, FEC_TXER, FEC_TXCLK) Table 17 lists MII transmit channel timings. The transmitter functions correctly FEC_TXCLK maximum frequency of 25 MHz +1%. There is no minimum frequency requirement. In addition, the processor ...
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Preliminary Electrical Characteristics FEC_CRS FEC_COL 5.11.4 MII Serial Management Channel Timing (FEC_MDIO and FEC_MDC) Table 19 lists MII serial management channel timings. The FEC functions correctly with a maximum MDC frequency of 2.5 MHz. Table 19. MII Serial Management Channel ...
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Timer Module AC Timing Specifications Table 20 lists timer module AC timings. Table 20. Timer Module AC Timing Specifications Name T1 DT0IN / DT1IN / DT2IN / DT3IN cycle time T2 DT0IN / DT1IN / DT2IN / DT3IN ...
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Preliminary Electrical Characteristics 5.14 JTAG and Boundary Scan Timing Num Characteristics J1 TCLK Frequency of Operation J2 TCLK Cycle Period J3 TCLK Clock Pulse Width J4 TCLK Rise and Fall Times J5 Boundary Scan Input Data Setup Time to TCLK ...
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TCLK V Data Inputs Data Outputs Data Outputs Data Outputs TCLK V IL TDI TMS TDO TDO TDO TCLK TRST 5.15 Debug AC Timing Specifications Table 23 lists specifications for the debug AC timing parameters shown in MCF5208 ColdFire Freescale ...
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Preliminary Electrical Characteristics Num DE0 PSTCLK cycle time DE1 PST valid to PSTCLK high DE2 PSTCLK high to PST invalid DE3 DSCLK cycle time DE4 DSI valid to DSCLK high 1 DE5 DSCLK high to DSO invalid DE6 BKPT input ...
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FB_CLK DE6 DE7 BKPT DSCLK DE3 DSI DSO 6 Revision History Revision Date Number 0 5/23/2005 0.1 6/16/2005 MCF5208 ColdFire Freescale Semiconductor DE5 Current DE4 Past Figure 34. BDM Serial Port AC Timing Table 24. Revision History Substantive Changes • ...
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Revision History Revision Date Number 0.2 8/26/2005 0.3 9/07/2005 0.4 10/10/2005 0.5 3/29/2006 MCF5208 ColdFire 44 Table 24. Revision History (continued) Substantive Changes • Changed ball M9 from SD_VDD to EVDD in • Table 3: Pin 33 for 144 LQFP ...
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THIS PAGE INTENTIONALLY LEFT BLANK MCF5208 ColdFire Freescale Semiconductor ® Microprocessor Data Sheet, Rev. 0.5 Preliminary 45 ...
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