MCIMX31LVKN5 Freescale Semiconductor, MCIMX31LVKN5 Datasheet

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... The MCIMX31 takes advantage of the ARM1136JF-S™ core running 532 MHz, and is optimized for This document contains information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2005–2008. All rights reserved. Document Number: MCIMX31 Rev. 4.1, 11/2008 ...

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... Multiple clock and power domains — Independent gating of power domains • Multiple communication and expansion ports including a fast parallel interface to an external graphic accelerator (supporting major graphic accelerator vendors) • Security MCIMX31/MCIMX31L Technical Data, Rev. 4.1 2 ® tightly-coupled Vector Freescale Semiconductor ...

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... MCIMX31. Part Number Silicon Revision MCIMX31VKN5 1.15 MCIMX31LVKN5 1.15 MCIMX31VKN5B 1.2 MCIMX31LVKN5B 1.2 MCIMX31VKN5C 2.0 MCIMX31LVKN5C 2.0 MCIMX31CVKN5C 2.0 MCIMX31LCVKN5C 2.0 MCIMX31VMN5C 2.0 MCIMX31LVMN5C 2.0 1 Information on reading the silicon revision register can be found in the IC Identification (IIM) chapter of the Reference Manual, see Section 7, “ ...

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... Java byte ™ logic Tamper Detection Mouse Keyboard AUDMUX Power SSI (2) Management UART ( (3) FIR CSPI (3) PWM USB Host (2) USB-OTG KPP Keypad GPIO CCM Serial ® 1-WIRE EPROM IIM GPU* GPS ATA Hard Drive USB Host/Device Freescale Semiconductor ...

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... The ARM Application Processor (AP) and other subsystems address the needs of the personal, wireless, and portable product market with integrated peripherals, advanced processor core, and power management capabilities. MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor Functional Description and Application Information ™ L2 interface Table 2. MCIMX31 Core ...

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... Mbit/s half duplex link via a LED and IR detector. It supports 0.576 Mbit/s, 1.152 Mbit/s medium infrared (MIR) physical layer protocol and 4Mbit/s fast infrared (FIR) physical layer protocol defined by IrDA, Rev. 1.4. Section/ Page 4.3.4/26 4.3.5/27 4.3.6/36 4.3.3/25 — 4.3.7/36 4.3.8/37 — — 4.3.9.3/46, 4.3.9.1/38, 4.3.9.2/41 — 4.3.10/54 4.3.11/55 Freescale Semiconductor ...

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... Run-Time Security Integrity Checkers MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor Functional Description and Application Information Brief Description The Fusebox is a ROM that is factory configured by Freescale. The GPIO provides several groups of 32-bit bidirectional, general purpose I/O. This peripheral provides dedicated general-purpose signals that can be configured as either inputs or outputs ...

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... In device (bypass) mode, the OTG port functions as gateway between the Host 1 Port and the OTG transceiver. The WDOG module protects against system failures by providing a method for the system to recover from unexpected events or programming errors. Section/ Page — 4.3.19/89 — 4.3.20/90 4.3.21/94 4.3.22/96 — 4.3.23/104 — Freescale Semiconductor ...

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... To select CKIH, tie CLKSS to NVCC1. To select CKIL, tie CLKSS to ground. After initialization, the reference clock source can be changed (initial setting is overwritten) by programming the PRCS bits in the CCMR. MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor Section 5, “Package Information and Signal Descriptions Pinout.” ...

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... Table 4 for a quick reference Topic appears … on page 10 on page 11 on page 13 on page 14 on page 14 on page 16 on page 19 Table 8, Min Max Units –0.5 1.65 V –0.5 3.3 V –0.5 NVCC +0 –40 125 C — 1500 V — 200 — 500 — Freescale Semiconductor ...

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... Junction to Ambient (natural convection) Junction to Ambient (natural convection) Junction to Ambient (@200 ft/min) Junction to Ambient (@200 ft/min) Junction to Board Junction to Case (Top) Junction to Package Top (natural convection) MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor × Package Board Symbol Single layer board (1s) R θJA ...

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... Thermal characterization parameter indicating the temperature difference between the package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT. MCIMX31/MCIMX31L Technical Data, Rev. 4.1 12 NOTES Freescale Semiconductor ...

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... Overshoot/undershoot must be controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other methods. Non-compliance to this specification may affect device reliability or cause permanent damage to the device. MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor NOTE CAUTION Table 8. Operating Ranges ...

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... Section 4.3.3, “Clock Amplifier Module (CAMP) Table 10. Interface Frequency Symbol Min f DC JTAG f 32 CKIL f 15 CKIH for extended temperature range offerings Min Max Units — — V 3.0 3.3 V Typ Max Units 5 10 MHz 32.768 38.4 kHz 26 75 MHz Freescale Semiconductor ...

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... The current I is during program time (t program 2 The current I is present for approximately the read access to the 8-bit word, and only applies to Silicon Rev. 1.2 read and previous. MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor Symbol Minimum I — program I — read ) ...

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... Silicon Revision 1.2 and Previous QVCC QVCC1 QVCC4 (Peripheral) (ARM) (L2) Typ Max Typ Max Typ 0.80 — 0.50 — — 6.00 — 3.00 — 0.04 FVCC + MVCC + SVCC + UVCC Unit (PLL) Max Typ Max — 0.04 — mA — 3.50 — mA Freescale Semiconductor ...

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... All clocks are gated off • All modules are off (by programming CGR[2:0] registers) • RNGA oscillator is off • No external resistive loads 1 Typical column 25°C 2 Maximum column 85°C Freescale Semiconductor 1, 2 ° ° QVCC QVCC1 (Peripheral) (ARM) ...

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... Typ Max Typ Max Typ Max 0.16 2.50 — — — — 0.16 2.50 0.07 1.60 — — 6.00 13.00 2.20 16.00 0.03 0.17 Freescale Semiconductor FVCC, +MVCC, +SVCC, +UVCC Unit (PLL) Typ Max 0.02 0.10 mA 0.02 0.10 mA 3.60 4.40 mA ...

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... NVCC1, and NVCC3 through NVCC10 do not need to be powered up in the order shown. NVCC6 and NVCC9 must be at the same voltage potential. These supplies are connected together on-chip to optimize ESD damage immunity. MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor NOTE CAUTION Electrical Characteristics Figure 3 ...

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... The board design must guarantee that supplies reach 90% level before transition to the next state, using Power Management IC or other means. 2 The NVCC1 supply must not precede IOQVDD by more than 0.2 V until IOQVDD has reached 1 IOQVDD is powered up first, there are no restrictions allowable for FVCC, MVCC, SVCC, and UVCC after FUSE_VDD Freescale Semiconductor ...

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... FVCC, MVCC, SVCC, UVCC 4 Release POR Figure 4. Option 2 Power-Up Sequence (Silicon Revision 2.0) MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor Notes: 1 The board design must guarantee that supplies reach 90% level before transition to the next state, using Power Management IC or other means. ...

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... Std Drive –2 High Drive –4 Max Drive – =0.8*NVCC OH_F OH Std Drive –4 High Drive –6 Max Drive –8 for temperature and supply Typ Max Units — — V — — V — 0.15 V — 0.2*NVCC V — — mA — — mA Freescale Semiconductor ...

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... NVCC for Table 16 Table 16. DDR (Double Data Rate) I/O DC Electrical Parameters Parameter High-level output voltage Low-level output voltage High-level output current MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor Symbol Test Conditions Min I V =0.2*NVCC OL_S OL ...

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... NVCC NVCC+0.3 V –0.3 0 0.3*NVCC V ±2 μA — — Table 18 for fast general I/O, and NVCC 80% 20% 0V PA1 1 General I/O Min Typ Max Units 0.92 1.95 3.17 ns 1.5 2.98 4.75 1.52 — 4.81 ns 2.75 8.42 2.79 — 8.56 ns 5.39 16.43 Freescale Semiconductor ...

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... VIH (for square wave input) Sinusoidal Input Amplitude Duty Cycle 1 VDD is the supply voltage of CAMP. See reference manual. 2 This value of the sinusoidal input will be measured through characterization. MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor 1 General I/O Test Symbol Condition tpr 25 pF ...

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... Symbol Min t 60 WR0_low t OW5 SLOT Figure 10 depicts the Read Sequence timing, and OW4 Typ Max Units 511 — µs — 60 µs — 240 µs 512 — µs Typ Max Units 100 120 µs 117 120 µs Table 23 lists Freescale Semiconductor ...

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... This direction control signal is ata_buffer_en. When its high, the bus should drive from host to device. When its low, the bus should drive from device to host. Steering of the signal is such that contention on the host and device tri-state busses is always avoided. MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor OW8 OW7 OW8 ...

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... UDMA0, UDMA1, UDMA2, UDMA3, UDMA4 Table 24 shows ATA Value/ 1 Contributing Factor peripheral clock frequency UDMA0 15 ns UDMA1 10 ns UDMA2, UDMA3 7 ns UDMA4 5 ns UDMA5 4 ns 5.0 ns UDMA5 4.6 ns 12.0 ns 8.5 ns 8 transceiver transceiver transceiver cable cable cable cable cable Freescale Semiconductor ...

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... T > tsu + thi + tskew3 + tskew4 t0 — t0 (min) = (time_1 + time_2 + time_9 Figure 12 shows timing for PIO write, and MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor Table 25 lists the timing parameters for PIO read. Figure 11. PIO Read Timing Diagram Table 25. PIO Read Timing Parameters Value Table 26 lists the timing parameters for PIO write ...

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... MDMA read and write. MCIMX31/MCIMX31L Technical Data, Rev. 4.1 30 Table 26. PIO Write Timing Parameters Value Figure 14 shows timing for MDMA write, and Controlling Variable time_1 time_2w time_9 If not met, increase time_2w time_4 time_ax time_1, time_2r, time_9 — — Table 27 lists the Freescale Semiconductor ...

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... T – (tskew1 + tskew2 + tskew6) — ton ton = time_on * T – tskew1 toff toff = time_off * T – tskew1 MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor Electrical Characteristics Value Controlling Variable time_m time_d time_k time_d, time_k time_d — ...

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... UDMA in burst. Figure 15. UDMA In Transfer Starts Timing Diagram Figure 16. UDMA In Host Terminates Transfer Timing Diagram MCIMX31/MCIMX31L Technical Data, Rev. 4.1 32 Figure 16 shows timing when the UDMA in device terminates transfer, and shows timing when the UDMA in Freescale Semiconductor ...

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... There is a special timing requirement in the ATA host that requires the internal DIOW to go only high 3 clocks after the last active edge on the DSTROBE signal. The equation given on this line tries to capture this constraint. 2. Make ton and toff big enough to avoid bus contention MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor Electrical Characteristics Description Controlling Variable ...

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... UDMA out burst. Figure 18. UDMA Out Transfer Starts Timing Diagram Figure 19. UDMA Out Host Terminates Transfer Timing Diagram MCIMX31/MCIMX31L Technical Data, Rev. 4.1 34 Figure 19 shows timing when the UDMA out device terminates transfer, and shows timing when the UDMA out Freescale Semiconductor ...

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... T – tskew1 toff toff = time_off * T – tskew1 MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor Electrical Characteristics Value Controlling Variable time_ack time_env time_dvs time_dvh time_cyc time_cyc — ...

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... Figure 21. CSPI Master Mode Timing Diagram SSx CS1 SCLK CS7 CS8 MISO CS9 CS10 MOSI Figure 22. CSPI Slave Mode Timing Diagram MCIMX31/MCIMX31L Technical Data, Rev. 4.1 36 CS2 CS3 CS3 CS2 CS2 CS6 CS3 CS3 CS2 Table 30 lists the CS6 CS5 CS4 CS5 CS4 Freescale Semiconductor ...

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... Pre-multiplier (FPM) enable mode) Predivision factor (PD bits) PLL reference frequency range after Predivider PLL output frequency range: MPLL and SPLL Maximum allowed reference clock phase noise. Frequency lock time (FOL mode or non-integer MF) MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor Symbol t clk RISE/FALL t ...

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... NF2 NF1 NF3 NF5 NF6 NF7 NF8 NF9 Command Unit Comments µs In addition to the frequency mV F < 50 kHz modulation mV 50 kHz < F < 300 kHz modulation mV F > 300 kHz modulation ns Measured on CLKO pin ps Measured on CLKO pin Figure 23, Figure 24, Figure 25, NF4 Freescale Semiconductor ...

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... NFCE NFWE NFALE NFIO[7:0] Figure 24. Address Latch Cycle Timing DIagram NFCLE NFCE NFWE NFALE NFIO[15:0] Figure 25. Write Data Latch Cycle Timing DIagram MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor NF1 NF3 NF4 NF10 NF11 NF5 NF7 NF6 NF8 NF9 Address NF1 ...

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... N/A tDHR N/A Table 31, "DPLL Specifications," on page Example Timing for ≈ NFC Clock 33 MHz Unit Min Max 29 — — — — — — — — 27.5 ns 180 — — — ns 12.5 — — — ns 37. Freescale Semiconductor ...

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... Input data, ECB and DTACK all captured according to BCLK rising edge time. WEIM module, and Table 33 lists the timing parameters. MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor NOTE Figure 27 depicts the timing of the Electrical Characteristics 41 ...

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... WEIM Outputs Timing WE22 WE21 WE23 ... WEIM Inputs Timing WE16 WE15 WE18 WE17 WE20 WE19 Figure 27. WEIM Bus Timing Diagram Parameter WE2 WE4 WE6 WE8 WE10 WE12 WE14 Min Max Unit –0.5 2.5 ns –0 – – – – – Freescale Semiconductor ...

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... BCLK is Max drive. Figure 28, Figure 29, Figure 30, Figure basic WEIM accesses to external memory devices with the timing parameters mentioned in Table 33 for specific control parameter settings. MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor Parameter FCE=1 FCE NOTE 31, Figure 32, and Figure 33 depict some examples of ...

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... Figure 29. Asynchronous Memory Timing Diagram for Write Access— MCIMX31/MCIMX31L Technical Data, Rev. 4.1 44 WE2 WE1 V1 WE3 V1 WE15 WE2 V1 WE3 WE4 WE5 WE6 WE12 WE9 WE10 V1 WE13 WSC=1, EBWA=1, EBWN=1, LBN=1 Next Address WE4 WE12 WE8 WE10 WE16 Next Address WE14 Freescale Semiconductor ...

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... WE5 RW WE11 LBA OE WE9 EB[y] ECB DATA WE13 Figure 31. Synchronous Memory TIming Diagram for Burst Write Access— BCS=1, WSC=4, SYNC=1, DOL=0, PSR=1 MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor WE2 Address V1 WE12 WE18 WE18 WE17 WE17 WE16 WE16 V1 V1+2 Halfword ...

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... WE2 Address V1 Write Data WE13 Write WE12 WSC=7, LBA=1, LBN=1, LAH=1 WE2 Address V1 WE11 WE12 WE7 37, Figure 38, and Figure 39 depict the timings pertaining to the Table WE14 WE4 WE6 WE10 WE16 Read Data WE15 WE4 WE8 WE10 34, Table 35, Table 36, Table 37, Freescale Semiconductor ...

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... CS, RAS, CAS, WE, DQM, CKE setup time SD5 CS, RAS, CAS, WE, DQM, CKE hold time SD6 Address setup time SD7 Address hold time SD8 SDRAM access time MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor SD1 SD2 SD4 SD3 SD5 SD4 SD5 COL/BA SD8 ...

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... ESDCTL at the negative edge of SDCLK and the parameters are measured at maximum memory frequency. MCIMX31/MCIMX31L Technical Data, Rev. 4.1 48 Parameter Symbol NOTE indicates SDRAM requirements. All output signals Min Max Unit tOH 1.8 — ns tRC 10 — clock Freescale Semiconductor ...

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... SD5 CS, RAS, CAS, WE, DQM, CKE hold time SD6 Address setup time SD7 Address hold time SD11 Precharge cycle period SD12 Active to read/write command delay MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor SD1 SD3 SD11 SD4 SD12 SD7 ROW / BA SD13 Parameter Symbol ...

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... MCIMX31/MCIMX31L Technical Data, Rev. 4.1 50 Parameter Symbol NOTE indicates SDRAM requirements. All output signals SD1 SD3 SD10 Symbol tCH tCL Min Max Unit tDS 2.0 — ns tDH 1.3 — ns SD2 SD10 ROW/BA Min Max Unit 3.4 4.1 ns 3.4 4.1 ns Freescale Semiconductor ...

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... The timing parameters are similar to the ones used in SDRAM data sheets—that is, Table 36 are driven by the ESDCTL at the negative edge of SDCLK and the parameters are measured at maximum memory frequency. MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor Symbol tCK tAS tAH tRP ...

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... The clock will continue to run unless both CKEs are low. Then the clock will be stopped in low state. Table 37. SDRAM Self-Refresh Cycle Timing Parameters ID Parameter SD16 CKE output delay time MCIMX31/MCIMX31L Technical Data, Rev. 4.1 52 SD16 NOTE Symbol Min tCKS 1.8 Max Unit — ns Freescale Semiconductor ...

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... The timing parameters are similar to the ones used in SDRAM data sheets—that is, Table 38 are driven by the ESDCTL at the negative edge of SDCLK and the parameters are measured at maximum memory frequency. MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor SD18 SD17 SD18 Data Data ...

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... MCIMX31/MCIMX31L Technical Data, Rev. 4.1 54 SD22 SD21 Data Data Data Data Data Parameter NOTE indicates SDRAM requirements. All output signals Table 40 lists the timing parameters. Data Data Data Symbol Min Max Unit tDQSQ — 0.85 ns tQH 2.3 — ns tDQSCK — 6.7 ns Freescale Semiconductor ...

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... Program time for eFuse 1 The program length is defined by the value defined in the epm_pgm_length[2:0] bits of the IIM module. The value to program is based kHz clock source (4 * 1/32 kHz = 125 µs). MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor Min Frequency dependent 2 2 — — ...

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... C-bus specification) Freescale Semiconductor ...

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... Motorola MC30300 (Python) National Semiconductor LM9618 1 Freescale Semiconductor does not recommend one supplier over another and in no way suggests that these are the only camera suppliers. 2 These sensors not validated at time of publication. 4.3.14.2 Functional Description There are three timing modes supported by the IPU. ...

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... Figure 44. Non-Gated Clock Mode Timing Diagram MCIMX31/MCIMX31L Technical Data, Rev. 4.1 58 Active Line n+1th frame invalid 1st byte Section 4.3.14.2.2, “Gated Clock Figure n+1th frame invalid 1st byte 1st byte Mode”), 44. All incoming pixel clocks are 1st byte Freescale Semiconductor ...

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... Display Interfaces — 4.3.15.1 Supported Display Components Table 46 lists the known supported display components at the time of publication. MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor is that of a Motorola sensor. Some other sensors may have a slightly Table 45 lists the timing parameters. 1/IP1 IP2 ...

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... Digital video encoders Analog Devices (for TV) Crystal (Cirrus Logic) Focus 1 Freescale Semiconductor does not recommend one supplier over another and in no way suggests that these are the only display component suppliers. 2 These display components not validated at time of publication. 4.3.15.2 Synchronous Interfaces 4.3.15.2.1 ...

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... DISPB_D3_CLK DISPB_D3_HSYNC DISPB_D3_DRDY DISPB_D3_DATA Figure 47. TFT Panels Timing Diagram—Horizontal Sync Pulse Figure 48 depicts the vertical timing (timing of one frame). All figure parameters shown are programmable. MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor LINE 2 LINE 3 LINE IP7 IP6 IP9 Electrical Characteristics ...

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... Tdpcp else (V_SYNC_WIDTH+1) * Tsw Tvbi1 BGYP * Tsw Tvbi2 (SCREEN_HEIGHT – BGYP – FH) * Tsw , for integer ⎞ ± 0.5 0.5 for fractional ⎠ HSP_CLK_PERIOD DISP3_IF_CLK_PER_WR ⋅ ----------------------------------------------------------------- - = T HSP_CLK HSP_CLK_PERIOD End of frame IP15 and Figure 48. Value Units DISP3_IF_CLK_PER_WR ----------------------------------------------------------------- - HSP_CLK_PERIOD DISP3_IF_CLK_PER_WR ----------------------------------------------------------------- - HSP_CLK_PERIOD Freescale Semiconductor ...

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... IP19 Data holdup time IP20 Control signals setup time to display interface clock 1 The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display. These conditions may be device specific. Freescale Semiconductor NOTE IP20 IP17 IP19 IP18 ...

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... SPL pulse width is fixed and aligned to the first data of the line. REV toggles every HSYNC period. Figure 50. Sharp HR-TFT Panel Interface Timing Diagram—Pixel Level 64 Table 49 Horizontal timing D1 D2 IP21 1 DISPB_D3_CLK period IP23 IP25 IP26 MCIMX31/MCIMX31L Technical Data, Rev. 4.1 lists the timing parameters. The The timing D320 Freescale Semiconductor ...

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... DISPB_D3_HSYNC coincide. — transition to an even field (of the same frame), they do not coincide. • The active intervals—during which data is transferred—are marked by the DISPB_D3_HSYNC signal being high. MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor Symbol Value Tsplr (BGXP – Tdpcp Tclsr ...

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... Line and Field Timing - NTSC 623 624 625 1 2 Odd Field 310 311 312 313 314 Line and Field Timing - PAL Odd Field 268 269 273 Even Field 315 316 336 Even Field Freescale Semiconductor ...

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... Additionally, the IPU allows a programmable pause between two burst. The pause is defined in the HSP_CLK cycles. It allows to avoid timing violation between two sequential bursts or two accesses to different displays. The range of this pause is from HSP_CLK cycles. MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor Electrical Characteristics Functional Description Electrical Characteristics ...

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... Single access mode (all control signals are not active for one display interface clock after each display access) Figure 52. Asynchronous Parallel System 80 Interface (Type 1) Burst Mode Timing Diagram MCIMX31/MCIMX31L Technical Data, Rev. 4.1 68 Burst access mode with sampling by CS signal Freescale Semiconductor ...

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... DISPB_PAR_RS DISPB_WR DISPB_RD DISPB_DATA Single access mode (all control signals are not active for one display interface clock after each display access) Figure 53. Asynchronous Parallel System 80 Interface (Type 2) Burst Mode Timing Diagram MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor Electrical Characteristics 69 ...

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... Single access mode (all control signals are not active for one display interface clock after each display access) Figure 54. Asynchronous Parallel System 68k Interface (Type 1) Burst Mode Timing Diagram MCIMX31/MCIMX31L Technical Data, Rev. 4.1 70 Burst access mode with sampling by CS signal Freescale Semiconductor ...

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... Display read operation can be performed with wait states when each read access takes up to four display interface clock cycles according to the DISP0_RD_WAIT_ST parameter in the DI_DISP0_TIME_CONF_3, DI_DISP1_TIME_CONF_3, DI_DISP2_TIME_CONF_3 Registers. Figure 56 shows timing of the parallel interface with read wait states. MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor Electrical Characteristics 71 ...

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... DI_DISP_SIG_POL Register). MCIMX31/MCIMX31L Technical Data, Rev. 4.1 72 WRITE OPERATION DISP0_RD_WAIT_ST=00 DISP0_RD_WAIT_ST=01 DISP0_RD_WAIT_ST=10 , Electrical Characteristics Figure 60 depict timing of asynchronous parallel interfaces based on Table 50 lists the timing parameters at display access level. All READ OPERATION Freescale Semiconductor ...

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... DISPB_DATA[16] (WRITE_H) IP37 DISPB_DATA (Input) DISPB_DATA (Output) IP46,IP44 Figure 57. Asynchronous Parallel System 80 Interface (Type 1) Timing Diagram MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor IP28, IP27 IP31, IP29 read point Read Data IP39 IP47 IP45, IP43 IP42, IP41 Electrical Characteristics IP36, IP34 ...

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... IP37 DISPB_DATA (Input) DISPB_DATA (Output) IP46,IP44 Figure 58. Asynchronous Parallel System 80 Interface (Type 2) Timing Diagram MCIMX31/MCIMX31L Technical Data, Rev. 4.1 74 IP28, IP27 IP31, IP29 read point IP38 Read Data IP39 IP47 IP45, IP43 IP42, IP41 IP36, IP34 IP32, IP30 IP40 Freescale Semiconductor ...

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... DISPB_WR (READ/WRITE) IP37 DISPB_DATA (Input) DISPB_DATA (Output) IP46,IP44 Figure 59. Asynchronous Parallel System 68k Interface (Type 1) Timing Diagram MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor IP28, IP27 IP31, IP29 read point IP38 Read Data IP39 IP47 IP45, IP43 IP42, IP41 Electrical Characteristics ...

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... Tdicpw–Tdicdw+ Tdicpw–Tdicdw+ Tdicuw–1.5 Tdicuw Tdicur–1.5 Tdicur Tdicpr–Tdicdr–1.5 Tdicpr–Tdicdr Tdicuw–1.5 Tdicuw IP36, IP34 IP32, IP30 IP40 1 Max. Units Tdicpr+1.5 ns Tdicpw+1 Tdicdr–Tdicur+1.5 ns Tdicpr–Tdicdr+Tdicur+1 Tdicdw–Tdicuw+1.5 ns Tdicpw–Tdicdw+ ns Tdicuw+1.5 — ns — ns — ns Freescale Semiconductor ...

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... T HSP_CLK ceil HSP_CLK_PERIOD 10 Loopback delay Tlbd is the cumulative propagation delay of read controls and read data. It includes an IPU output delay, a device-level output delay, board delays, a device-level input delay, an IPU input delay. This value is device specific. Freescale Semiconductor Min. Tdicpw–Tdicdw 0 Tdrp–Tlbd–Tdicdr+1.5 Tdicdw– ...

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... Figure 61. 3-Wire Serial Interface Timing Diagram Figure 62 depicts timing of the 4-wire serial interface. For this interface, there are separate input and output data lines both inside and outside the device. MCIMX31/MCIMX31L Technical Data, Rev. 4 Functional Description display IF clock cycle Input or output data Freescale Semiconductor ...

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... Figure 62. 4-Wire Serial Interface Timing Diagram Figure 63 depicts timing of the 5-wire serial interface (Type 1). For this interface, a separate RS line is added. When a burst is transmitted within single active chip select interval, the RS can be changed at boundaries of words. MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor Electrical Characteristics Write ...

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... DISPB_SD_D (Input) DISPB_SER_RS 1 display IF DISPB_D#_CS clock cycle DISPB_SD_D_CLK DISPB_SD_D (Output) DISPB_SD_D (Input) DISPB_SER_RS Figure 63. 5-Wire Serial Interface (Type 1) Timing Diagram MCIMX31/MCIMX31L Technical Data, Rev. 4.1 80 Write Preamble Read RW Preamble display IF clock cycle Output data 1 display IF clock cycle Input data Freescale Semiconductor ...

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... IF DISPB_SER_RS clock cycle 1 display IF DISPB_D#_CS clock cycle DISPB_SD_D_CLK DISPB_SD_D (Output) DISPB_SD_D (Input) 1 display IF DISPB_SER_RS clock cycle Figure 64. 5-Wire Serial Interface (Type 2) Timing Diagram MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor Write Preamble Read RW Preamble Electrical Characteristics 1 display IF clock cycle D4 ...

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... Tdicdw–Tdicuw–1.5 Tdicdw –Tdicuw Tdicpw–Tdicdw+ Tdicpw–Tdicdw+ Tdicuw–1.5 Tdicuw Tdicur–1.5 Tdicur Tdicpr–Tdicdr–1.5 Tdicpr–Tdicdr IP57, IP55 IP51, IP53 IP61 1 Max. Units Tdicpr+1.5 ns Tdicpw+1 Tdicdr–Tdicur+1.5 ns Tdicpr–Tdicdr+Tdicur+1 Tdicdw–Tdicuw+1.5 ns Tdicpw–Tdicdw+ ns Tdicuw+1.5 — ns — ns Freescale Semiconductor ...

Page 83

... HSP_CLK HSP_CLK_PERIOD 10 Loopback delay Tlbd is the cumulative propagation delay of read controls and read data. It includes an IPU output delay, a device-level output delay, board delays, a device-level input delay, an IPU input delay. This value is device specific. Freescale Semiconductor Min. Tdicuw–1.5 Tdicuw Tdicpw–Tdicdw 0 Tdrp– ...

Page 84

... Figure 66. MSHC_CLK Timing Diagram MSHC_SCLK MSHC_BS MSHC_DATA (Output) MSHC_DATA (Intput) Figure 67. Transfer Operation Timing Diagram (Serial) MCIMX31/MCIMX31L Technical Data, Rev. 4.1 84 depict the MSHC timings, and Table 52 tSCLKc tSCLKwh tSCLKwl tSCLKf tSCLKc tBSsu tDsu tDd and Table 53 list the timing tBSh tDh Freescale Semiconductor ...

Page 85

... Hold time Setup time MSHC_DATA Hold time Output delay time 1 Timing is guaranteed for NVCC from 2.7 through 3.1 V and maximum overdrive NVCC of 3.3 V. See NVCC restrictions described in MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor tSCLKc tDsu tDd NOTE Symbol tSCLKc tSCLKwh tSCLKwl ...

Page 86

... MCIMX31/MCIMX31L Technical Data, Rev. 4 Standards Symbol Min tSCLKc 25 tSCLKwh 5 tSCLKwl 5 tSCLKr — tSCLKf — tBSsu 8 tBSh 1 tDsu 8 tDh 1 tDd — 13. Table 54 Unit Max — ns — ns — — ns — ns — ns — lists the timing Freescale Semiconductor ...

Page 87

... CONTROL HWDATA HREADY HRESP A[25:0] D[15:0] WAIT REG OE/WE/IORD/IOWR CE1/CE2 RW POE Figure 69. Write Accesses Timing Diagram—PSHT=1, PSST=1 MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor ADDR 1 CONTROL 1 DATA write 1 OKAY ADDR 1 DATA write 1 REG PSST PSL Electrical Characteristics OKAY OKAY PSHT ...

Page 88

... The selected clock signal is passed through a prescaler before being input to the counter. The output is available at the pulse-width modulator output (PWMO) external pin. MCIMX31/MCIMX31L Technical Data, Rev. 4.1 88 ADDR 1 CONTROL 1 OKAY OKAY ADDR 1 REG PSST Min DATA read 1 OKAY PSHT PSL Max Unit 63 clock 63 clock 128 clock Freescale Semiconductor ...

Page 89

... CL of PWMO = 30 pF 4.3.19 SDHC Electrical Specifications This section describes the electrical information of the SDHC. 4.3.19.1 SDHC Timing Figure 72 depicts the timings of the SDHC, and MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor Table 55 lists the PWM timing characteristics Figure 71. PWM Timing ...

Page 90

... Output from SDHC to card SD7 Input to SDHC SD8 Figure 72. SDHC Timing Diagram Symbol TLH t THL t ODL SD4 SD3 SD2 Min Max Unit 0 400 kHz 0 25 MHz 0 20 MHz 100 400 kHz 10 — — ns — — –6 — 18.5 ns — –11.5 ns Freescale Semiconductor ...

Page 91

... After 200 clock cycles, RX must be high. • The card must send a response on RX acknowledging the reset between 400 and 40000 clock cycles after T0. MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor Figure 57 lists the timing parameters. 1/Sfreq Sfall Srise Figure 73. SIM Clock Timing Diagram ...

Page 92

... Figure 75. Active-Low-Reset Card Reset Sequence MCIMX31/MCIMX31L Technical Data, Rev. 4.1 92 response 400 clock cycles < Figure 400 clock cycles < 400000 clock cycles < < 200 clock cycles 1 < 40000 clock cycles 2 75): response 3 < 200 clock cycles 1 < 40000 clock cycles 2 3 Freescale Semiconductor ...

Page 93

... Table 58. Timing Requirements for Power Down Sequence Num Description 1 SIM reset to SIM clock stop 2 SIM reset to SIM TX data low 3 SIM reset to SIM Voltage Enable Low 4 SIM Presence Detect to SIM reset Low MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor Figure 76 and Srst2clk Srst2dat Srst2ven Symbol Min S 0.9*1/FCKIL rst2clk S 1 ...

Page 94

... Figure 79 Table 59 lists the SJC timing parameters. SJ1 SJ2 SJ2 VM VM VIL SJ3 SJ4 Input Data Valid SJ6 Output Data Valid SJ7 SJ6 Output Data Valid depicts the SJC test clock depicts the SJC test access port, VIH SJ5 Freescale Semiconductor ...

Page 95

... TCK low to output high impedance SJ8 TMS, TDI data set-up time SJ9 TMS, TDI data hold time SJ10 TCK low to TDO data valid MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor SJ8 Input Data Valid SJ10 Output Data Valid SJ11 SJ10 Output Data Valid Figure 80 ...

Page 96

... Data (for example, during AC97 mode of operation). 4.3.22.1 SSI Transmitter Timing with Internal Clock Figure 81 depicts the SSI transmitter timing with internal clock, and MCIMX31/MCIMX31L Technical Data, Rev. 4.1 96 Parameter All Frequencies Unit Min Max — 100 — — ns Table 60 lists the timing parameters. Freescale Semiconductor ...

Page 97

... SS6 DAM1_T_FS (bl) (Output) DAM1_T_FS (wl) (Output) DAM1_TXD (Output) DAM1_RXD (Input) Note: SRXD Input in Synchronous mode only Figure 81. SSI Transmitter with Internal Clock Timing Diagram MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor SS1 SS5 SS3 SS4 SS8 SS10 SS14 SS16 SS17 SS43 SS42 ...

Page 98

... Loading MCIMX31/MCIMX31L Technical Data, Rev. 4.1 98 Parameter Min Max Unit 81.4 — ns 36.0 — ns — 36.0 — ns — — 15.0 ns — 15.0 ns — 15.0 ns — 15.0 ns — — — 15.0 ns — 15.0 ns — 15.0 ns — 10.0 — — ns — Freescale Semiconductor ...

Page 99

... SS2 DAM1_T_CLK (Output) DAM1_T_FS (bl) (Output) DAM1_T_FS (wl) (Output) DAM1_RXD (Input) SS48 DAM1_R_CLK (Output) Figure 82. SSI Receiver with Internal Clock Timing Diagram MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor Table 61 SS1 SS5 SS4 SS9 SS11 SS20 SS21 SS51 SS47 SS50 SS1 SS5 SS4 ...

Page 100

... Oversampling clock fall time MCIMX31/MCIMX31L Technical Data, Rev. 4.1 100 Parameter Min 81.4 36.0 — 36.0 — — — — — 10.0 0 15.04 6 — 6 — Max Unit — ns — — 15.0 ns 15.0 ns 15.0 ns 15.0 ns — ns — ns — ns — — Freescale Semiconductor ...

Page 101

... SS27 DAM1_T_FS (bl) (Input) DAM1_T_FS (wl) (Input) DAM1_TXD (Output) DAM1_RXD (Input) Note: SRXD Input in Synchronous mode only Figure 83. SSI Transmitter with External Clock Timing Diagram MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor Table 62 SS22 SS25 SS26 SS29 SS31 SS37 SS38 SS45 SS44 SS22 ...

Page 102

... MCIMX31/MCIMX31L Technical Data, Rev. 4.1 102 Parameter Min 81.4 36.0 — 36.0 — –10.0 10.0 –10.0 10.0 — — — 10.0 2.0 — Max Unit — ns — ns 6.0 ns — ns 6.0 ns 15.0 ns — ns 15.0 ns — ns 15.0 ns 15.0 ns 15.0 ns — ns — ns 6.0 ns Freescale Semiconductor ...

Page 103

... SS22 (Tx/Rx) CK clock period SS23 (Tx/Rx) CK clock high period SS24 (Tx/Rx) CK clock rise time SS25 (Tx/Rx) CK clock low period SS26 (Tx/Rx) CK clock fall time MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor Table 63 SS22 SS26 SS25 SS30 SS32 SS35 SS41 SS40 SS22 ...

Page 104

... MCIMX31/MCIMX31L Technical Data, Rev. 4.1 104 Parameter Min –10.0 10.0 –10.0 10.0 — — 10.0 2.0 Table 64 lists the timing parameters Symbol Max Unit 15.0 ns — ns 15.0 ns — ns 6.0 ns 6.0 ns — ns — ns Figure Min Max Units 6 — — ns — Freescale Semiconductor ...

Page 105

... MAPBGA signal assignments), and MAPBGA ground/power ID by ball grid location for the 457 mm, 0.5 mm pitch package. 5.1.1 Production Package Outline Drawing– Figure 86. Production Package: Case 1581—0.5 mm Pitch MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor Package Information and Pinout Section 8, “Revision History,” 0.5 mm 105 ...

Page 106

... J14, L13, L14, L15, L16, M18, U18, V10, V11, V12, V13 QVCC1 J10, J11, K9, L11 QVCC4 N9, R9, T9, U9 SGND T14 SVCC V14 UVCC V16 UGND T16 MCIMX31/MCIMX31L Technical Data, Rev. 4.1 106 × Figure 70 for the 0 MAPBGA signal assignments 0 0.5 mm Ball Location Table 66 shows the device Freescale Semiconductor ...

Page 107

... ATA_CS1 ATA_DIOR ATA_DIOW ATA_DMACK ATA_RESET BATT_LINE BCLK BOOT_MODE0 BOOT_MODE1 BOOT_MODE2 BOOT_MODE3 BOOT_MODE4 CAPTURE CAS CE_CONTROL CKIH MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor Ball Location Signal ID AD6 CKIL AF5 CLKO AF18 CLKSS AC3 COMPARE AD3 CONTRAST AD4 CS0 AF17 CS1 AF16 ...

Page 108

... N25 J24 H25 J3 C15 B17 G15 A17 C16 B18 F15 A18 F13 B15 C14 A15 G14 B16 F14 A16 See VPG1 AE22 P26 P21 T24 U26 V24 Y25 Y26 V21 AA25 W24 AA26 V20 T21 V25 T20 V26 U24 T2 Freescale Semiconductor ...

Page 109

... PWMO RAS READ RESET_IN RI_DCE1 RI_DTE1 RTCK RTS1 RTS2 RW RXD1 RXD2 SCK3 SCK4 SCK5 SDCKE0 SDCKE1 MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor Ball Location Signal ID U21 SCLK0 W26 SD_D_CLK Y21 SD_D_I AC25 SD_D_IO AC1 SD0 See VPG0 SD1 V1 SD1_CLK T6 SD1_CMD ...

Page 110

... USBOTG_DATA1 C19 USBOTG_DATA2 B21 USBOTG_DATA3 R3 USBOTG_DATA4 C3 USBOTG_DATA5 B4 USBOTG_DATA6 R7 USBOTG_DATA7 F17 USBOTG_DIR R1 USBOTG_NXT B3 USBOTG_STP C5 VPG0 T1 VPG1 A21 VSTBY B19 VSYNC0 F16 VSYNC3 A19 WATCHDOG_RST G16 WRITE Ball Location F10 C13 A9 C10 B10 G10 G25 J20 F26 N24 R26 A24 R25 Freescale Semiconductor ...

Page 111

... MAPBGA ground/power ID by ball grid location for the 473 mm, 0.8 mm pitch package. 5.2.1 Production Package Outline Drawing– 0.8 mm Figure 87. Production Package: Case 1931—0.8 mm Pitch MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor Package Information and Pinout Section 8, “Revision History,” 111 ...

Page 112

... T10, U7, U8, U9, U10, V6, V7, V8, V9, V10 QVCC H13, J14, L15, M15, N9, N15, P9, P15, R10, R11, R13, R14 QVCC1 J8, J9, J10, K9 QVCC4 L9, M7, M8, N8 SGND U13 SVCC U12 UVCC P18 UGND P17 MCIMX31/MCIMX31L Technical Data, Rev. 4.1 112 0 0.8 mm Ball Location Table 68, which Freescale Semiconductor ...

Page 113

... A22 A23 A24 A25 ATA_CS0 ATA_CS1 ATA_DIOR ATA_DIOW ATA_DMACK ATA_RESET BATT_LINE BCLK BOOT_MODE0 BOOT_MODE1 MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor Table 68 BGA No Connects Signal Ball Location U21 Ball Location Signal ID Y6 CKIL AC5 CLKO V15 CLKSS AB3 COMPARE AA3 CONTRAST ...

Page 114

... G20 D21 D19 G18 G23 K17 L23 J18 K18 J7 A15 B15 D14 C15 F13 A16 B16 A17 A13 B13 C13 A14 F12 D13 B14 C14 See VPG1 V17 M22 N23 R23 R22 U22 R18 U20 V23 V22 V21 V20 Freescale Semiconductor ...

Page 115

... PC_RST PC_RW PC_VS1 PC_VS2 PC_WAIT POR POWER_FAIL PWMO RAS READ RESET_IN RI_DCE1 RI_DTE1 RTCK RTS1 RTS2 RW MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor Ball Location Signal ID W21 LD17 Y21 LD2 M23 LD3 C19 LD4 G17 LD5 B20 LD6 T20 SCK6 R17 ...

Page 116

... USBOTG_DATA2 C18 USBOTG_DATA3 A19 USBOTG_DATA4 N3 USBOTG_DATA5 C3 USBOTG_DATA6 C4 USBOTG_DATA7 R1 USBOTG_DIR F16 USBOTG_NXT N4 USBOTG_STP B3 VPG0 D1 VPG1 P3 VSTBY D17 VSYNC0 F14 VSYNC3 A18 WATCHDOG_RST B17 WRITE C16 Ball Location AB15 AC15 AA14 AA6 Y7 F15 D9 F11 G21 G22 H18 L22 N20 B21 N22 Freescale Semiconductor ...

Page 117

Ball Maps GND GND SFS5 CSPI2 CSPI2_ USBOT USBOT USBOT _MISO SS2 G_DAT G_DAT G_NXT GND GND STXD4 SRXD CSPI2_ CSPI2_ USBOT USBOT 5 SS0 SPI_R G_DAT ...

Page 118

CSPI2_ USBOTG_ USBOTG USBOTG A GND GND GND SS1 DATA6 _DATA2 _DIR CSPI2_ CSPI2_ USBOTG_ USBOTG_ B GND GND STXD4 MISO SCLK DATA5 NXT CSPI2_ USBOTG_ USBOTG_ C GND GND SRXD4 SRXD5 SS0 ...

Page 119

... Silicon Revision 2.0," on page 17 DPLL maximum Table 31, "DPLL Specifications," on output freq range page 37 MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor Table 73. Silicon 1.2 and Previous Table 1 N/A Table 8, "Operating Ranges," on page 13 Figure 2, "Power-Up Sequence for Silicon Revisions 1.2 and Previous," ...

Page 120

... MCIMX31 Reference Manual (order number MCIMX31RM) MCIMX31 Chip Errata (order number MCIMX31CE) The Freescale manuals are available on the Freescale Semiconductors Web site at http://www.freescale.com/imx. These documents may be downloaded directly from the Freescale Web site, or printed versions may be ordered. ARM Ltd. documentation is available from http://www.arm.com. ...

Page 121

... MCIMX31/MCIMX31L Technical Data, Rev. 4.1 Freescale Semiconductor This page left intentionally blank Revision History 121 ...

Page 122

... Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use ...