mm74hc174 Fairchild Semiconductor, mm74hc174 Datasheet

mm74hc174

Manufacturer Part Number

mm74hc174

Description

Hex D-type Flip-flops With Clear

Manufacturer

Fairchild Semiconductor

Datasheet

1.MM74HC174.pdf (7 pages)

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MM74HC174M

MM74HC174SJ

MM74HC174MTC

MM74HC174N

MM74HC174

Hex D-Type Flip-Flops with Clear

General Description

The MM74HC174 edge triggered flip-flops utilize advanced

silicon-gate CMOS technology to implement D-type flip-

flops. They possess high noise immunity, low power, and

speeds comparable to low power Schottky TTL circuits.

This device contains 6 master-slave flip-flops with a com-

mon clock and common clear. Data on the D input having

the specified setup and hold times is transferred to the Q

output on the LOW-to-HIGH transition of the CLOCK input.

The CLEAR input when LOW, sets all outputs to a low

state.

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Order Number

Pin Assignments for DIP, SOIC, SOP and TSSOP

Package Number

MTC16

M16D

M16A

N16E

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow

16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

DS005318.prf

Each output can drive 10 low power Schottky TTL equiva-

lent loads. The MM74HC174 is functionally as well as pin

compatible to the 74LS174. All inputs are protected from

damage due to static discharge by diodes to V

ground.

Features

Truth Table

established.

Typical propagation delay: 16 ns

Wide operating voltage range: 2–6V

Low input current: 1 A maximum

Low quiescent current: 80 A (74HC Series)

Output drive: 10 LSTTL loads

LOW Level (steady state)

Transition from LOW-to-HIGH level

Don't Care

HIGH Level (steady state)

The level of Q before the indicated steady state input conditions were

Package Description

Clear

Inputs

(Each Flip-Flop)

Clock

September 1983

Revised February 1999

Outputs

www.fairchildsemi.com

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mm74hc174 Summary of contents

Page 1

... Pin Assignments for DIP, SOIC, SOP and TSSOP © 1999 Fairchild Semiconductor Corporation Each output can drive 10 low power Schottky TTL equiva- lent loads. The MM74HC174 is functionally as well as pin compatible to the 74LS174. All inputs are protected from damage due to static discharge by diodes to V ground ...

Page 2

Logic Diagram www.fairchildsemi.com 2 ...

Page 3

Absolute Maximum Ratings (Note 2) Supply Voltage ( Input Voltage ( Output Voltage (V ) OUT Clamp Diode Current ( Output Current, per pin (I ) OUT DC ...

Page 4

AC Electrical Characteristics 15pF Symbol Parameter f Maximum Operating MAX Frequency Maximum Propagation PHL PLH Delay, Clock ...

Page 5

Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC)JEDEC MS-012, 0.150” Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16A Package Number M16D 5 www.fairchildsemi.com ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide www.fairchildsemi.com Package Number MTC16 6 ...

Page 7

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In Line Package (PDIP), JEDEC MS-001, 0.300” Wide LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS ...

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