MP7628 Exar Corporation, MP7628 Datasheet

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MP7628

Manufacturer Part Number
MP7628
Description
5 V Cmos Quad Multiplying 8-bit Digital-to-analog Converter
Manufacturer
Exar Corporation
Datasheet

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FEATURES
GENERAL DESCRIPTION
signed using a decoded DAC architecture featuring excellent
DAC-to-DAC matching and guaranteed monotonicity.
easy microprocessor interface.
latches, eliminating the need for storing information in RAM. In
the event the microprocessor power supply is interrupted, it can
poll the DACs to establish the last known system state.
DATA BUS
SIMPLIFIED BLOCK DIAGRAM
(LSB)
(MSB)
DB0
DB7
Readback Capability for all DACs
On-Chip Latches for All DACs
Linearity Grades to +1/8 LSB
Single Supply Voltage (5 Volt)
DACs Matched to 1%
Four Quadrant Multiplication
Microprocessor TTL/CMOS Compatible
Latch-Up Free
Dual Version: MP7529B
The MP7628 is a quad 8-bit Digital-to-Analog Converter de-
Separate on-chip latches are provided for each DAC to allow
The readback function allows the user to poll or read the data
R/W
DS1
DS2
Rev. 2.00
A/B
DIRECTIONAL
CONTROL
DRIVER
LOGIC
LINE
BI-
GND
V
DD
1
APPLICATIONS
common 8-bit TTL/CMOS compatible input port. Control inputs
DS1, DS2 and A/B determine which DAC is to be loaded. The
MP7628’s load cycle is similar to the write cycle of a random ac-
cess memory and the device is bus compatible with most 8-bit
microprocessors.
less than 5mW.
teristics with a separate reference input and feedback resistor
for each DAC.
Microprocessor Controlled Gain and Attenuation
Circuits
Microprocessor Controlled/Programmable
Power Supplies
Hardware Redundant Applications Requiring
Data Readback
THREE-STATE
THREE-STATE
THREE-STATE
THREE-STATE
Data is transferred into any of the four DAC data latches via
The device operates at +5 V power supply and dissipates
All DACs offer excellent four quadrant multiplication charac-
LATCH A
BUFFER
LATCH B
BUFFER
LATCH C
BUFFER
LATCH D
BUFFER
Digital-to-Analog Converter
V
V
REFB
REFC
Quad Multiplying 8-Bit
V
V
REFD
REFA
DAC C
DAC D
DAC A
DAC B
MP7628
R
R
R
R
FB
FB
FB
FB
5 V CMOS
R
I
I
I
I
R
R
I
I
I
I
R
OUT1A
OUT2A
OUT2B
OUT1B
OUT1C
OUT2C
OUT2D
OUT1D
FBA
FBB
FBC
FBD
/
/

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MP7628 Summary of contents

Page 1

... Data is transferred into any of the four DAC data latches via common 8-bit TTL/CMOS compatible input port. Control inputs DS1, DS2 and A/B determine which DAC loaded. The MP7628’s load cycle is similar to the write cycle of a random ac- cess memory and the device is bus compatible with most 8-bit microprocessors. ...

Page 2

... A DB4 DB7 (MSB DB5 DB6 Pin CDIP, PDIP (0.600”) D28, N28 Rev. 2.00 INL Part No. (LSB) MP7628JN +1/2 MP7628KN +1/4 MP7628JS +1/2 MP7628KS +1/4 MP7628JP +1/2 MP7628KP +1/4 MP7628AD +1/2 MP7628BD +1/4 MP7628SD* +1/2 MP7628TD* +1 OUT2A OUT2B OUT2D OUT1B 5 24 See ...

Page 3

... Control 1 DS2 Control 2 V Reference Voltage for DAC D REFD R Feedback Resistor for DAC D FBD I Current Output 1 DAC D OUT1D I / Current Output 2 DAC C/DAC D OUT2C I OUT2D I Current Output 1 DAC C OUT1C R Feedback Resistor for DAC C FBC V Reference Voltage for DAC C REFC GND Ground 3 MP7628 ...

Page 4

... MP7628 ELECTRICAL CHARACTERISTICS ( +10 V unless otherwise noted) DD REF Parameter Symbol 1 STATIC PERFORMANCE Resolution (All Grades) N Integral Non-Linearity INL (Relative Accuracy Differential Non-Linearity DNL Gain Error Gain Temperature Coefficient TC GE ...

Page 5

... C unless otherwise noted Storage Temperature +0.5 V Lead Temperature (Soldering, 10 seconds) DD +0.5 V Package Power Dissipation Rating +25 V CDIP, PDIP, SOIC, PLCC +25 V Derates above MP7628 Units Test Conditions/Comments 5 All digital inputs = all = – ...

Page 6

... MP7628 TIMING DIAGRAM READ CYCLE A/B R/W t DS1 H DS2 BUS ( 3-state Set up time for BUS, A/B, R/W Minimum DS = low pulse Minimum time between DS = low pulses Data delay time DSR TIMING DIAGRAM WRITE CYCLE DATA ( A/B R/W DS1 DS2 DAC A OUT DAC B OUT MODE SELECTION TABLE ...

Page 7

... Both analog outputs remain at the values corre- sponding to the data in their respective latches. Read Mode: When DS is low and R/W is high, the selected DAC is in the read mode and the data held in the appropriate latch is outputed to the data bus. 7 MP7628 ...

Page 8

... MP7628 28 LEAD CERAMIC DUAL-IN-LINE See Note Base Plane Seating L Plane b INCHES MILLIMETERS SYMBOL MIN MAX MIN A –– 0.232 b 0.014 0.023 0.356 b 0.038 0.065 0.965 1 c 0.008 0.015 0.203 D –– 1.490 E 0.500 0.610 12.70 E 0.590 0.620 14. 0.100 BSC L 0 ...

Page 9

... BSC 2.54 BSC 0.115 0.150 2.92 3. 0.055 0.070 1.40 1.78 0.020 0.100 1.508 2.54 (0.58 mm) for all four corner leads only. 9 MP7628 E C ...

Page 10

... MP7628 28 Seating Plane e Rev. 2.00 28 LEAD SMALL OUTLINE (300 MIL JEDEC SOIC) S28 INCHES MILLIMETERS SYMBOL MIN MAX MIN A 0.097 0.104 2.464 A1 0.0050 0.0115 0.127 B 0.014 0.019 0.356 C 0.0091 0.0125 0.231 D 0.701 0.711 17.81 E 0.292 0.299 7.42 e 0.050 BSC 1.27 BSC H 0 ...

Page 11

... Ref 7.62 Ref. 0.050 BSC 1.27 BSC (1) Dimension D does not include mold protrusion. 1 Allowed mold protrusion is 0.254 mm/0.010 in. 11 MP7628 Seating A 2 Plane 4.57 2.79 3.96 ...

Page 12

... MP7628 EXAR Corporation reserves the right to make changes to the products contained in this publication in order to im- prove design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits de- scribed herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contains here in are only for illustration purposes and may vary depending upon a user’ ...

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