mpc880 Freescale Semiconductor, Inc, mpc880 Datasheet

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mpc880

Manufacturer Part Number
mpc880
Description
Mpc885 Powerquicc Integrated Communications Processor
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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Freescale Semiconductor
Technical Data
MPC885/MPC880 PowerQUICC™
Hardware Specifications
This hardware specification contains detailed information on
power considerations, DC/AC electrical characteristics, and
AC timing specifications for the MPC885/MPC880. The
MPC885 is the superset device of the MPC885/MPC880
family. The CPU on the MPC885/MPC880 is a 32-bit core
built on Power Architecture™ technology that incorporates
memory management units (MMUs) and instruction and
data caches. For functional characteristics of the
MPC885/MPC880, refer to the MPC885 PowerQUICC™
Family Reference Manual.
To locate published errata or updates for this document, refer
to the MPC875/MPC870 product summary page on our
website listed on the back cover of this document or, contact
your local Freescale sales office.
© Freescale Semiconductor, Inc., 2003–2007. All rights reserved.
10. Bus Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 16
11. IEEE 1149.1 Electrical Specifications . . . . . . . . . . . 44
12. CPM Electrical Characteristics . . . . . . . . . . . . . . . . . 46
13. UTOPIA AC Electrical Specifications . . . . . . . . . . . 69
14. USB Electrical Characteristics . . . . . . . . . . . . . . . . . 71
15. FEC Electrical Characteristics . . . . . . . . . . . . . . . . . 71
16. Mechanical Data and Ordering Information . . . . . . . 75
17. Document Revision History . . . . . . . . . . . . . . . . . . . 85
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3. Maximum Tolerated Ratings . . . . . . . . . . . . . . . . . . . 9
4. Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . 10
5. Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 11
7. Thermal Calculation and Measurement . . . . . . . . . . 12
8. Power Supply and Power Sequencing . . . . . . . . . . . 15
9. Layout Practices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Contents
Rev. 4, 08/2007
MPC885EC

Related parts for mpc880

mpc880 Summary of contents

Page 1

... DC/AC electrical characteristics, and AC timing specifications for the MPC885/MPC880. The MPC885 is the superset device of the MPC885/MPC880 family. The CPU on the MPC885/MPC880 is a 32-bit core built on Power Architecture™ technology that incorporates memory management units (MMUs) and instruction and data caches. For functional characteristics of the MPC885/MPC880, refer to the MPC885 PowerQUICC™ ...

Page 2

... MPC880 Features The MPC885/MPC880 is comprised of three modules that each use the 32-bit internal bus: a MPC8xx core, a system integration unit (SIU), and a communications processor module (CPM). The following list summarizes the key MPC885/MPC880 features: • Embedded MPC8xx core up to 133 MHz • ...

Page 3

... Two fast Ethernet controllers (FEC)—Two 10/100 Mbps Ethernet/IEEE Std. 802.3® CDMA/CS that interface through MII and/or RMII interfaces • System integration unit (SIU) — Bus monitor — Software watchdog MPC885/MPC880 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor 2 C can be relocated without RAM-based microcode Features 3 ...

Page 4

... RESTART TRANSMIT — Supports continuous mode transmission and reception on all serial channels — 8-Kbytes of dual-port RAM — Several serial DMA (SDMA) channels to support the CPM — Three parallel I/O registers with open-drain capability MPC885/MPC880 PowerQUICC™ Hardware Specifications, Rev GRACEFUL STOP TRANSMIT ) , ...

Page 5

... The USB function mode has the following features: – Four independent endpoints support control, bulk, interrupt, and isochronous data transfers. – CRC16 generation and checking – CRC5 checking – NRZI encoding/decoding with bit stuffing – 12- or 1.5-Mbps data rate MPC885/MPC880 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor Features 5 ...

Page 6

... Can be internally connected to four serial channels (two SCCs and two SMCs) • Parallel interface port (PIP) — Centronics interface support — Supports fast connection between compatible ports on MPC885/MPC880 and other MPC8xx devices • PCMCIA interface — Master (socket) interface, release 2.1-compliant — ...

Page 7

... I/O operation • The MPC885/MPC880 comes in a 357-pin ball grid array (PBGA) package The MPC885 block diagram is shown in Instruction Instruction Cache Bus Instruction MMU Embedded MPC8xx Processor Core Load/Store Bus Fast Ethernet Controller DMAs DMAs DMAs FIFOs 10/100 BaseT ...

Page 8

... Features The MPC880 block diagram is shown in Instruction Bus Instruction Cache Instruction MMU Embedded MPC8xx Processor Core Load/Store Bus Fast Ethernet Controller DMAs DMAs FIFOs 10/100 BaseT Media Access Control Parallel Interface MIII/RMII MPC885/MPC880 PowerQUICC™ Hardware Specifications, Rev Figure 2. 8-Kbyte ...

Page 9

... See Caution: All inputs that tolerate 5 V cannot be more than 2.5 V greater than V normal operation (that is, if the MPC885/MPC880 is unpowered, a voltage greater than 2.5 V must not be applied to its inputs). Figure 3 shows the undershoot and overshoot voltages at the interfaces of the MPC885/MPC880. ...

Page 10

... Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for example, either GND Thermal Characteristics Table 4 shows the thermal characteristics for the MPC885/MPC880. Table 4. MPC885/MPC880 Thermal Resistance Data Rating 1 Junction-to-ambient Natural convection ...

Page 11

... The V power dissipation is negligible. DDSYN 6 DC Characteristics Table 6 provides the DC electrical characteristics for the MPC885/MPC880. Characteristic Operating voltage Input high voltage (all inputs except EXTAL and EXTCLK) 3 Input low voltage EXTAL, EXTCLK input high voltage Input leakage current, Vin = 5 ...

Page 12

... The junction-to-ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal performance. However, the answer is only an estimate; test cases have demonstrated that errors of a factor of two (in the quantity T MPC885/MPC880 PowerQUICC™ Hardware Specifications, Rev cannot be more than 100 mV. ...

Page 13

... It has been observed that the thermal performance of most plastic packages and especially PBGA packages is strongly dependent on the board temperature; see Figure 4. Figure 4. Effect of Board Temperature Rise on Thermal Behavior MPC885/MPC880 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor θCA . For instance, the user can change the airflow around θCA ...

Page 14

... The thermocouple wire is placed flat against the package case to avoid measurement errors caused by the cooling effects of the thermocouple wire. MPC885/MPC880 PowerQUICC™ Hardware Specifications, Rev × P ...

Page 15

... MPC885/MPC880 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor ) and PLL voltage (V DDL . The I/O section of the MPC885/MPC880 is supplied with 3.3 V across during power up and power down. DDH must not exceed 3.465 V. DDH Power Supply and Power Sequencing ...

Page 16

... DDSYN 10 Bus Signal Timing The maximum bus speed supported by the MPC885/MPC880 is 80 MHz. Higher-speed parts must be operated in half-speed bus mode (for example, an MPC885/MPC880 used at 133 MHz must be configured for a 66 MHz bus). Table 7 shows the frequency ranges for standard part frequencies in 1:1 bus mode, and Table 8 shows the frequency ranges for standard part frequencies in 2:1 bus mode ...

Page 17

... Core frequency Bus frequency Table 9 provides the timings for the MPC885/MPC880 at 33-, 40-, 66-, and 80-MHz bus operation. The timing for the MPC885/MPC880 bus shown assumes a 50-pF load for maximum delays and a 0-pF load for minimum delays. CLKOUT assumes a 100-pF load maximum delay. Num Characteristic ...

Page 18

... TA, BI valid to CLKOUT (setup time) × (MIN = 0. 6.00) B16a TEA, KR, RETRY, CR valid to CLKOUT (setup × time) (MIN = 0. 4.5) B16b BB, BG, BR, valid to CLKOUT (setup time) × (4MIN = 0. 0.00) MPC885/MPC880 PowerQUICC™ Hardware Specifications, Rev Table 9. Bus Operation Timings (continued) 33 MHz Min Max 7.60 — × B1) 7.60 — B1) 7.60 — ...

Page 19

... B1 + 9.00) B27 A(0:31) and BADDR(28:30 asserted GPCM ACS = 10, TRLX = 1 (MIN = 1.25 × B1 – 2.00) B27a A(0:31) and BADDR(28:30 asserted GPCM ACS = 11, TRLX = 1 (MIN = 1.50 × B1 – 2.00) MPC885/MPC880 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor Table 9. Bus Operation Timings (continued) 33 MHz Min Max 1.00 — 2.00 — ...

Page 20

... CS negated to D(0:31) High-Z GPCM write access, TRLX = 0, CSNT = 1 ACS = 10 or ACS = 11, EBDF = 1 (MIN = 0.375 × B1 – 6.30) B29h WE(0:3) negated to D(0:31) High-Z GPCM write access, TRLX = 1, CSNT = 1, EBDF = 1 (MIN = 0.375 × B1 – 3.30) MPC885/MPC880 PowerQUICC™ Hardware Specifications, Rev Table 9. Bus Operation Timings (continued) 33 MHz Min Max — ...

Page 21

... CST1 in the corresponding word in the UPM EBDF = 1 (MAX = 0.375 × 6.6) B32 CLKOUT falling edge to BS valid, as requested by control bit BST4 in the corresponding word in the UPM (MAX = 0.00 × 6.00) MPC885/MPC880 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor Table 9. Bus Operation Timings (continued) 33 MHz Min Max 38.40 — ...

Page 22

... BST2 in the corresponding word in the UPM (MIN = 0.75 × B1 – 2.00) B36 A(0:31), BADDR(28:30), and D(0:31) to GPL valid, as requested by control bit GxT4 in the corresponding word in the UPM (MIN = 0.25 × B1 – 2.00) MPC885/MPC880 PowerQUICC™ Hardware Specifications, Rev Table 9. Bus Operation Timings (continued) 33 MHz Min Max 7.60 14.30 6.30 13.00 3.80 10.50 3.13 10.00 1.50 8 ...

Page 23

... For part speeds above 50 MHz, use 9.80 ns for B11a. 2 The timing required for BR input is relevant when the MPC885/MPC880 is selected to work with the internal bus arbiter. The timing for BG input is relevant when the MPC885/MPC880 is selected to work with the external bus arbiter. 3 For part speeds above 50 MHz, use 2 ns for B17. ...

Page 24

... Maximum output delay specification. B Minimum output hold time. C Minimum input setup time specification. D Minimum input hold time specification. Figure 7 provides the timing for the external clock. CLKOUT MPC885/MPC880 PowerQUICC™ Hardware Specifications, Rev Figure 6. Control Timing B1 B3 ...

Page 25

... Figure 8. Synchronous Output Signals Timing Figure 9 provides the timing for the synchronous active pull-up and open-drain output signals. CLKOUT TS, BB TA, BI TEA Figure 9. Synchronous Active Pull-Up Resistor and Open-Drain Outputs Signals Timing MPC885/MPC880 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor B8 B9 B8a B9 B8b B11 ...

Page 26

... It also applies to normal read accesses under the control of the user-programmable machine (UPM) in the memory controller. CLKOUT TA D[0:31] Figure 11. Input Data Timing in Normal Case MPC885/MPC880 PowerQUICC™ Hardware Specifications, Rev B16 B17 B16a B17a B16b ...

Page 27

... Figure 16 provide the timing for the external bus read controlled by various GPCM factors. CLKOUT TS A[0:31] CSx OE WE[0:3] D[0:31] Figure 13. External Bus Read Timing (GPCM Controlled—ACS = 00) MPC885/MPC880 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor B20 B21 B11 B12 B8 B22 B25 B28 B18 Bus Signal Timing ...

Page 28

... Bus Signal Timing CLKOUT TS A[0:31] CSx OE D[0:31] Figure 14. External Bus Read Timing (GPCM Controlled—TRLX = 0, ACS = 10) CLKOUT TS A[0:31] CSx OE D[0:31] Figure 15. External Bus Read Timing (GPCM Controlled—TRLX = 0, ACS = 11) MPC885/MPC880 PowerQUICC™ Hardware Specifications, Rev B11 B12 B8 B22a B24 B25 B18 B11 B12 B22b B8 B22c B24a ...

Page 29

... CLKOUT B11 TS A[0:31] CSx OE D[0:31] Figure 16. External Bus Read Timing (GPCM Controlled—TRLX = 1, ACS = 10, ACS = 11) MPC885/MPC880 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor B12 B8 B22a B27 B27a B22b B22c B18 Bus Signal Timing B23 B26 B19 29 ...

Page 30

... Figure 19 provide the timing for the external bus write controlled by various GPCM factors. CLKOUT TS A[0:31] CSx WE[0:3] OE D[0:31] Figure 17. External Bus Write Timing (GPCM Controlled—TRLX = 0, CSNT = 0) MPC885/MPC880 PowerQUICC™ Hardware Specifications, Rev B11 B12 B8 B22 B25 B26 B8 B30 B23 B28 B29b ...

Page 31

... CLKOUT TS A[0:31] CSx WE[0:3] OE D[0:31] Figure 18. External Bus Write Timing (GPCM Controlled—TRLX = 0, CSNT = 1) MPC885/MPC880 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor B11 B12 B8 B28b B28d B22 B25 B26 B28a B28c B8 Bus Signal Timing B30a B30c B23 B29c B29g B29a B29f B9 31 ...

Page 32

... Bus Signal Timing CLKOUT B11 TS A[0:31] CSx WE[0:3] OE D[0:31] Figure 19. External Bus Write Timing (GPCM Controlled—TRLX = 1, CSNT = 1) MPC885/MPC880 PowerQUICC™ Hardware Specifications, Rev B12 B8 B22 B25 B26 B8 B30b B30d B28b B28d B23 B29e B29i B29d B29h B29b B28a B28c B9 Freescale Semiconductor ...

Page 33

... Figure 20 provides the timing for the external bus controlled by the UPM. CLKOUT A[0:31] CSx BS_A[0:3], BS_B[0:3] GPL_A[0:5], GPL_B[0:5] Figure 20. External Bus Timing (UPM-Controlled Signals) MPC885/MPC880 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor B8 B31a B31d B31 B34 B34a B34b B32a B32d B32 B35 ...

Page 34

... Figure 21. Asynchronous UPWAIT Asserted Detection in UPM-Handled Cycles Timing Figure 22 provides the timing for the asynchronous negated UPWAIT signal controlled by the UPM. CLKOUT B37 UPWAIT CSx BS_A[0:3], BS_B[0:3] GPL_A[0:5], GPL_B[0:5] Figure 22. Asynchronous UPWAIT Negated Detection in UPM-Handled Cycles Timing MPC885/MPC880 PowerQUICC™ Hardware Specifications, Rev B38 B38 Freescale Semiconductor ...

Page 35

... Figure 24. Asynchronous External Master Memory Access Timing (GPCM Controlled—ACS = 00) Figure 25 provides the timing for the asynchronous external master control signals negation. AS CSx, WE[0:3], OE, GPLx, BS[0:3] Figure 25. Asynchronous External Master—Control Signals Negation Timing MPC885/MPC880 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor B41 B42 B40 B39 B40 B43 ...

Page 36

... The IRQ lines are synchronized internally and do not have to be asserted or negated with reference to the CLKOUT. The I41, I42, and I43 timings are specified to allow correct functioning of the IRQ lines detection circuitry and have no direct relation with the total system interrupt latency that the MPC885/MPC880 is able to support. Figure 26 provides the interrupt detection timing for the external level-sensitive lines ...

Page 37

... Table 11 shows the PCMCIA timing for the MPC885/MPC880. Num Characteristic P44 A(0:31), REG valid to PCMCIA strobe 1 (MIN = 0.75 × B1 – 2.00) asserted P45 A(0:31), REG valid to ALE negation (MIN = 1.00 × B1 – 2.00) P46 CLKOUT to REG valid (MAX = 0.25 × 8.00) P47 CLKOUT to REG invalid (MIN = 0.25 – 1.00) P48 CLKOUT to CE1, CE2 asserted (MAX = 0.25 × ...

Page 38

... PCMCIA access cycle timing for the external bus read. CLKOUT TS A[0:31] REG CE1/CE2 PCOE, IORD ALE D[0:31] Figure 28. PCMCIA Access Cycles Timing External Bus Read MPC885/MPC880 PowerQUICC™ Hardware Specifications, Rev P44 P46 P45 P48 P50 P52 P53 B18 P47 ...

Page 39

... PCWE, IOWR ALE D[0:31] Figure 29. PCMCIA Access Cycles Timing External Bus Write Figure 30 provides the PCMCIA WAIT signals detection timing. CLKOUT WAITx Figure 30. PCMCIA WAIT Signals Detection Timing MPC885/MPC880 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor P44 P46 P45 P48 P50 P52 P53 ...

Page 40

... Figure 31 provides the PCMCIA output port timing for the MPC885/MPC880. CLKOUT Output Signals HRESET OP2, OP3 Figure 32 provides the PCMCIA input port timing for the MPC885/MPC880. CLKOUT Input Signals MPC885/MPC880 PowerQUICC™ Hardware Specifications, Rev Table 12. PCMCIA Port Timing 33 MHz ...

Page 41

... Table 13 shows the debug port timing for the MPC885/MPC880. Num P44 DSCK cycle time D45 DSCK clock pulse width D46 DSCK rise and fall times D47 DSDI input data setup time D48 DSDI data hold time D49 DSCK low to DSDO data valid ...

Page 42

... Bus Signal Timing Table 14 shows the reset timing for the MPC885/MPC880. Num Characteristic P44 CLKOUT to HRESET high impedance (MAX = 0.00 × 20.00) R45 CLKOUT to SRESET high impedance (MAX = 0.00 × 20.00) R46 RSTCONF pulse width (MIN = 17.00 × B1) R47 — R48 Configuration data to HRESET rising edge setup time (MIN = 15.00 × ...

Page 43

... Figure 36. Reset Timing—Data Bus Weak Drive During Configuration Figure 37 provides the reset timing for the debug port configuration. CLKOUT SRESET DSCK, DSDI Figure 37. Reset Timing—Debug Port Configuration MPC885/MPC880 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor R71 R76 R73 R74 R75 ...

Page 44

... IEEE 1149.1 Electrical Specifications 11 IEEE 1149.1 Electrical Specifications Table 15 provides the JTAG timings for the MPC885/MPC880 shown in Num P44 TCK cycle time J45 TCK clock pulse width measured at 1.5 V J46 TCK rise and fall times J47 TMS, TDI data setup time ...

Page 45

... Figure 39. JTAG Test Access Port Timing Diagram TCK TRST TCK Output Signals Output Signals Output Signals Figure 41. Boundary Scan (JTAG) Timing Diagram MPC885/MPC880 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor J85 J86 J87 J88 J91 J90 Figure 40. JTAG TRST Timing Diagram J92 J93 IEEE 1149 ...

Page 46

... Data-in setup time to clock high 30 Data-in hold time from clock high 31 Clock low to data-out valid (CPU writes data, control, or direction) DATA-IN STBI STBO Figure 42. PIP Rx (Interlock Mode) Timing Diagram MPC885/MPC880 PowerQUICC™ Hardware Specifications, Rev Figure 42 Table 16. PIP/PIO Timing Characteristic ...

Page 47

... Figure 43. PIP Tx (Interlock Mode) Timing Diagram DATA-IN STBI (Input) STBO (Output) Figure 44. PIP Rx (Pulse Mode) Timing Diagram DATA-OUT STBO (Output) STBI (Input) Figure 45. PIP TX (Pulse Mode) Timing Diagram MPC885/MPC880 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor CPM Electrical Characteristics ...

Page 48

... Port C interrupt pulse width low (edge-triggered mode) 36 Port C interrupt minimum time between active edges Figure 47 shows the port C interrupt detection timing. Port C (Input) MPC885/MPC880 PowerQUICC™ Hardware Specifications, Rev Table 17. Port C Interrupt Timing Characteristic 35 Figure 47. Port C Interrupt Detection Timing 30 33 ...

Page 49

... TA assertion to rising edge of the clock setup time (applies to external TA) 1 Applies to high-to-low mode (EDM = 1). CLKO (Output) DREQ (Input) Figure 48. IDMA External Requests Timing Diagram MPC885/MPC880 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor Figure 48 Table 18. IDMA Controller Timing Characteristic 1 40 CPM Electrical Characteristics ...

Page 50

... CPM Electrical Characteristics CLKO (Output) TS (Output) R/W (Output) DATA TA (Input) SDACK Figure 49. SDACK Timing Diagram—Peripheral Write, Externally-Generated TA CLKO (Output) TS (Output) R/W (Output) DATA TA (Output) SDACK Figure 50. SDACK Timing Diagram—Peripheral Write, Internally-Generated TA MPC885/MPC880 PowerQUICC™ Hardware Specifications, Rev Freescale Semiconductor ...

Page 51

... Num 50 BRGO rise and fall time 51 BRGO duty cycle 52 BRGO cycle BRGOX Figure 52. Baud Rate Generator Timing Diagram MPC885/MPC880 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor 42 Table 19. Baud Rate Generator Timing Characteristic CPM Electrical Characteristics ...

Page 52

... L1TXD, L1ST(1–4), L1RQ, L1CLKO rise/fall time 73 L1RSYNC, L1TSYNC valid to L1CLK edge (SYNC setup time) 74 L1CLK edge to L1RSYNC, L1TSYNC, invalid (SYNC hold time) 75 L1RSYNC, L1TSYNC rise/fall time MPC885/MPC880 PowerQUICC™ Hardware Specifications, Rev Table 20. Timer Timing Characteristic Figure 54 Table 21 ...

Page 53

... These specs are valid for IDL mode only. 3 Where P = 1/CLKOUT. Thus for a 25-MHz CLKO1 rate ns. 4 These strobes and TxD on the first bit of the frame become valid after L1CLK edge or L1SYNC, whichever comes later. MPC885/MPC880 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor Table 21. SI Timing (continued) Characteristic 4 ...

Page 54

... CPM Electrical Characteristics L1RCLK ( (Input) 71 L1RCLK ( (Input) L1RSYNC (Input) 73 L1RXD (Input) L1ST(4-1) (Output) Figure 54. SI Receive Timing Diagram with Normal Clocking (DSC = 0) MPC885/MPC880 PowerQUICC™ Hardware Specifications, Rev 71a 72 RFSD BIT0 Freescale Semiconductor ...

Page 55

... L1RCLK ( (Input) 82 L1RCLK ( (Input) 75 L1RSYNC (Input L1RXD (Input) 76 L1ST(4-1) (Output) L1CLKO (Output) Figure 55. SI Receive Timing with Double-Speed Clocking (DSC = 1) MPC885/MPC880 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor 72 83a RFSD=1 77 BIT0 78 84 CPM Electrical Characteristics 79 55 ...

Page 56

... CPM Electrical Characteristics L1TCLK ( (Input) 71 L1TCLK ( (Input) 73 L1TSYNC (Input) L1TXD (Output) L1ST(4-1) (Output) Figure 56. SI Transmit Timing Diagram (DSC = 0) MPC885/MPC880 PowerQUICC™ Hardware Specifications, Rev TFSD 80a BIT0 Freescale Semiconductor ...

Page 57

... (Input) L1RCLK ( (Input) L1RSYNC (Input) 73 L1TXD BIT0 (Output) 80 78a L1ST(4-1) (Output) 84 L1CLKO (Output) Figure 57. SI Transmit Timing with Double Speed Clocking (DSC = 1) MPC885/MPC880 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor 72 83a 82 TFSD CPM Electrical Characteristics 79 57 ...

Page 58

... CPM Electrical Characteristics MPC885/MPC880 PowerQUICC™ Hardware Specifications, Rev Figure 58. IDL Timing Freescale Semiconductor ...

Page 59

... CD1 setup time to RCLK1 rising edge 1 The ratios SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater than or equal to 3/1. 2 Also applies to CD and CTS hold time when they are used as external sync signals MPC885/MPC880 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor Table 22. NMSI External Clock Timing 1 2 Table 23 ...

Page 60

... Figure 59. SCC NMSI Receive Timing Diagram TCLK1 102 TxD1 (Output) RTS1 (Output) CTS1 (Input) CTS1 (SYNC Input) Figure 60. SCC NMSI Transmit Timing Diagram MPC885/MPC880 PowerQUICC™ Hardware Specifications, Rev 102 101 100 107 102 101 100 103 105 104 108 ...

Page 61

... TCLK1 clock period 131 TXD1 active delay (from TCLK1 rising edge) 132 TXD1 inactive delay (from TCLK1 rising edge) 133 TENA active delay (from TCLK1 rising edge) MPC885/MPC880 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor 102 101 100 103 104 107 105 Figure 61 ...

Page 62

... SDACK is asserted whenever the SDMA writes the incoming frame DA into memory. CLSN(CTS1) (Input) Figure 62. Ethernet Collision Timing Diagram RCLK1 RxD1 (Input) RENA(CD1) (Input) Figure 63. Ethernet Receive Timing Diagram MPC885/MPC880 PowerQUICC™ Hardware Specifications, Rev Table 24. Ethernet Timing (continued) Characteristic 2 2 120 121 124 125 ...

Page 63

... SMTXD active delay (from SMCLK falling edge) 154 SMRXD/SMSYNC setup time 155 RXD1/SMSYNC hold time 1 SyncCLK must be at least twice as fast as SMCLK. MPC885/MPC880 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor 128 121 132 Figure Table 25. SMC Transparent Timing Characteristic CPM Electrical Characteristics ...

Page 64

... Master data hold time (inputs) 164 Master data valid (after SCK edge) 165 Master data hold time (outputs) 166 Rise time output 167 Fall time output MPC885/MPC880 PowerQUICC™ Hardware Specifications, Rev 151A 152 151 150 Note 1 154 155 154 ...

Page 65

... SPICLK ( (Output) 163 162 SPIMISO msb (Input) 167 SPIMOSI (Output) Figure 67. SPI Master ( Timing Diagram MPC885/MPC880 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor 167 166 160 167 162 166 Data lsb 165 164 Data lsb 167 ...

Page 66

... SPICLK ( (Input) 177 SPIMISO msb (Output) 175 176 SPIMOSI msb (Input) Figure 68. SPI Slave ( Timing Diagram MPC885/MPC880 PowerQUICC™ Hardware Specifications, Rev Figure 68 and Table 27. SPI Slave Timing Characteristic 172 182 181 170 181 182 180 Data ...

Page 67

... High period of SCL 205 Start condition setup time 206 Start condition hold time 207 Data hold time 208 Data setup time 209 SDL/SCL rise time MPC885/MPC880 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor 172 170 182 181 181 182 180 msb Data ...

Page 68

... SCL frequency is given by SCL = BrgClk_frequency/((BRG register + 3) × pre_scaler × 2). The ratio SyncClk/(Brg_Clk/pre_scaler) must be greater or equal to 4/1. 2 Figure 70 shows the I C bus timing. SDA 202 203 205 SCL 206 MPC885/MPC880 PowerQUICC™ Hardware Specifications, Rev Timing (SCL < 100 kH ) (continued) Z Characteristic 2 Table 29 Timing (SCL > 100 kH Expression fSCL ...

Page 69

... Frequency U2 UTPB, SOC, Rxclav, and Txclav active delay U3 UTPB_AUX, SOC_Aux, RxEnb, TxEnb, RxAddr, and TxAddr setup time U4 UTPB_AUX, SOC_Aux, RxEnb, TxEnb, RxAddr, and TxAddr hold time MPC885/MPC880 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor UTOPIA AC Electrical Specifications Direction Min Max Unit ...

Page 70

... RxClav High-Z at MPHY RxEnb UTPB SOC Figure 72 shows signal timings during UTOPIA transmit operations. UtpClk U2 5 PHSEL n TxClav High-Z at MPHY TxEnb UTPB SOC MPC885/MPC880 PowerQUICC™ Hardware Specifications, Rev Figure 71. UTOPIA Receive Timing Figure 72. UTOPIA Transmit Timing ...

Page 71

... MII_RX_CLK pulse width high M4 MII_RX_CLK pulse width low M1_RMII RMII_RXD[1:0], RMII_CRS_DV, RMII_RX_ERR to RMII_REFCLK setup M2_RMII RMII_REFCLK to RMII_RXD[1:0], RMII_CRS_DV, RMII_RX_ERR hold MPC885/MPC880 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor Table 33 lists the USB interface timings. Characteristic 1 1%. – Table 34. MII Receive Signal Timing ...

Page 72

... M20_RMII RMII_TXD[1:0], RMII_TX_EN to RMII_REFCLK setup M21_RMII RMII_TXD[1:0], RMII_TX_EN data hold from RMII_REFCLK rising edge M7 MII_TX_CLK and RMII_REFCLK pulse width high M8 MII_TX_CLK and RMII_REFCLK pulse width low MPC885/MPC880 PowerQUICC™ Hardware Specifications, Rev Table 35. MII Transmit Signal Timing Characteristic M4 Min ...

Page 73

... M11 MII_MDC falling edge to MII_MDIO output valid (max prop delay) M12 MII_MDIO (input) to MII_MDC rising edge setup M13 MII_MDIO (input) to MII_MDC rising edge hold MPC885/MPC880 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor Table 36. MII Async Inputs Signal Timing Characteristic ...

Page 74

... M15 MII_MDC pulse width low Figure 76 shows the MII serial management channel timing diagram. MII_MDC (Output) MII_MDIO (Output) MII_MDIO (Input) Figure 76. MII Serial Management Channel Timing Diagram MPC885/MPC880 PowerQUICC™ Hardware Specifications, Rev Characteristic M14 M10 M11 M12 M13 Min ...

Page 75

... Mechanical Data and Ordering Information Table 38 identifies the available packages and operating frequencies for the MPC885/MPC880 derivative devices. Table 38. Available MPC885/MPC880 Packages/Frequencies Package Type Plastic ball grid array ZP suffix — Leaded VR suffix — Lead-Free are available as needed Plastic ball grid array CZP suffix — ...

Page 76

... WE2 CS4 CE2_A WE3 WE0 GPL_A0 CS7 CE1_A OE GPL_AB3 CS5 CS2 MPC885/MPC880 PowerQUICC™ Hardware Specifications, Rev NOTE: This is the top view of the device. PC8 PA5 PB17 PA13 PC4 PA11 PE17 PA7 PB19 PC7 PB16 PC13 PE21 PE24 ...

Page 77

... IRQ0 N4 IRQ1 P3 IRQ7 P4 CS[0:5] B14, C14, A15, D14, C16, A16 CS6, CE1_B D15 CS7, CE2_B B16 MPC885/MPC880 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor Table 39. Pin Assignments Pin Number Mechanical Data and Ordering Information Type Bidirectional Three-state Bidirectional Three-state Bidirectional Three-state Bidirectional ...

Page 78

... UTPB_Split2 1 IP_A3, UTPB_Split3 E3 1 IP_A4, UTPB_Split4 D2 1 IP_A5, UTPB_Split5 D1 1 IP_A6, UTPB_Split6 E2 1 IP_A7, UTPB_Split7 D3 MPC885/MPC880 PowerQUICC™ Hardware Specifications, Rev Table 39. Pin Assignments (continued) Pin Number Type Output Output Output Output Output Output Output Output Bidirectional Bidirectional Output Input ...

Page 79

... W15 PA7, CLK1, L1RCLKA, V14 BRGO1, TIN1 PA6, CLK2, TOUT1 U13 PA5, CLK3, L1TCLKA, W13 BRGO2, TIN2 MPC885/MPC880 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor Table 39. Pin Assignments (continued) Pin Number Mechanical Data and Ordering Information Type Bidirectional Three-state Bidirectional Bidirectional ...

Page 80

... PB20, SMRXD2, T13 1 L1CLKOA, TXADDR0 , RXADDR0, PHSEL[0] PB19, MII1-RXD3, RTS4 V13 1 PB18, RXADDR4 , T12 TXADDR4, RTS2, L1ST2 MPC885/MPC880 PowerQUICC™ Hardware Specifications, Rev Table 39. Pin Assignments (continued) Pin Number Type Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional (Optional: open-drain) Bidirectional (Optional: open-drain) ...

Page 81

... PD10, TXD3, TXENB T2 PD9, TXD4, UTPCLK U2 PD8, RXD4, MII-MDC, R3 RMII-MDC PD7, RTS3, UTPB4 W3 PD6, RTS4, UTPB5 W5 MPC885/MPC880 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor Table 39. Pin Assignments (continued) Pin Number Mechanical Data and Ordering Information Type Bidirectional (Optional: open-drain) Bidirectional (Optional: open-drain) Bidirectional ...

Page 82

... SMTXD1, MII2-TXD3 PE17, TIN3, CLK5, W8 BRGO3, SMSYN1, MII2-TXD2 PE16, L1RCLKB, CLK6, T7 TXD3, MII2-TXCLK, RMII2-REFCLK PE15, TGATE1, W6 MII2-TXD1, RMII2-TXD1 MPC885/MPC880 PowerQUICC™ Hardware Specifications, Rev Table 39. Pin Assignments (continued) Pin Number Type Bidirectional Bidirectional Bidirectional Bidirectional (Optional: open-drain) Bidirectional (Optional: open-drain) ...

Page 83

... F14, F15, G5, G14, H6, H15, J6, J14, K5, K6, K14, L6, L14, L15, M5, M6, M14, N6, N15, P5, P6, P8, P9, P10, P11, P12, P14, P15, R5, R7, R8, R11, R13, R14 N/C N17 1 ESAR mode only. MPC885/MPC880 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor Table 39. Pin Assignments (continued) Pin Number Mechanical Data and Ordering Information Type Bidirectional ...

Page 84

... INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M—1994. 3. MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A. 4. DATUM A, THE SEATING PLANE, IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. Figure 78. Mechanical Dimensions and Bottom Surface Nomenclature of the PBGA Package MPC885/MPC880 PowerQUICC™ Hardware Specifications, Rev Freescale Semiconductor ...

Page 85

... Figure • In Table • In Figure MPC885/MPC880 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor Table 40. Document Revision History Changes 9, for reset timings B29f and B29g added footnote indicating that the formula only applies 6, changed all reference voltage measurement points from 0.2 and 0 50% level. ...

Page 86

... Document Revision History THIS PAGE INTENTIONALLY LEFT BLANK MPC885/MPC880 PowerQUICC™ Hardware Specifications, Rev Freescale Semiconductor ...

Page 87

... THIS PAGE INTENTIONALLY LEFT BLANK MPC885/MPC880 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor Document Revision History 87 ...

Page 88

... Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power ...

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