mpc9331 Integrated Device Technology, mpc9331 Datasheet

mpc9331

Manufacturer Part Number

mpc9331

Description

3.3v 1 6 Lvcmos Pll Clock Generator

Manufacturer

Integrated Device Technology

Datasheet

1.MPC9331.pdf (12 pages)

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IDT™ 3.3 V 1:6 LVCMOS PLL Clock Generator

Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc

3.3 V 1:6 LVCMOS PLL Clock

Generator

Freescale Semiconductor

Technical Data

3.3 V 1:6 LVCMOS PLL Clock

Generator

for high performance low-skew clock distribution in mid-range to high-performance

telecom, networking, and computing applications. With output frequencies up to

240 MHz and output skews less than 150 ps, the device meets the needs of most

the demanding clock applications. The MPC9331 is specified for the temperature

range of 0°C to +70°C.

Features

•

Functional Description

MPC9331 requires either the selection of internal PLL feedback or the connection of one of the device outputs to the feedback

input to close the PLL feedback path in external feedback mode. The reference clock frequency and the divider for the feedback

path determine the VCO frequency. Both must be selected to match the VCO frequency range. In external PLL feedback

configuration and with the available post-PLL dividers (divide-by-2, divide-by-4, and divide-by-6), the internal VCO of the

MPC9331 is running at either 2x, 4x, 6x, 8x, or 12x of the reference clock frequency. In internal feedback configuration

(divide-by-8) the internal VCO is running 8x of the reference frequency. The frequency of the QA, QB, QC output banks is a

division of the VCO frequency and can be configured independently for each output bank using the FSELA, FSELB, and FSELC

pins, respectively. The available output to input frequency ratios are 4x, 3x, 2x, 1x, 4/3x, 3/2x, 2/3x, x/2, x/3, or x/4.

control selects the PLL bypass configuration for test and diagnosis. In this configuration, the selected input reference clock is

routed directly to the output dividers bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency

specification and all other PLL characteristics do not apply. The outputs can be disabled (high-impedance) by deasserting the

OE/MR pin. In the PLL configuration with external feedback selected, deasserting OE/MR causes the PLL to loose lock due to

missing feedback signal presence at FB_IN. Asserting OE/MR will enable the outputs and close the phase locked loop, enabling

the PLL to recover to normal operation. The MPC9331 output clock stop control allows the outputs to start and stop

synchronously in logic low state, without the potential generation of runt pulses.

LVCMOS except signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 Ω

transmission lines. For series terminated transmission lines, each of the MPC9331 outputs can drive one or two traces giving the

devices an effective fanout of 1:12. The device is packaged in a 7x7 mm

The MPC9331 is a 3.3 V compatible, 1:6 PLL based clock generator targeted

The MPC9331 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the

The REF_SEL pin selects the differential LVPECL or the LVCMOS compatible input as the reference clock signal. The PLL_EN

The MPC9331 is fully 3.3 V compatible and requires no external loop filter components. The inputs (except PCLK) accept

1:6 PLL based low-voltage clock generator

3.3 V power supply

Generates clock signals up to 240 MHz

Maximum output skew of 150 ps

Differential LVPECL reference clock input

Alternative LVCMOS PLL reference clock input

Internal and external PLL feedback

Supports zero-delay operation in external feedback mode

PLL multiplies the reference clock by 4x, 3x, 2x, 1x, 4/3x, 3/2x, 2/3x, x/2, x/3

or x/4

Synchronous output clock stop in logic low eliminates output runt pulses

Power_down feature reduces output clock frequency

Drives up to 12 clock lines

32-lead LQFP packaging

32-lead Pb-free Package Available

Ambient temperature range 0°C to +70°C

Internal Power-Up Reset

Pin and function compatible to the MPC931

32-lead LQFP package.

32-LEAD LQFP PACKAGE

CLOCK GENERATOR

3.3 V LVCMOS 1:6

Pb-FREE PACKAGE

MPC9331

LOW VOLTAGE

CASE 873A-03

FA SUFFIX

AC SUFFIX

DATA SHEET

Rev. 7, 1/2005

MPC9331

Related parts for mpc9331

mpc9331 Summary of contents

Page 1

... The MPC9331 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the MPC9331 requires either the selection of internal PLL feedback or the connection of one of the device outputs to the feedback input to close the PLL feedback path in external feedback mode. The reference clock frequency and the divider for the feedback path determine the VCO frequency ...

Page 2

... QA1 27 QA0 MPC9331 power supply pin. Please see application section for details. CC_PLL Figure 2. MPC9331 32-Lead Package Pinout (Top View) 2 Bank A ÷2 0 CLK Stop ÷4 1 ÷6 Bank B 0 CLK Stop 1 Bank C 0 CLK Stop 1 3 ...

Page 3

... During reset in external feedback configuration, the PLL feedback loop is open. The VCO is tied to its lowest frequency. The MPC9331 requires reset after any loss of PLL lock. Loss of PLL lock may occur when the external feedback path is interrupted. The length of the reset pulse should be greater than one reference clock cycle (CCLK or PCLK) ...

Page 4

... CMR and the input swing lies within the V 2. The MPC9331 is capable of driving 50 Ω transmission lines on the incident edge. Each output drives one 50 Ω parallel terminated transmission line to a termination voltage Inputs have pull-down or pull-up resistors affecting the input current. ...

Page 5

... Normal AC operation is obtained when the crosspoint is within the V CMR and the input swing lies within the V 5. Calculation of reference duty cycle limits The MPC9331 will operate with input rise/fall times up to 3.0 ns, but the AC characteristics, specifically t be guaranteed are within the specified range. ...

Page 6

... QAx (÷2) QBx (÷4) QCx (÷6) Programming the MPC9331 The MPC9331 supports output clock frequencies from 16.67 to 240 MHz. Different feedback and output divider configurations can be used to achieve the desired input to output frequency relationship. The feedback frequency and divider should be used to situate the VCO in the frequency lock range between 200 and 480 MHz for stable and optimal operation ...

Page 7

... PCLK). 2. QAx connected to FB_IN and FSELA=0, PWR_DN=0. 3. QAx connected to FB_IN and FSELA=1, PWR_DN=0. 4. QCx connected to FB_IN and FSELC=1, PWR_DN=0. Table 10. MPC9331 Example Configurations (External Feedback and PWR_DN = 1) (1) PLL fref FSELA Feedback [MHz] (2) VCO ÷ ...

Page 8

... This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC9331 clock driver. For the series terminated case, however, there current draw, thus the outputs can drive multiple series terminated lines. ...

Page 9

... Time (ns) Figure 5. Single versus Dual Line Termination Waveforms Pulse Generator Z = 50Ω Figure 7. CCLK MPC9331 AC Test Reference for V IDT™ 3.3 V 1:6 LVCMOS PLL Clock Generator Advanced Clock Drivers Devices Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc Freescale Semiconductor + Z ...

Page 10

... JIT(ý for a controlled edge with respect Figure 11. I/O Jitter –1/f | JIT(PER Figure 13. Period Jitter =3 2.4 0.55 Advanced Clock Drivers Devices Freescale Semiconductor NETCOM ÷ GND V CC ÷ GND mean 0 MPC9331 ...

Page 11

... EXACT SHAPE OF EACH CORNER IS OPTIONAL. 8. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.1-mm AND 0.25-mm FROM THE LEAD TIP. MILLIMETERS DIM MIN MAX A 1.40 1.60 A1 0.05 0. 1.35 1.45 b 0.30 0.45 b1 0.30 0.40 c 0.09 0.20 c1 0.09 0.16 D 9.00 BSC D1 7.00 BSC e 0.80 BSC E 9.00 BSC E1 7.00 BSC L 0.50 0.70 L1 1.00 REF q 0˚ 7˚ REF R1 0.08 0.20 R2 0.08 --- S 0.20 REF MPC9331 NETCOM MPC9331 11 ...

Page 12

... MPC92459 MPC9331 PART NUMBERS 900 MHz Low Voltage LVDS Clock Synthesizer 3.3 V 1:6 LVCMOS PLL Clock Generator INSERT PRODUCT NAME AND DOCUMENT TITLE Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. ...

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