mpc9893 Integrated Device Technology, mpc9893 Datasheet

mpc9893

Manufacturer Part Number

mpc9893

Description

3.3v 1 12 Lvcmos Pll Clock Generator

Manufacturer

Integrated Device Technology

Datasheet

1.MPC9893.pdf (13 pages)

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3.3V 1:12 LVCMOS PLL CLOCK GENERATOR

switch and generator specifically designed for redundant clock distribution systems. The

device receives two LVCMOS clock signals and generates 12 phase aligned output

clocks. The MPC9893 is able to detect a failing reference clock signal and to dynamically

switch to a redundant clock signal. The switch from the failing clock to the redundant clock

occurs without interruption of the output clock signal (output clock slews to alignment). The

phase bump typically caused by a clock failure is eliminated.

configurable to support the different clock frequencies.

networking requirements. The device employs a fully differential PLL design to minimize

jitter.

Features

•

Functional Description

generate clock signals from redundant clock sources. The PLL multiplies the input reference clock signal by one, two, three, four or eight.

The frequency-multiplied clock drives six bank A outputs. Six bank B outputs can run at either the same frequency than bank A or at half

of the bank A frequency. Therefore, bank B outputs additionally support the frequency multiplication of the input reference clock by 3÷2

and 1÷2. Bank A and bank B outputs are phase-aligned

also phase-aligned

monitors both clock inputs and indicates a clock failure individually for each clock input. When a false clock signal is detected, the

MPC9893 switches to the redundant clock input, forcing the PLL to slowly slew to alignment and not produce any phase bumps at the

outputs. Both clock inputs are interchangeable, also supporting the switch to a failed clock that was restored. The MPC9893 also provides

a manual mode that allows for user-controlled clock switches.

is fully static in order to distribute low-frequency clocks for system test and diagnosis. Outputs of the MPC9893 can be disabled (high-im-

pedance tristate) to isolate the device from the system. Applying output disable also resets the MPC9893. On power-up this reset function

needs to be applied for correct operation of the circuitry. Please see the application section for power-on sequence recommendations.

1. At coincident rising edges.

IDT™ / ICS™ 3.3V 1:12 LVCMOS PLL CLOCK GENERATOR

The MPC9893 is a 2.5 V and 3.3 V compatible, PLL based intelligent dynamic clock

The device offers 12 low skew clock outputs organized into two output banks, each

The extended temperature range of the MPC9893 supports telecommunication and

The MPC9893 is a 3.3 V or 2.5 V compatible PLL clock driver and clock generator. The clock generator uses a fully integrated PLL to

The PLL bypass of the MPC9893 disables the IDCS and PLL-related specifications do not apply. In PLL bypass mode, the MPC9893

The device is packaged in a 7x7 mm

12-output LVCMOS PLL clock generator

2.5 V and 3.3 V compatible

IDCS - on-chip intelligent dynamic clock switch

Automatically detects clock failure

Smooth output phase transition during clock failover switch

7.5 – 200 MHz output frequency range

LVCMOS compatible inputs and outputs

External feedback enables zero-delay configurations

Supports networking, telecommunications and computer applications

Output enable/disable and static test mode (PLL bypass)

Low skew characteristics: maximum 50 ps output-to-output (within bank)

48-lead LQFP package

48-lead Pb-free package available

Ambient operating temperature range of -40 to 85°C

(1)

to the selected input reference clock, providing virtually zero-delay capability. The integrated IDCS continuously

48-lead LQFP package.

(1)

. Due to the external PLL feedback, the clock signals of both output banks are

2.5 V AND 3.3 V IDCS AND

PLL CLOCK GENERATOR

48-LEAD LQFP PACKAGE

MPC9893

Pb-FREE PACKAGE

MPC9893

LOW VOLTAGE

CASE 932-03

FA SUFFIX

AE SUFFIX

SCALE 2:1

REV. 7 MARCH 3, 2008

MPC9893

Related parts for mpc9893

mpc9893 Summary of contents

Page 1

... Ambient operating temperature range of -40 to 85°C Functional Description The MPC9893 2.5 V compatible PLL clock driver and clock generator. The clock generator uses a fully integrated PLL to generate clock signals from redundant clock sources. The PLL multiplies the input reference clock signal by one, two, three, four or eight. ...

Page 2

... MPC9893 Figure 2. MPC9893 48-Lead Pinout (Top View Data Generator D Q GND 24 23 QB0 QB1 GND 20 QB2 19 18 QB3 V ...

Page 3

... Please see the application CC_PLL 1 PLL bypassed and IDCS disabled. The VCO output is replaced by the reference clock signal fref. The MPC9893 is in manual mode. Automatic clock switch mode. IDCS enabled. Clock failure detection and output flags ALARM0, ALARM1, CLK_IND are enabled. IDCS overrides REF_SEL on a clock failure. ...

Page 4

... Unit ÷ 4.0 pF Max Unit ±20 mA ±50 mA °C 125 MPC9893 REV. 7 MARCH 3, 2008 (1) QFB REF f 8 REF f 6 REF f 8 REF f 4 REF f 16 REF f 8 REF f 4 REF Condition Per output Inputs ...

Page 5

... Maximum Quiescent Supply Current CC V Output Termination Voltage TT 1. The MPC9893 is capable of driving 50 Ω transmission lines on the incident edge. Each output drives one 50 Ω parallel terminated transmission line to a termination voltage of V output. IDT™ / ICS™ 3.3V 1:12 LVCMOS PLL CLOCK GENERATOR = 3.3 V ± 5 – ...

Page 6

... 225 ps See applications 425 ps section 150 ps See applications 250 ps section See applications 40 ps section 0.8-4.0 MHz 10 ms APPLICATIONS INFORMATION for more information MPC9893 REV. 7 MARCH 3, 2008 Condition ...

Page 7

... AC and DC specification for the input reference clock. A loss of clock is detected if as well as the loss of both clocks. In the case of both clocks lost, the MPC9893 will set the alarm flags and the PLL will stall. The MPC9893 does not monitor and detect changes in the input frequency ...

Page 8

... In the following example calculation jitter confidence factor of 99.7% (± 3σ) is assumed, resulting in a worst case timing uncertainty from the common clock input to any MPC9893 output of –275 ps to +265 ps relative to the reference clock input CLK0/1: t SK(PP) ...

Page 9

... MPC9893 3.3V 1:12 LVCMOS PLL CLOCK GENERATOR The I/O (Phase) jitter of the MPC9893 depends on the internal VCO frequency and the PLL feedback divider configuration. A high internal VCO frequency and a low PLL feedback divider result in lower I/O jitter than the jitter limits in the AC characteristics (Table 8). When calculating the part-to-part skew, ...

Page 10

... Figure 9 show the simulation results of an output driving a single line versus two lines. In both cases the drive capability of the MPC9893 output buffer is more than sufficient to drive 50 Ω transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43 ps exists between the two differently loaded outputs ...

Page 11

... Figure 15. I/O Jitter T JIT(PER The deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles Figure 17. Period Jitter 2.4 1.8 0.55 0.6 MPC9893 V CC ÷ GND ÷ GND , static phase = |T –T mean mean in a random sample ...

Page 12

... G 0.500 BSC H 0.050 0.150 J 0.090 0.200 K 0.500 0.700 L 0˚ 7˚ M 12˚ REF N 0.090 0.160 P 0.250 BSC R 0.150 0.250 S 9.000 BSC S1 4.500 BSC V 9.000 BSC V1 4.500 BSC W 0.200 REF AA 1.000 REF R L˚ MPC9893 REV. 7 MARCH 3, 2008 ...

Page 13

... MPC9893 3.3V 1:12 LVCMOS PLL CLOCK GENERATOR Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) © ...

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