MT48LC64M4A2 Micron Technology, MT48LC64M4A2 Datasheet

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MT48LC64M4A2

Manufacturer Part Number
MT48LC64M4A2
Description
(MT48Lxxxx) SYNCHRONOUS DRAM
Manufacturer
Micron Technology
Datasheet

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SYNCHRONOUS
DRAM
FEATURES
• PC66-, PC100-, and PC133-compliant
• Fully synchronous; all signals registered on
• Internal pipelined operation; column address can
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto Precharge, includes CONCURRENT AUTO
• Self Refresh Mode
• 64ms, 8,192-cycle refresh
• LVTTL-compatible inputs and outputs
• Single +3.3V ±0.3V power supply
OPTIONS
• Configurations
• WRITE Recovery (
• Package/Pinout
• Timing (Cycle Time)
• Self Refresh
• Operating Temperature
NOTE: 1. Refer to Micron Technical Note TN-48-05.
256Mb: x4, x8, x16 SDRAM
256MSDRAM_E.p65 – Rev. E; Pub. 3/02
positive edge of system clock
be changed every clock cycle
PRECHARGE, and Auto Refresh Modes
64 Meg x 4
32 Meg x 8
16 Meg x 16 ( 4 Meg x 16 x 4 banks)
t
54-pin TSOP II OCPL
60-ball FBGA (8mm x 16mm) (x4, x8)
54-ball FBGA (8mm x 14mm) (x16 only)
7.5ns @ CL = 2 (PC133)
7.5ns @ CL = 3 (PC133)
Standard
Low power
Commercial (0
Industrial (-40
WR = “2 CLK”
2. Off-center parting line.
3. Consult Micron for availability.
4. Not available in x16 configuration.
5. Actual FBGA part marking shown on page 58.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
MT48LC16M16A2TG-75
( 8 Meg x 8
(16 Meg x 4
1
o
o
C to +85
C to +70
Part Number Example:
t
WR)
2
(400 mil)
o
o
C)
C)
x 4 banks)
x 4 banks)
MARKING
16M16
None
64M4
32M8
None
FB
FG
-7E
-75
TG
IT
A2
L
3
4, 5
3
3
1
*CL = CAS (READ) latency
KEY TIMING PARAMETERS
MT48LC64M4A2 – 16 Meg x 4
MT48LC32M8A2 – 8 Meg x 8
MT48LC16M16A2 – 4 Meg x 16 x 4 banks
For the latest data sheet, please refer to the Micron Web site:
www.micron.com/dramds
Note:
GRADE
Configuration
Refresh Count
Row Addressing
Bank Addressing
Column Addressing
SPEED
-75
-7E
-7E
-75
DQ0
DQ1
x4
NC
NC
NC
NC
NC
NC
NC
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DQ0
DQ1
DQ2
DQ3
The # symbol indicates signal is active LOW. A dash (–)
indicates x8 and x4 pin function is same as x16 pin function.
x8
NC
NC
NC
NC
NC
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PIN ASSIGNMENT (Top View)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
FREQUENCY CL = 2* CL = 3*
DQML
V
V
CAS#
RAS#
x16
VssQ
VssQ
WE#
133 MHz
133 MHz
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
143 MHz
100 MHz
DD
DD
BA0
BA1
A10
V
V
V
CS#
CLOCK
A0
A1
A2
A3
DD
DD
DD
Q
Q
16 Meg x 4 x 4 banks 8 Meg x 8 x 4 banks 4 Meg x 16 x 4 banks
2K (A0–A9, A11)
64 Meg x 4
8K (A0–A12)
4 (BA0, BA1)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
8K
54-Pin TSOP
256Mb: x4, x8, x16
5.4ns
ACCESS TIME
6ns
32 Meg x 8
8K (A0–A12)
4 (BA0, BA1)
1K (A0–A9)
5.4ns
5.4ns
8K
x 4 banks
x 4 banks
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
SETUP
1.5ns
1.5ns
TIME
1.5ns
1.5ns
©2002, Micron Technology, Inc.
x16
Vss
DQ15
VssQ
DQ14
DQ13
V
DQ12
DQ11
VssQ
DQ10
DQ9
V
DQ8
Vss
NC
DQMH
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
Vss
SDRAM
DD
DD
Q
Q
16 Meg x 16
8K (A0–A12)
512 (A0–A8)
4 (BA0, BA1)
x8
-
DQ7
-
NC
DQ6
-
NC
DQ5
-
NC
DQ4
-
NC
-
-
DQM
-
-
-
-
-
-
-
-
-
-
-
8K
HOLD
0.8ns
0.8ns
TIME
0.8ns
0.8ns
-
NC
-
NC
DQ3
-
NC
NC
-
NC
DQ2
-
NC
-
-
DQM
-
-
-
-
-
-
-
-
-
-
-
x4

Related parts for MT48LC64M4A2

MT48LC64M4A2 Summary of contents

Page 1

... SDRAM 256MSDRAM_E.p65 – Rev. E; Pub. 3/02 PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. MT48LC64M4A2 – 16 Meg x 4 MT48LC32M8A2 – 8 Meg x 8 MT48LC16M16A2 – 4 Meg banks For the latest data sheet, please refer to the Micron Web site: www ...

Page 2

... Vss VssQ DQ6 NC VssQ DQ4 NC Vss DQM CK CKE Vss Depopulated Balls Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc DQ0 VssQ DQ1 NC DQ2 DQ3 VssQ NC ...

Page 3

... VssQ DQ1 DQ2 V Q DQ3 DQ4 DD DQ6 V Q DQ5 SS V LDQM DQ7 DD RAS# CAS# WE# BA0 BA1 CS A10 256Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ...

Page 4

... Mb SDRAM PART NUMBERS PART NUMBER ARCHITECTURE MT48LC64M4A2TG 64 Meg x 4 MT48LC64M4A2FB* 64 Meg x 4 MT48LC32M8A2TG 32 Meg x 8 MT48LC32M8A2FB* 32 Meg x 8 MT48LC16M16A2TG 16 Meg x 16 MT48LC16M16A2FG 16 Meg x 16 *Actual FBGA part marking shown on page 58. GENERAL DESCRIPTION The 256Mb SDRAM is a high-speed CMOS, dynamic random-access memory 268,435,456 bits ...

Page 5

... Write – With Auto Precharge ........................... 53 Single Write - Without Auto Precharge ......... 54 Single Write - With Auto Precharge ................ 55 Alternating Bank Write Accesses ................... 56 Write – Full-Page Burst .................................... 57 Write – DQM Operation ................................... 58 Micron Technology, Inc., reserves the right to change products or specifications without notice. 5 256Mb: x4, x8, x16 SDRAM ...................................................... 31 ........................ 32 .................. 34 © ...

Page 6

... ADDRESS COUNTER/ LATCH 6 256Mb: x4, x8, x16 BANK3 BANK2 BANK1 BANK0 MEMORY 1 ARRAY DATA OUTPUT 4 REGISTER 8192 DATA INPUT 4 2048 REGISTER (x4) COLUMN DECODER Micron Technology, Inc., reserves the right to change products or specifications without notice. SDRAM 1 DQM DQ0- 4 DQ3 ©2002, Micron Technology, Inc. ...

Page 7

... ADDRESS COUNTER/ LATCH 7 256Mb: x4, x8, x16 BANK3 BANK2 BANK1 BANK0 MEMORY 1 ARRAY DATA OUTPUT 8 REGISTER 8192 DATA INPUT 8 1024 REGISTER (x8) COLUMN DECODER Micron Technology, Inc., reserves the right to change products or specifications without notice. SDRAM 1 DQM DQ0- 8 DQ7 ©2002, Micron Technology, Inc. ...

Page 8

... LATCH 8 256Mb: x4, x8, x16 BANK3 BANK2 BANK1 BANK0 MEMORY 2 ARRAY DATA OUTPUT 16 REGISTER 8192 DATA 16 INPUT 512 REGISTER (x16) COLUMN DECODER Micron Technology, Inc., reserves the right to change products or specifications without notice. SDRAM 2 DQML, DQMH DQ0- 16 DQ15 ©2002, Micron Technology, Inc. ...

Page 9

... Supply DQ Power: Isolated DQ power to the die for improved noise immunity. Supply DQ Ground: Isolated DQ ground to the die for improved noise immunity. Supply Power Supply: +3.3V ±0.3V. Supply Ground. 9 256Mb: x4, x8, x16 SDRAM DESCRIPTION Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ...

Page 10

... DQ Power: Provide isolated power to DQs for improved noise immunity. Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity. Supply Power Supply: Voltage dependant on option. Supply Ground. Micron Technology, Inc., reserves the right to change products or specifications without notice. 10 256Mb: x4, x8, x16 SDRAM DESCRIPTION ©2002, Micron Technology, Inc. ...

Page 11

... DQ Power: Provide isolated power to DQs for improved noise immunity. Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity. Supply Power Supply: Voltage dependant on option. Supply Ground. 11 256Mb: x4, x8, x16 SDRAM DESCRIPTION Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ...

Page 12

... Full-page bursts wrap within the page if the boundary is reached. 12 256Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ...

Page 13

... For a burst length of one, A0-A9, A11 (x4); A0-A9 (x8); or A0-A8 (x16) select the unique column to be accessed, and mode register bit M3 is ignored. Micron Technology, Inc., reserves the right to change products or specifications without notice. SDRAM 0-1 1-0 0-1-2-3 ...

Page 14

... LZ D OUT t AC DON’T CARE UNDEFINED 14 256Mb: x4, x8, x16 SDRAM Table 2 CAS Latency ALLOWABLE OPERATING FREQUENCY (MHz) CAS CAS LATENCY = 2 LATENCY = 3 133 100 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. 143 133 ...

Page 15

... – – – – L – – – – H Micron Technology, Inc., reserves the right to change products or specifications without notice. 15 SDRAM ADDR DQs NOTES Bank/Row X 3 Bank/Col X 4 Bank/Col Valid 4 X Active Code X 5 ...

Page 16

... PRECHARGE command was issued at the earliest possible time, as described for each burst type in the Operation section of this data sheet. Micron Technology, Inc., reserves the right to change products or specifications without notice. 16 SDRAM t RP) after the PRECHARGE RP) is completed. This is © ...

Page 17

... Upon exiting the self refresh mode, AUTO REFRESH commands must be issued every 7.81µs or less as both SELF REFRESH and AUTO REFRESH utilize the row refresh counter. Micron Technology, Inc., reserves the right to change products or specifications without notice. 17 SDRAM ©2002, Micron Technology, Inc. ...

Page 18

... CAS# WE# ROW ADDRESS BANK ADDRESS Figure 3 Activating a Specific Row in a Specific Bank READ or NOP WRITE DON’T CARE CK < < < < < RCD (MIN)/ Micron Technology, Inc., reserves the right to change products or specifications without notice. SDRAM ©2002, Micron Technology, Inc. ...

Page 19

... OUT t AC CAS Latency = READ NOP NOP CAS Latency = 3 Figure 6 CAS Latency Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc NOP OUT DON’T CARE UNDEFINED ...

Page 20

... OUT READ NOP NOP NOP cycles BANK, COL OUT OUT OUT DON’T CARE Micron Technology, Inc., reserves the right to change products or specifications without notice. SDRAM D OUT b ©2002, Micron Technology, Inc. ...

Page 21

... Random READ Accesses 21 256Mb: x4, x8, x16 SDRAM T4 T5 NOP NOP D D OUT OUT NOP NOP NOP OUT OUT OUT DON’T CARE Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ...

Page 22

... A CAS latency of three is used for illustration. The READ command may be to any bank, and the WRITE command may be to any bank. Figure 10 READ to WRITE With Extra Clock Cycle Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. T5 WRITE BANK, ...

Page 23

... OUT NOP NOP ACTIVE cycles BANK a, ROW OUT OUT OUT DON’T CARE Micron Technology, Inc., reserves the right to change products or specifications without notice. SDRAM RP is met. Note ©2002, Micron Technology, Inc. ...

Page 24

... T5 T6 NOP NOP D D OUT OUT NOP NOP NOP cycles OUT OUT OUT DON’T CARE Micron Technology, Inc., reserves the right to change products or specifications without notice. SDRAM ©2002, Micron Technology, Inc. ...

Page 25

... ADDRESS COL NOTE: DQM is LOW. Each WRITE command may be to any bank. Figure 15 WRITE to WRITE Micron Technology, Inc., reserves the right to change products or specifications without notice. SDRAM T3 NOP T2 WRITE BANK, COL ©2002, Micron Technology, Inc. ...

Page 26

... BANK BANK all) COL Figure 18 WRITE to PRECHARGE Micron Technology, Inc., reserves the right to change products or specifications without notice. SDRAM met. The T5 T6 ACTIVE NOP BANK a, ROW t RP NOP ACTIVE BANK a, ROW DON’T CARE ...

Page 27

... CKS t CKS ( ( ) ) ( ( ) ) NOP NOP ( ( ) ) Input buffers gated off Exit power-down mode. Figure 21 Power-Down Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. t RP) af- ACTIVE t RCD t RAS t RC DON’T CARE ...

Page 28

... READ NOP NOP NOP BANK, COL OUT OUT DQM is LOW. Figure 23 Micron Technology, Inc., reserves the right to change products or specifications without notice. SDRAM T5 T6 NOP NOP D D OUT OUT DON’T CARE ©2002, Micron Technology, Inc. ...

Page 29

... Idle BANK BANK n WRITE with Burst of 4 Write-Back BANK m, COL T4. IN DON’T CARE Micron Technology, Inc., reserves the right to change products or specifications without notice. SDRAM ©2002, Micron Technology, Inc. ...

Page 30

... Interrupt Burst, Write-Back Precharge BANK BANK BANK m Write-Back WRITE with Burst DON’T CARE Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. SDRAM met, ...

Page 31

... AUTO REFRESH VALID See Truth Table 3 was the state of CKE at the previous clock edge. n result of COMMAND n t XSR period. Micron Technology, Inc., reserves the right to change products or specifications without notice. 31 256Mb: x4, x8, x16 SDRAM ACTION NOTES n Maintain Power-Down Maintain Self Refresh ...

Page 32

... SDRAM t XSR has been t RCD has been met. No data bursts/accesses and met. Once t RCD is met. Once Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. NOTES ...

Page 33

... Does not affect the state of the bank and acts as a NOP to that bank. 256Mb: x4, x8, x16 SDRAM 256MSDRAM_E.p65 – Rev. E; Pub. 3/02 t MRD is met, the SDRAM will be in the all banks idle state. Micron Technology, Inc., reserves the right to change products or specifications without notice. 33 256Mb: x4, x8, x16 SDRAM met ...

Page 34

... RP is met, the bank will be in the idle state. 34 256Mb: x4, x8, x16 SDRAM t XSR has been met (if the t RCD has been met. No data bursts/accesses and no Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. NOTES ...

Page 35

... WRITE to bank m (Figure 27). 256Mb: x4, x8, x16 SDRAM 256MSDRAM_E.p65 – Rev. E; Pub. 3/ begins when the READ to bank m is registered. The last valid WRITE to bank n Micron Technology, Inc., reserves the right to change products or specifications without notice. 35 256Mb: x4, x8, x16 SDRAM met, where ...

Page 36

... 285 270 3.5 3 2.5 2 1.5 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc µA µ 18, 19 12, 19 18, 19 12, 18, 19, 32 ...

Page 37

... REF 64 t RFC RRD 0.3 1 CLK+ 1 CLK+ 7ns 7.5ns 14 t XSR 67 Micron Technology, Inc., reserves the right to change products or specifications without notice. 37 SDRAM MAX UNITS NOTES MAX UNITS NOTES -75 MAX ...

Page 38

... PED t DQD t DQM t DQZ t DWD t DAL t DPL t BDL t CDL t RDL t MRD ROH( ROH(2) Micron Technology, Inc., reserves the right to change products or specifications without notice. 38 SDRAM -7E -75 UNITS NOTES ...

Page 39

... RP) begins 7ns for -7E and 7.5ns for -75 AC for -75/- with no load is 4.6ns and 7.5ns; for -7E and CK = 7.5ns. RFC (MIN) else CKE is LOW. The I Micron Technology, Inc., reserves the right to change products or specifications without notice. SDRAM under- IL 3ns. 6 limit is actu- DD © ...

Page 40

... Program Mode Register AUTO REFRESH -7E -75 MIN MAX MIN 1.5 1.5 0.8 0.8 1.5 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. SDRAM ACTIVE ROW ROW BANK DON’T CARE UNDEFINED MAX UNITS ©2002, Micron Technology, Inc. ...

Page 41

... All banks idle -7E -75 MIN MAX MIN 7.5 10 0.8 0.8 1.5 1.5 0.8 0.8 1.5 1.5 Micron Technology, Inc., reserves the right to change products or specifications without notice. SDRAM ACTIVE ROW ROW BANK DON’T CARE MAX UNITS ©2002, Micron Technology, Inc. ...

Page 42

... OUT OUT -7E -75 MIN MAX MIN 1.5 1.5 0.8 0.8 1.5 1.5 0.8 0.8 1.5 1.5 5.4 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. SDRAM T9 NOP OUT DON’T CARE UNDEFINED MAX UNITS 5 ©2002, Micron Technology, Inc. ...

Page 43

... AUTO NOP NOP ACTIVE ( ( REFRESH ) ) ( ( ) ) ( ( ) ) ( ( ) ) ROW ( ( ) ) ( ( ) ) ROW ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) t RFC -7E -75 MIN MAX MIN MAX 0.8 0.8 1.5 1.5 0.8 0.8 1.5 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. BANK DON’T CARE UNITS ...

Page 44

... Exit self refresh mode (Restart refresh time base) -7E -75 MIN MAX MIN 1.5 1.5 0.8 0.8 1.5 1.5 37 120,000 44 120,000 Micron Technology, Inc., reserves the right to change products or specifications without notice. SDRAM AUTO DON’T CARE MAX UNITS ©2002, Micron Technology, Inc. ...

Page 45

... MIN MAX MIN MAX 0.8 0.8 1.5 1.5 5.4 5.4 5 120,000 44 120,000 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. T8 ACTIVE ROW ROW BANK DON’T CARE UNDEFINED UNITS ...

Page 46

... MIN MAX MIN MAX 0.8 0.8 1.5 1.5 5.4 5.4 5 120,000 44 120,000 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. T8 ACTIVE ROW ROW BANK DON’T CARE UNDEFINED UNITS ...

Page 47

... BANK( -7E -75 MIN MAX MIN 0.8 0.8 1.5 1.5 5.4 5 120,000 Micron Technology, Inc., reserves the right to change products or specifications without notice. SDRAM T8 NOP DON’T CARE UNDEFINED MAX UNITS 120,000 ©2002, Micron Technology, Inc. ...

Page 48

... OUT -7E -75 MIN MAX MIN MAX 0.8 0.8 1.5 1.5 5.4 5.4 5 120,000 44 120,000 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. T8 NOP DON’T CARE UNDEFINED UNITS ...

Page 49

... MAX 0.8 0.8 1.5 1 120,000 44 120,000 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. T8 ACTIVE ROW ROW BANK OUT t RCD - BANK 0 DON’T CARE UNDEFINED UNITS ...

Page 50

... Full page completed 3 -7E -75 MIN MAX MIN 1.5 1.5 0.8 0.8 1.5 1.5 5.4 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. SDRAM NOP NOP m+1 OUT t HZ DON’T CARE UNDEFINED MAX UNITS 5 ...

Page 51

... OUT OUT -7E -75 MIN MAX MIN MAX 1.5 1.5 0.8 0.8 1.5 1.5 5.4 5.4 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. T8 NOP DON’T CARE UNDEFINED UNITS ...

Page 52

... -7E -75 MIN MAX MIN 1.5 1.5 0.8 0.8 1.5 1.5 37 120,000 Micron Technology, Inc., reserves the right to change products or specifications without notice. SDRAM T9 ACTIVE ROW ROW BANK DON’T CARE MAX UNITS 120,000 ©2002, Micron Technology, Inc. ...

Page 53

... MAX MIN 1.5 1.5 0.8 0.8 1.5 1.5 37 120,000 CLK + 1 CLK + 7ns 7.5ns Micron Technology, Inc., reserves the right to change products or specifications without notice. SDRAM T9 ACTIVE ROW ROW BANK DON’T CARE MAX UNITS 120,000 – ©2002, Micron Technology, Inc. ...

Page 54

... SINGLE BANK BANK BANK t RP -7E -75 MIN MAX MIN 1.5 1.5 0.8 0.8 1.5 1.5 37 120,000 44 120,000 Micron Technology, Inc., reserves the right to change products or specifications without notice. SDRAM T8 NOP DON’T CARE MAX UNITS ©2002, Micron Technology, Inc. ...

Page 55

... ROW BANK t RP DON’T CARE -7E -75 MIN MAX MIN MAX 1.5 1.5 0.8 0.8 1.5 1.5 37 120,000 44 120,000 CLK + 1 CLK + 7ns 7.5ns Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. T9 NOP UNITS – ...

Page 56

... MAX MIN 1.5 1.5 0.8 0.8 1.5 1.5 37 120,000 Note 2 Note 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. SDRAM T9 ACTIVE ROW ROW BANK RCD - BANK BANK 1 DON’T CARE MAX UNITS ns ns ...

Page 57

... Can use BURST TERMINATE command to stop. Full page completed -7E -75 MIN MAX MIN MAX 1.5 1.5 0.8 0.8 1.5 1.5 0.8 0.8 1.5 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc NOP 2, 3 DON’T CARE UNITS ...

Page 58

... T5 T6 NOP NOP NOP -7E -75 MIN MAX MIN 1.5 1.5 0.8 0.8 1.5 1.5 0.8 0.8 1.5 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. SDRAM T7 NOP DON’T CARE MAX UNITS ©2002, Micron Technology, Inc. ...

Page 59

... Rev. E; Pub. 3/02 54-PIN PLASTIC TSOP (400 mil) .71 .10 (2X) 2.80 11.86 11.66 10.24 10.08 .18 .13 .10 1.2 MAX MIN 59 256Mb: x4, x8, x16 SDRAM SEE DETAIL A .20 .05 .60 .40 DETAIL A Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. .25 GAUGE PLANE .80 TYP ...

Page 60

... View) 60 256Mb: x4, x8, x16 0.205 MAX. 2.40 ± 0.05 CTR 0.80 (TYP) PIN #1 ID 11.20 0.80 (TYP) 1.20 MAX. Micron Technology, Inc., reserves the right to change products or specifications without notice. SDRAM ©2002, Micron Technology, Inc. ...

Page 61

... SDRAM 1.00 MAX PIN A1 ID MOLD COMPOUND: EPOXY NOVOLAC SUBSTRATE: PLASTIC LAMINATE SOLDER BALL MATERIAL: EUTECTIC 63% Sn, 37 62% Sn, 36% Pb, 2%Ag SOLDER BALL PAD: Ø .27mm Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ...

Page 62

... The abbreviated device marks are cross referenced to Micron part num- bers in Table 1. CROSS REFERENCE FOR FBGA DEVICE MARKING PART NUMBER ARCHITECTURE MT48LC64M4A2FB-75 64 Meg x 4 MT48LC64M4A2FB-7E 64 Meg x 4 MT48LC32M8A2FB-75 32 Meg x 8 MT48LC32M8A2FB-7E 32 Meg x 8 MT48LC16M16A2FG-75 16 Meg x 16 MT48LC16M16A2FG-7E 16 Meg x 16 8000 S ...

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