MX25L4005 Macronix International, MX25L4005 Datasheet

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MX25L4005

Manufacturer Part Number
MX25L4005
Description
4M-BIT [x 1] CMOS SERIAL FLASH
Manufacturer
Macronix International
Datasheet

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www.DataSheet4U.com
GENERAL
• Serial Peripheral Interface (SPI) compatible -- Mode 0
• 4,194,304 x 1 bit structure
• 128 Equal Sectors with 4K byte each
• 8 Equal Blocks with 64K byte each
• Single Power Supply Operation
• Latch-up protected to 100mA from -1V to Vcc +1V
• Low Vcc write inhibit is from 1.5V to 2.5V
PERFORMANCE
• High Performance
• Low Power Consumption
• Minimum 100,000 erase/program cycles
P/N: PM1236
FEATURES
and Mode 3
- Any Sector can be erased individually
- Any Block can be erased individually
- 2.7 to 3.6 volt for read, erase, and program operations
- Fast access time: 70MHz serial clock (15pF + 1TTL
Load) and 66MHz serial clock (30pF + 1TTL Load)
- Fast program time: 1.4ms(typ.) and 5ms(max.)/page
(256-byte per page)
- Fast erase time: 60ms(typ.) and 120ms(max.)/sector
(4K-byte per sector) ; 1s(typ.) and 2s(max.)/block (64K-
byte per block)
- Low active read current: 12mA(max.) at 70MHz,
8mA(max.) at 66MHz and 4mA(max.) at 33MHz
- Low active programming current: 15mA (max.)
- Low active erase current: 15mA (max.)
- Low standby current: 10uA (max.)
- Deep power-down mode 1uA (typical)
1
SOFTWARE FEATURES
• Input Data Format
• Block Lock protection
• Auto Erase and Auto Program Algorithm
• Status Register Feature
• Electronic Identification
HARDWARE FEATURES
• SCLK Input
• SI Input
• SO Output
• WP# pin
• HOLD# pin
• PACKAGE
- 1-byte Command code
-
sector
-
page by an internal algorithm that automatically times
the program pulse widths (Any page to be programed
should have page in the erased state first)
-
- RES command, 1-byte Device ID
-
-
-
-
-
-
-
- 8-land SON (6x5mm)
- All Pb-free devices are RoHS Compliant
- The BP0~BP2 status bit defines the size of the area
to be software protected against Program and Erase
instructions.
Hardware write protection
JEDEC 2-byte Device ID
Serial clock input
Serial Data Input
Serial Data Output
pause the chip without diselecting the chip
8-pin SOP (150mil)
8-pin SOP (200mil)
Automatically programs and verifies data at selected
Automatically erases and verifies data at selected
4M-BIT [x 1] CMOS SERIAL FLASH
MX25L4005
REV. 1.1, SEP. 30, 2005

Related parts for MX25L4005

MX25L4005 Summary of contents

Page 1

... Low active erase current: 15mA (max.) - Low standby current: 10uA (max.) - Deep power-down mode 1uA (typical) • Minimum 100,000 erase/program cycles P/N: PM1236 MX25L4005 4M-BIT [x 1] CMOS SERIAL FLASH SOFTWARE FEATURES • Input Data Format - 1-byte Command code • Block Lock protection ...

Page 2

... GENERAL DESCRIPTION The MX25L4005 is a CMOS 4,194,304 bit serial Flash memory, which is configured as 524,288 x 8 internally. The MX25L4005 feature a serial peripheral interface and soft- ware protocol allowing operation on a simple 3-wire bus. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO) ...

Page 3

... BLOCK DIAGRAM www.DataSheet4U.com SI CS# SCLK P/N: PM1236 Address Generator Memory Array Page Buffer Data Register Y-Decoder SRAM Buffer Mode State HV Logic Machine Generator Clock Generator 3 MX25L4005 Output Sense Amplifier Buffer SO REV. 1.1, SEP. 30, 2005 ...

Page 4

... Release from Deep Powerdown instruction). P/N: PM1236 MX25L4005 • To avoid unexpected changes by system power supply transition, the Power-On Reset and an internal timer (tPUW) can protect the device. • Before the Program, Erase, and Write Status Register execution, instruction length will be checked on follow- ing the clock pulse number to be multiple of eight base ...

Page 5

... P/N: PM1236 Protect level 0 0 (none block blocks blocks blocks (All (All (All) 5 MX25L4005 4Mb None Block 7 Block 6-7 Block 4-7 All All All All REV. 1.1, SEP. 30, 2005 ...

Page 6

... HOLD operation. If Chip Select (CS#) signal goes high during HOLD operation, it has the effect on resetting the internal logic of the device necessary to drive HOLD# signal to high, and then to drive CS# to low for restarting communication with the device. P/N: PM1236 Hold Hold Condition Condition (standard use) (non-standard use) 6 MX25L4005 REV. 1.1, SEP. 30, 2005 ...

Page 7

... Erase) Erase) Program) Power Down Hex B9 Hex D8 Hex C7 Hex AD1 AD1 AD2 AD2 AD3 AD3 7 MX25L4005 WRSR READ Fast Read (write status (read data) (fast read register) data) 01 Hex 03 Hex 0B Hex AD1 AD1 AD2 AD2 AD3 AD3 x ...

Page 8

... P/N: PM1236 Address Range 07FFFFh 070FFFh 06FFFFh 060FFFh 05FFFFh 050FFFh 04FFFFh 040FFFh 03FFFFh 030FFFh 02FFFFh 020FFFh 01FFFFh 010FFFh 00FFFFh 003FFFh 002FFFh 001FFFh 000FFFh 8 MX25L4005 REV. 1.1, SEP. 30, 2005 ...

Page 9

... During the progress of Write Status Register, Program, Erase operation, to access the memory array is neglected and not affect the current operation of Write Status Register, Program, Erase. P/N: PM1236 SCLK SCLK SI MSB SO 9 MX25L4005 MSB REV. 1.1, SEP. 30, 2005 ...

Page 10

... The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The MXIC Manufacturer ID is C2(hex), the memory type ID is 20(hex) as the first-byte device ID, and the individual device ID of second-byte followings: 13(hex) for MX25L4005. The sequence of issuing RDID instruction is: CS# goes low-> sending RDID instruction code -> 24-bits ID data out on SO -> ...

Page 11

... BP2 BP1 0 the level of the level of the level of protected protected protected block block (note 1) (note 1) (note 1) 11 MX25L4005 bit 2 bit 1 bit 0 BP0 WEL WIP (write enable (write in progress latch) bit) block 1=write enable 1=write operation 0=not write 0=not in write ...

Page 12

... Status Register is Hardware write protected Protected against Page The values in the SRWD, Program, Sector Erase BP2, BP1 and BP0 and Chip Erase bits cannot be changed 12 MX25L4005 Memory Content 1 1 Unprotected Area Ready to accept Page Program and Sector Erase instructions Ready to accept Page ...

Page 13

... Address bits [Am-A12] (Am is the most significant address) select the sector address. The sequence of issuing SE instruction is: CS# goes low -> sending SE instruction code-> 3-byte address on SI -> CS# goes high. (see Figure 19) P/N: PM1236 MX25L4005 13 REV. 1.1, SEP. 30, 2005 ...

Page 14

... If less than 256 bytes are sent to the device, the data is programmed at the request address of the page without effect on other address of the same page. The sequence of issuing PP instruction is: CS# goes low-> sending PP instruction code-> 3-byte address on SI-> at least 1-byte on data on SI-> CS# goes high. (see Figure 18) P/N: PM1236 MX25L4005 14 REV. 1.1, SEP. 30, 2005 ...

Page 15

... CS# must remain to high at least tRES2(max). Once in the standby mode, the device waits to be selected can be receive, decode, and execute instruction. The RDP instruction is for releasing from Deep Power Down Mode. P/N: PM1236 MX25L4005 15 REV. 1.1, SEP. 30, 2005 ...

Page 16

... The Manufacturer and Device IDs can be read continuously, alternating from one to the other. The instruction is completed www.DataSheet4U.com by driving CS# high. Table of ID Definitions: RDID Command RES Command REMS Command P/N: PM1236 manufacturer ID memory type C2 20 manufacturer MX25L4005 memory density 13 electronic ID 12 device ID 12 REV. 1.1, SEP. 30, 2005 ...

Page 17

... POWER-ON STATE www.DataSheet4U.com P/N: PM1236 MX25L4005 17 REV. 1.1, SEP. 30, 2005 ...

Page 18

... During voltage transitions, all pins may overshoot to -0.5V to 4.6V 4.6V or -0.5V for period up to 20ns. 4. All input and output pins may overshoot to VCC+0.5V -0.5V to 4.6V while VCC+0.5V is smaller than or equal to 4.6V. Figure 4. Maximum Positive Overshoot Waveform 20ns 4.6V 3.6V MIN. TYP 18 MX25L4005 20ns MAX. UNIT CONDITIONS 6 pF VIN = VOUT = 0V REV. 1.1, SEP. 30, 2005 ...

Page 19

... Input timing referance level 0.7VCC AC Measurement Level 0.3VCC Note: Input pulse rise and fall time are <5ns DEVICE UNDER TEST CL 6.2K ohm CL=30pF Including jig capacitance (CL=15pF Including jig capacitance for 70MHz) 19 MX25L4005 Output timing referance level 0.5VCC 2.7K ohm +3.3V DIODES=IN3064 OR EQUIVALENT REV. 1.1, SEP. 30, 2005 ...

Page 20

... VCC+0.4 0.4 VCC-0.2 20 MX25L4005 TEST CONDITIONS uA VCC = VCC Max VIN = VCC or GND uA VCC = VCC Max VIN = VCC or GND uA VIN = VCC or GND CS# = VCC uA VIN = VCC or GND CS# = VCC mA f=70MHz SCLK=0.1VCC/0.9VCC, SO=Open mA f=66MHz SCLK=0.1VCC/0.9VCC, SO=Open ...

Page 21

... Value guaranteed by characterization, not 100% tested in production. 3. Expressed as a slew-rate. 4. Only applicable as a constraint for a WRSR instruction when SRWD is set Test condition is shown as Figure 3. P/N: PM1236 for Commercial grade, VCC = 2.7V ~ 3.6V) @33MHz 30pF @70MHz 15pF or @66MHz 30pF 21 MX25L4005 Min. Typ. Max. Unit D.C. 70 MHz (Condition:15pF) ...

Page 22

... Note: 1. These parameters are characterized only. www.DataSheet4U.com INITIAL DELIVERY STATE The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register contains 00h (all Status Register bits are 0). P/N: PM1236 MX25L4005 Min. Max 1.5 ...

Page 23

... Figure 7. Serial Input Timing CS# tCHSL SCLK www.DataSheet4U.com SI SO Figure 8. Write Protect Setup and Hold Timing during WRSR when SRWD=1 WP# tWHSL CS# SCLK SI SO P/N: PM1236 tSLCH tDVCH tCHDX MSB IN High Impedance High Impedance 23 MX25L4005 tSHSL tCHSH tSHCH tCHCL tCLCH LSB IN tSHWL REV. 1.1, SEP. 30, 2005 ...

Page 24

... Figure 9. Hold Timing CS# SCLK www.DataSheet4U.com SO SI HOLD# Figure 10. Output Timing CS# SCLK tCLQV tCLQX SO ADDR.LSB IN SI P/N: PM1236 tHLCH tCHHL tCHHH tHLQZ tCLQV tCLQX 24 MX25L4005 tHHCH tHHQX tCH tCL tSHQZ LSB OUT tQLQH tQHQL REV. 1.1, SEP. 30, 2005 ...

Page 25

... SO CS SCLK Instruction SI High Impedance Instruction Manufacturer Identification High Impedance MSB 25 MX25L4005 Device Identification MSB REV. 1.1, SEP. 30, 2005 ...

Page 26

... SCLK Instruction SI High Impedance Instruction 24-Bit Address MSB High Impedance 26 MX25L4005 Status Register Out MSB Status Register ...

Page 27

... BIT ADDRESS High Impedance Dummy Byte DATA OUT MSB 27 MX25L4005 DATA OUT MSB MSB REV. 1.1, SEP. 30, 2005 ...

Page 28

... Data Byte 2 Data Byte MSB MSB 28 MX25L4005 Data Byte MSB Data Byte 256 ...

Page 29

... Figure 20. Block Erase (BE) Instruction Sequence CS# SCLK SI Note: BE instruction D8(hex). P/N: PM1236 Instruction 24 Bit Address MSB Instruction 24 Bit Address 23 22 MSB 29 MX25L4005 REV. 1.1, SEP. 30, 2005 ...

Page 30

... Instruction Instruction 3 Dummy Bytes MSB 30 MX25L4005 Stand-by Mode Deep Power-down Mode RES2 0 Electronic Signature Out MSB Deep Power-down Mode Stand-by Mode REV ...

Page 31

... High Impedance ADD ( Manufacturer MSB 31 MX25L4005 t RES1 Stand-by Mode Device MSB MSB REV. 1.1, SEP. 30, 2005 ...

Page 32

... Figure 26. Power-up Timing (max (min) www.DataSheet4U.com V WI P/N: PM1236 Program, Erase and Write Commands are Rejected by the Device Chip Selection Not Allowed tVSL Reset State of the Device tPUW 32 MX25L4005 Read Access allowed Device fully accessible time REV. 1.1, SEP. 30, 2005 ...

Page 33

... For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer to "AC CHARACTERISTICS" table. P/N: PM1236 tCHSL tSLCH tDVCH tCHDX MSB IN High Impedance Figure A. AC Timing at Device Power-Up Notes 1 33 MX25L4005 tSHSL tCHSH tSHCH tCHCL tCLCH LSB IN Min. Max. Unit 0.5 500000 us/V ...

Page 34

... Input Voltage with respect to GND on ACC Input Voltage with respect to GND on all power pins, SI, CS# Input Voltage with respect to GND on SO Current Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time. P/N: PM1236 MX25L4005 Min. TYP. (1) Max. ( ...

Page 35

... ORDERING INFORMATION PART NO. MX25L4005MC-15 MX25L4005MC-15G MX25L4005M2C-15 www.DataSheet4U.com MX25L4005M2C-15G MX25L4005ZMC-15G MX25L4005MI-15 MX25L4005MI-15G MX25L4005M2I-15 MX25L4005M2I-15G MX25L4005ZMI-15G P/N: PM1236 CLOCK OPERATING STANDBY (MHz) CURRENT(mA) CURRENT(uA MX25L4005 Temperature PACKAGE 10 0~70 C 8-SOP (150mil) 10 0~70 C 8-SOP (150mil) 10 0~70 C 8-SOP ...

Page 36

... OPTION: G: Pb-free blank: normal SPEED: 15: 70MHz, for SPI TEMPERATURE RANGE: C: Commercial (0˚C to 70˚C) I: Industrial (-40˚C to 85˚C) PACKAGE: ZM: SON M: 150mil 8-SOP M2: 200mil 8-SOP DENSITY & MODE: 4005: 4Mb TYPE DEVICE: 25: Serial Flash 36 MX25L4005 REV. 1.1, SEP. 30, 2005 ...

Page 37

... PACKAGE INFORMATION www.DataSheet4U.com P/N: PM1236 MX25L4005 37 REV. 1.1, SEP. 30, 2005 ...

Page 38

... P/N: PM1236 MX25L4005 38 REV. 1.1, SEP. 30, 2005 ...

Page 39

... P/N: PM1236 MX25L4005 39 REV. 1.1, SEP. 30, 2005 ...

Page 40

... REVISION HISTORY Revision No. Description 1.0 1. Removed "Preliminary" 2. Improved tVSL spec from 30us to 10us separated from MX25L4005, MX25L8005 to MX25L4005 1.1 1. Standby current is reduced from 50uA(max.) to 10uA(max.) 2. Added description about Pb-free device is RoHS compliant 3. Improved erase speed: 4KB sector: 90ms(typ.)/270ms(max.)-->60ms(typ.)/120ms(max.) 64KB sector:1s(typ.)/3s(max.)-->1s(typ.)/2s(max.) www.DataSheet4U.com chip sector:4.5s(typ.)/10s(max.)--> ...

Page 41

... MX25L4005 MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice. ...

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