mx25l512 Macronix International Co., mx25l512 Datasheet

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mx25l512

Manufacturer Part Number
mx25l512
Description
512k-bit [x 1] Cmos Serial Flash
Manufacturer
Macronix International Co.
Datasheet

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GENERAL
• Serial Peripheral Interface (SPI) compatible -- Mode 0 and Mode 3
• 524,288 x 1 bit structure
• 16 Equal Sectors with 4K byte each
• Single Power Supply Operation
• Latch-up protected to 100mA from -1V to Vcc +1V
• Low Vcc write inhibit is from 1.5V to 2.5V
PERFORMANCE
• High Performance
• Low Power Consumption
• Minimum 100,000 erase/program cycles
SOFTWARE FEATURES
• Input Data Format
• Block Lock protection
• Auto Erase and Auto Program Algorithm
• Status Register Feature
• Electronic Identification
HARDWARE FEATURES
• SCLK Input
P/N: PM1214
FEATURES
- Any Sector can be erased individually
- 2.7 to 3.6 volt for read, erase, and program operations
- Fast access time: 85MHz serial clock (15pF + 1TTL Load) and 66MHz serial clock (30pF + 1TTL Load)
- Fast program time: 1.4ms(typ.) and 5ms(max.)/page (256-byte per page)
- Fast erase time: 60ms(typ.) and 120ms(max.)/sector (4K-byte per sector) ; 1s(typ.) and 2s(max.)/chip(512Kb)
- Low active read current: 12mA(max.) at 85MHz, 8mA(max.) at 66MHz and 4mA(max.) at 33MHz
- Low active programming current: 15mA (max.)
- Low active erase current: 15mA (max.)
- Low standby current: 10uA (max.)
- Deep power-down mode 1uA (typical)
- 1-byte Command code
-
-
program pulse widths (Any page to be programed should have page in the erased state first)
-
- RES command, 1-byte Device ID
-
- The BP0~BP1 status bit defines the size of the area to be software protected against Program and Erase instructions.
Automatically erases and verifies data at selected sector
JEDEC 2-byte Device ID
Serial clock input
Automatically programs and verifies data at selected page by an internal algorithm that automatically times the
1
512K-BIT [x 1] CMOS SERIAL FLASH
MX25L512
REV. 1.4, MAR. 24, 2008

Related parts for mx25l512

mx25l512 Summary of contents

Page 1

... Status Register Feature • Electronic Identification - JEDEC 2-byte Device ID - RES command, 1-byte Device ID HARDWARE FEATURES • SCLK Input - Serial clock input P/N: PM1214 MX25L512 512K-BIT [x 1] CMOS SERIAL FLASH 1 REV. 1.4, MAR. 24, 2008 ...

Page 2

... All Pb-free devices are RoHS Compliant GENERAL DESCRIPTION The MX25L512 is a CMOS 524,288 bit serial Flash memory, which is configured as 65,536 x 8 internally. The MX25L512 feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO) ...

Page 3

... PIN CONFIGURATIONS 8-PIN SOP (150mil) P/N: PM1214 MX25L512 PIN DESCRIPTION SYMBOL DESCRIPTION CS# Chip Select SI Serial Data Input SO Serial Data Output SCLK Clock Input HOLD# Hold, to pause the device without deselecting the device WP# Write Protection VCC + 3.3V Power Supply GND Ground 3 REV. 1.4, MAR. 24, 2008 ...

Page 4

... BLOCK DIAGRAM Address Generator SI CS# SCLK P/N: PM1214 Memory Array Page Buffer Data Register Y-Decoder SRAM Buffer Mode State HV Logic Machine Generator Clock Generator 4 MX25L512 Output Sense Amplifier Buffer SO REV. 1.4, MAR. 24, 2008 ...

Page 5

... DATA PROTECTION The MX25L512 are designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. During power up the device automatically resets the state machine in the Read mode. In addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific command sequences ...

Page 6

... HOLD operation. If Chip Select (CS#) drives high during HOLD operation, it will reset the internal logic of the device. To re-start communication with chip, the HOLD# must be at high and CS# must be at low. P/N: PM1214 Protect level 0 (none) 1 (All) 2 (All) 3 (All) Hold Hold Condition Condition (standard) (non-standard) 6 MX25L512 512b None All All All REV. 1.4, MAR. 24, 2008 ...

Page 7

... RDP (Page (Deep (Release Program) Power from Deep Down) Power-down) 02 Hex B9 Hex AB Hex AD1 AD2 AD3 7 MX25L512 READ Fast Read (read data) (fast read data) 03 Hex 0B Hex AD1 AD1 AD2 AD2 AD3 AD3 x n bytes read out CS# goes high ...

Page 8

... CPOL indicates clock polarity of SPI master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which SPI mode is supported. P/N: PM1214 shift in MSB 8 MX25L512 shift out MSB REV. 1.4, MAR. 24, 2008 ...

Page 9

... The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The MXIC Manufacturer ID is C2(hex), the memory type ID is 20(hex) as the first-byte device ID, and the individual device ID of second-byte followings: 10(hex) for MX25L512. The sequence of issuing RDID instruction is: CS# goes low-> sending RDID instruction code -> 24-bits ID data out on SO -> ...

Page 10

... N x 15ms ( multiple of 10,000 cycles, ex for 20,000 cycles) after 10,000 cycles on those bits. P/N: PM1214 bit 4 bit 3 bit 2 BP1 BP0 0 the level of the level of protected protected block block (note 1) (note 1) 1=write enable 1=write operation 10 MX25L512 bit 1 bit 0 WEL WIP (write enable (write in progress latch) bit) 0=not write 0=not in write enable operation REV. 1.4, MAR. 24, 2008 ...

Page 11

... BP0. The protected area, which is defined by BP1, BP0 software protected mode (SPM) Note: If SRWD bit=1 but WP# is low impossible to write the Status Register even if the WEL bit has previously been P/N: PM1214 MX25L512 WP# and SRWD bit status WP#=1 and SRWD bit=0, or ...

Page 12

... Address bits [Am-A12] (Am is the most significant address) select the sector address. The sequence of issuing SE instruction is: CS# goes low -> sending SE instruction code-> 3-byte address on SI -> CS# goes high. (see Figure 19) P/N: PM1214 MX25L512 12 REV. 1.4, MAR. 24, 2008 ...

Page 13

... The sequence of issuing PP instruction is: CS# goes low-> sending PP instruction code-> 3-byte address on SI-> at least 1-byte on data on SI-> CS# goes high. (see Figure 18) The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress P/N: PM1214 MX25L512 13 REV. 1.4, MAR. 24, 2008 ...

Page 14

... CS# must remain to high at least tRES2(max). Once in the standby mode, the device waits to be selected can be receive, decode, and execute instruction. The RDP instruction is for releasing from Deep Power Down Mode. P/N: PM1214 MX25L512 14 REV. 1.4, MAR. 24, 2008 ...

Page 15

... The Manufacturer and Device IDs can be read continuously, alternating from one to the other. The instruction is completed by driving CS# high. Table of ID Definitions: 1. RDID: manufacturer ID MX25L512 2. RES: MX25L512 3. REMS: MX25L512 P/N: PM1214 memory type C2 20 electronic ID 05 manufacturer MX25L512 memory density 10 device ID 05 REV. 1.4, MAR. 24, 2008 ...

Page 16

... At power-down stage, the VCC drops below VWI level, all operations are disable and device has no response to any command. The data corruption might occur during the stage while a write, program, erase cycle is in progress. P/N: PM1214 MX25L512 16 REV. 1.4, MAR. 24, 2008 ...

Page 17

... During voltage transitions, all pins may overshoot to 4.6V or -0.5V for period up to 20ns. -0.5V to 4.6V 4. All input and output pins may overshoot to VCC+0.5V -0.5V to 4.6V while VCC+0.5V is smaller than or equal to 4.6V. Figure 4. Maximum Positive Overshoot Waveform 4.6V 3.6V MIN. TYP 17 MX25L512 20ns MAX. UNIT CONDITIONS 6 pF VIN = VOUT = 0V REV. 1.4, MAR. 24, 2008 ...

Page 18

... Figure 6. OUTPUT LOADING DEVICE UNDER TEST P/N: PM1214 Output timing referance level 0.7VCC AC Measurement Level 0.3VCC Note: Input pulse rise and fall time are <5ns 2.7K ohm CL 6.2K ohm DIODES=IN3064 OR EQUIVALENT CL=30pF Including jig capacitance (CL=15pF Including jig capacitance for 85MHz) 18 MX25L512 0.5VCC +3.3V REV. 1.4, MAR. 24, 2008 ...

Page 19

... V 0.7VCC VCC+0.4 V 0.4 V VCC-0 MX25L512 TEST CONDITIONS VCC = VCC Max VIN = VCC or GND VCC = VCC Max VIN = VCC or GND VIN = VCC or GND CS# = VCC VIN = VCC or GND CS# = VCC f=85MHz SCLK=0.1VCC/0.9VCC, SO=Open f=66MHz SCLK=0.1VCC/0.9VCC, SO=Open f=33MHz SCLK=0 ...

Page 20

... Chip Erase Cycle Time Note: 1. tCH + tCL must be greater than or equal Value guaranteed by characterization, not 100% tested in production. 3. Expressed as a slew-rate. 4. Only applicable as a constraint for a WRSR instruction when SRWD is set Test condition is shown as Figure 3. P/N: PM1214 MX25L512 Min. 1KHz 1KHz 7 7 0.1 0.1 ...

Page 21

... Write Inhibit Voltage Note: 1. These parameters are characterized only. INITIAL DELIVERY STATE The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register contains 00h (all Status Register bits are 0). P/N: PM1214 MX25L512 Min. Max 1.5 ...

Page 22

... Figure 7. Serial Input Timing CS# tCHSL SCLK tDVCH SI High-Z SO Figure 8. Output Timing CS# SCLK tCLQV tCLQX tCLQX SO ADDR.LSB IN SI P/N: PM1214 tSLCH tCHSH tCHDX tCLCH MSB LSB tCH tCLQV tCL tQLQH tQHQL 22 MX25L512 tSHSL tSHCH tCHCL tSHQZ LSB REV. 1.4, MAR. 24, 2008 ...

Page 23

... HOLD "don't care" during HOLD operation. Figure 10. WP# Disable Setup and Hold Timing during WRSR when SRWD=1 WP# tWHSL CS SCLK SI High-Z SO P/N: PM1214 tHLCH tCHHL tCHHH tHLQZ MX25L512 tHHCH tHHQX tSHWL REV. 1.4, MAR. 24, 2008 ...

Page 24

... High-Z SO P/N: PM1214 Command 06 High Command 04 High Manufacturer Identification MSB MSB 24 MX25L512 Device Identification REV. 1.4, MAR. 24, 2008 ...

Page 25

... Status Register MSB High 24-Bit Address MSB 7 MSB 25 MX25L512 Status Register Out MSB Data Out 1 Data Out REV ...

Page 26

... P/N: PM1214 BIT ADDRESS DATA OUT MSB MSB 26 MX25L512 DATA OUT MSB REV. 1.4, MAR. 24, 2008 ...

Page 27

... Address MSB MSB Data Byte MSB 27 MX25L512 Data Byte Data Byte 256 MSB REV. 1.4, MAR. 24, 2008 ...

Page 28

... Figure 20. Block Erase (BE) Sequence (Command 52 or D8) CS# SCLK SI Note: BE command D8(hex). P/N: PM1214 Command 24 Bit Address MSB Command 24 Bit Address MSB 28 MX25L512 REV. 1.4, MAR. 24, 2008 ...

Page 29

... DP Command B9 Stand-by Mode Dummy Bytes MSB Electronic Signature Out MSB Deep Power-down Mode 29 MX25L512 Deep Power-down Mode Sequence RES2 Stand-by Mode REV. 1.4, MAR. 24, 2008 ...

Page 30

... Dummy Bytes Manufacturer MSB MSB 30 MX25L512 Stand-by Mode 47 Device MSB REV. 1.4, MAR. 24, 2008 ...

Page 31

... Figure 26. Power-up Timing (max) Program, Erase and Write Commands are Ignored Chip Selection is Not Allowed V CC (min) Reset State of the Flash V WI P/N: PM1214 MX25L512 tVSL Read Command is Device is fully allowed accessible tPUW 31 time REV. 1.4, MAR. 24, 2008 ...

Page 32

... For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer to "AC CHARACTERISTICS" table. P/N: PM1214 tSLCH tDVCH tCHDX MSB IN High Impedance Figure A. AC Timing at Device Power-Up Notes 1 32 MX25L512 tSHSL tCHSH tSHCH tCHCL tCLCH LSB IN Min. Max. Unit 0.5 500000 us/V REV ...

Page 33

... Input Voltage with respect to GND on ACC Input Voltage with respect to GND on all power pins, SI, CS# Input Voltage with respect to GND on SO Current Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time. P/N: PM1214 MX25L512 Min. TYP. (1) Max. ( ...

Page 34

... ORDERING INFORMATION PART NO. CLOCK (MHz) MX25L512MC-12 85 MX25L512MC-12G 85 MX25L512MI-12 85 MX25L512MI-12G 85 P/N: PM1214 OPERATING STANDBY Temperature PACKAGE CURRENT MAX. CURRENT MAX. (mA) (uA MX25L512 Remark 0~70 C 8-SOP (150mil) 0~70 C 8-SOP Pb-free (150mil) -40~85 C 8-SOP (150mil) -40~85 C 8-SOP Pb-free (150mil) REV. 1.4, MAR. 24, 2008 ...

Page 35

... PART NAME DESCRIPTION P/N: PM1214 512 OPTION: G: Pb-free blank: normal SPEED: 12: 85MHz TEMPERATURE RANGE: I: Industrial (-40˚CC to 85˚ Commercial (0˚CC to 70˚ C PACKAGE: M: 150mil 8-SOP DENSITY & MODE: 512: 512Kb TYPE DEVICE: 25: Serial Flash 35 MX25L512 REV. 1.4, MAR. 24, 2008 ...

Page 36

... PACKAGE INFORMATION P/N: PM1214 MX25L512 36 REV. 1.4, MAR. 24, 2008 ...

Page 37

... Removed "Advanced Information" title 5. Added C-grade part number 1.1 1. Format change 2. Supplemented the footnote for tW of protect/unprotect bits 1.2 1. Added statement 1.3 1. Defined min. clock frequency of fSCLK & fRSCLK as 1KHz 1.4 1. Removed 8-land SON package and order information P/N: PM1214 MX25L512 Page P1,18,33 P1,19, P33 All P9 P38 P20 P2,3,34,35 ...

Page 38

... Macronix's products in the prohibited applications ACRONIX NTERNATIONAL Headquarters Macronix America, Inc. Macronix Japan Cayman Islands Ltd. Macronix (Hong Kong) Co., Limited. http : //www.macronix.com C L O., TD. Taipei Office Macronix Europe N.V. Singapore Office MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice. 38 MX25L512 ...

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