n25q064 Numonyx, n25q064 Datasheet
n25q064
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n25q064 Summary of contents
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... More than 20 years data retention Packages (All packages RoHS compliant): – VDFPN8 (MLP8) – VDFPN8 (MLP8) – SO8W (SO8 Wide 208 mils body width) – SO16W (SO16 Wide 300 mils body width) – TBGA24 Rev 1 N25Q064 A (Typical) µ 1/154 ...
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... Subsector erase, sector erase and bulk erase . . . . . . . . . . . . . . . . . . . 23 Polling during a write, program or erase cycle . . . . . . . . . . . . . . . . . . . . 23 Active power and standby power modes . . . . . . . . . . . . . . . . . . . . . . . . 23 Hold (or Reset) condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Multiple Read Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Micron Technology, Inc., reserves the right to change products or specifications without notice. N25Q064 - 1.8V ©2010 Micron Technology, Inc. All rights reserved. ...
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... N25Q064 - 1.8V 5.2.2 5.2.3 5.2.4 5.2.5 5.2.6 5.2.7 5.2.8 5.3 Quad SPI (QIO-SPI)Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 5.3.6 5.3.7 5.3.8 5.3.9 6 Volatile and Non Volatile Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.1 Legacy SPI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 6.2 Non Volatile Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 6.2.6 6.3 Volatile Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.3.1 6.3.2 6.3.3 6.4 Volatile Enhanced Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . 37 Dual Command Fast reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Page programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Subsector Erase, Sector Erase and Bulk Erase . . . . . . . . . . . . . . . . . . 26 Polling during a Write, Program or Erase cycle . . . . . . . . . . . . . . . . . . . 26 Read and Modify registers ...
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... Write Enable (WREN Write Disable (WRDI Page Program (PP Dual Input Fast Program (DIFP Dual Input Extended Fast Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Quad Input Fast Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Micron Technology, Inc., reserves the right to change products or specifications without notice. N25Q064 - 1.8V ©2010 Micron Technology, Inc. All rights reserved. ...
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... N25Q064 - 1.8V 9.1.16 9.1.17 9.1.18 9.1.19 9.1.20 9.1.21 9.1.22 9.1.23 9.1.24 9.1.25 9.1.26 9.1.27 9.1.28 9.1.29 9.1.30 9.1.31 9.1.32 9.1.33 9.1.34 9.1.35 9.1.36 9.2 DIO-SPI Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 9.2.1 9.2.2 9.2.3 9.2.4 9.2.5 9.2.6 9.2.7 9.2.8 9.2.9 9.2.10 9.2.11 9.2.12 9.2.13 9.2.14 9.2.15 Quad Input Extended Fast Program . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Program OTP instruction (POTP Subsector Erase (SSE Sector Erase (SE Bulk Erase (BE Program/Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Program/Erase Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Read Status Register (RDSR Write status register (WRSR Read Lock Register (RDLR Write to Lock Register (WRLR Read Flag Status Register ...
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... Read NV Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Write NV Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Read Volatile Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Write Volatile Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Read Volatile Enhanced Configuration Register . . . . . . . . . . . . . . . . . 126 Micron Technology, Inc., reserves the right to change products or specifications without notice. N25Q064 - 1.8V ©2010 Micron Technology, Inc. All rights reserved. ...
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... N25Q064 - 1.8V 9.3.25 9.3.26 9.3.27 10 XIP Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 10.1 Enter XIP mode: Set the Non Volatile Configuration Register . . . . . . . . 131 10.2 Enter XIP mode: Set the Volatile Configuration Register . . . . . . . . . . . . 132 10.3 XIP mode hold and exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 10.4 XIP Memory reset after a controller reset . . . . . . . . . . . . . . . . . . . . . . . . 134 11 Power-up and power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 11.1 Rescue sequence in case of power loss during WRNVCR . . . . . . . . . . 136 12 Initial delivery state ...
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... TBGA 6x8 mm 24-Ball, Dimensions, Symbols FD to fff . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Table 39. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Table 40. Valid Order Information Line Items . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Table 41. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 8/154 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2010 Micron Technology, Inc. All rights reserved. N25Q064 - 1.8V ...
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... N25Q064 - 1.8V List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 2. SO8N, SO8W and MLP8 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 3. SO16 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 4. BGA connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 5. Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 6. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 7. Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 8. Non Volatile and Volatile configuration Register Scheme . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 9 ...
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... Write NV Configuration Register instruction sequence QIO-SPI . . . . . . . . . . . . . . . . . . . 124 Figure 99. Read Volatile Configuration Register instruction sequence QIO-SPI . . . . . . . . . . . . . . . . 125 Figure 100. Write Volatile Configuration Register instruction sequence QIO-SPI . . . . . . . . . . . . . . . . 126 10/154 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2010 Micron Technology, Inc. All rights reserved. N25Q064 - 1.8V ...
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... Figure 103. Deep Power-down instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Figure 104. Deep Power-down instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Figure 105. N25Q064 Read functionality Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Figure 106. XIP mode directly after power 132 Figure 107. XiP: enter by VCR 2/2 (QIOFR in normal SPI protocol example 133 Figure 108 ...
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... Description 1 Description The N25Q064 Mbit (8Mb x 8) multiple I/O high performance serial Flash memory, with advanced security and write protection mechanisms accessed by a high speed SPI-compatible bus with different sets of I/O bus configurations (x1, x2, and x4). It features the possibility to work in XIP (“eXecution in Place”) mode. ...
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... N25Q064 - 1.8V The N25Q064 has 64 one-time-programmable bytes (OTP bytes) that can be read and programmed using two dedicated instructions, Read OTP (ROTP) and Program OTP (POTP), respectively. These 64 bytes can be permanently locked by a particular Program OTP (POTP) sequence. Once they have been locked, they become read-only and this state cannot be reversed ...
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... S W/V /DQ2 DQ1 DQ0 HOLD/DQ3 Drawing. Micron Technology, Inc., reserves the right to change products or specifications without notice. N25Q064 - 1.8V Section 16: Ordering C DQ0 W/V /DQ2 PP Section 16: Ordering ©2010 Micron Technology, Inc. All rights reserved. ...
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... N25Q064 - 1.8V 2 Signal descriptions 2.1 Serial data output (DQ1) This output signal is used to transfer data serially out of the device. Data are shifted out on the falling edge of Serial Clock (C). When used as an Input latched on the rising edge of the Serial Clock (C). In the Extended SPI protocol, during the Quad and Dual Input Fast Program (QIFP, DIFP) instructions and during the Quad and Dual Input Extended Fast Program (QIEFP, DIEFP) instructions, pin DQ1 is used also as an input ...
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... W/VPP/DQ2 is used as an input/output (DQ2 functionality). 16/154 information. format). Table 27.: Operating conditions). In this case VPP must be stable until Micron Technology, Inc., reserves the right to change products or specifications without notice. N25Q064 - 1.8V ©2010 Micron Technology, Inc. All rights reserved. ...
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... N25Q064 - 1.8V Using the Extended SPI protocol the QIFP, QIEFP and the QIO-SPI Program/Erase instructions still possible to use the VPP additional power supply to speed up internal operations. However, to enable this possibility it is necessary to set bit 3 of the Volatile Enhanced Configuration Register to 0. ...
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... Resistors R ensures that the N25Q064 is not selected if the bus master leaves the S line in the high impedance state. As the bus master may enter a state where all ...
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... N25Q064 - 1. parasitic capacitance of the bus line) is shorter than the time during which the bus p master leaves the SPI bus in high impedance. Example pF, that is R*C p master never leaves the SPI bus in the high impedance state for a time period shorter than 5 µs. The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate ...
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... SPI Protocols 4 SPI Protocols The N25Q064 memory can work with 3 different Serial protocols: Extended SPI protocol. Dual I/O SPI (DIO-SPI) protocol. Quad I/O SPI (QIO-SPI) protocol possible to choose among the three protocols by means of user volatile or non-volatile configuration bits.It's not possible to mix Extended SPI, DIO-SPI, and QIO-SPI protocols. ...
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... N25Q064 - 1.8V 4.3 Quad SPI (QIO-SPI) protocol Quad SPI (QIO-SPI) protocol: instructions, addresses, and I/O data are always transmitted on four data lines DQ0, DQ1, W/VPP(DQ2), and HOLD / (DQ3). The exception is the Program/Erase cycle performed with the VPP, in which case the device temporarily goes to Extended SPI protocol. Going temporarily into Extended SPI protocol ...
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... DIEFP sequences, each containing only a few bytes. 22/154 Table 31: AC Characteristics). Section 9.1.13: Dual Input Fast Program Micron Technology, Inc., reserves the right to change products or specifications without notice. N25Q064 - 1. Section 5.2.3: Page (DIFP)). ©2010 Micron Technology, Inc. All rights reserved. ...
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... N25Q064 - 1.8V 5.1.5 Quad Input Fast Program The Quad Input Fast Program (QIFP) instruction makes it possible to program up to 256 bytes using 4 input pins at the same time (by changing bits from 1 to 0). For optimized timings recommended to use the QIFP instruction to program all consecutive targeted bytes in a single sequence rather than using several QIFP sequences each containing only a few bytes ...
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... The hold condition ends on the rising edge of the Hold Figure 7). Hold condition (standard use) information. Micron Technology, Inc., reserves the right to change products or specifications without notice. N25Q064 - 1.8V CC1 Hold condition (non-standard use) AI02029D Table 31.: AC Characteristics. All ©2010 Micron Technology, Inc. All rights reserved. ...
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... N25Q064 - 1.8V 5.2 Dual SPI (DIO-SPI) Protocol In the Dual SPI (DIO-SPI) protocol all the instructions, addresses and I/O data are transmitted on two data lines. All the functionality available in the Extended SPI protocol is also available in the DIO-SPI protocol. The DIO-SPI instructions are comparable with the Extended SPI instructions ...
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... DIO-SPI protocol Extended SPI protocol, so please refer to section 5.1.10, Hold (or Reset) condition” in the Extend SPI protocol section for further details. 26/154 Table 31.: AC Characteristics. Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2010 Micron Technology, Inc. All rights reserved. N25Q064 - 1.8V ...
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... N25Q064 - 1.8V 5.3 Quad SPI (QIO-SPI)Protocol In the Quad SPI (QIO-SPI) protocol all the Instructions, addresses and I/O data are transmitted on four data lines, with the exception of the polling instructions performed during a Program or Erase cycle performed with VPP, in this case the device temporarily goes in Extended SPI protocol. The protocol again becomes QIO-SPI as soon as the VPP voltage goes low ...
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... Extended SPI protocol, the only difference is that instruction codes, addresses and output data are transmitted across 4 data lines. 28/154 Table 31.: AC Characteristics. Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2010 Micron Technology, Inc. All rights reserved. N25Q064 - 1.8V ...
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... N25Q064 - 1.8V 5.3.7 Active Power and Standby Power modes Exactly as in Extended SPI protocol, when Chip Select (S) is Low, the device is selected, and in the Active Power mode. When Chip Select (S) is High, the device is deselected, but could remain in the Active Power mode until all internal (Program, Erase, Write) Cycles have completed ...
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... Registers download executed after a WRVCR or WRVECR instructions, it overwrites NVCR configurations on iCR iCR (internal Configuration Register) Device behaviour Micron Technology, Inc., reserves the right to change products or specifications without notice. N25Q064 - 1.8V Scheme, the (Volatile Co nfiguratio n Register) (Volatile Enhanced ©2010 Micron Technology, Inc. All rights reserved. ...
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... N25Q064 - 1.8V A Flag Status Register (FSR), 8 bits, is also available to check the status of the device, detecting possible errors or a Program/Erase internal cycle in progress. Each register can be read and modified by means of dedicated instructions in all the 3 protocols (Extended SPI, DIO-SPI, and QIO-SPI). Reading time for all registers is comparable; writing time instead is very different: NVCR bits are set as Flash Cell memory content requiring a longer time to perform internal writing cycles ...
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... Write Non Volatile Configuration Register (WRNVCR) in all the 3 available SPI protocols. See the sections that follow as well as Configuration Register. 32/154 Table 3.: Non-Volatile Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2010 Micron Technology, Inc. All rights reserved. N25Q064 - 1.8V ...
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... N25Q064 - 1.8V Table 3. Non-Volatile Configuration Register Bit Parameter Dummy clock NVCR<15:12> cycle XIP enabling NVCR<11:9> at POR Output Driver NVCR<8:6> Strength Value Description 0000 As '1111' 0001 1 0010 2 0011 3 0100 4 0101 5 0110 6 0111 7 1000 8 1001 9 1010 10 1011 11 1100 12 1101 13 1110 14 Target on maximum allowed frequency fc ...
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... Micron Technology, Inc., reserves the right to change products or specifications without notice. N25Q064 - 1.8V Note Default value = 1 Disable Pad Hold/Reset functionality Enable command on four input line Enable command on two input line Default value = "11" (1) DIOFR ...
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... N25Q064 - 1.8V 6.2.2 XIP NV configuration bits (NVCR bits from The bits from the Non Volatile Configuration register store the default settings for the XIP operation, allowing the memory to start working directly on the required XIP mode after successive POR sequence: the device then accepts only address on one, two, or four wires (skipping the instruction) depending on the NVCR XIP bits settings ...
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... Output data wraps within an aligned 64-byte boundary 2 starting from the address issued after the command code. 3 Continous reading (Default): All bytes are read sequentially Micron Technology, Inc., reserves the right to change products or specifications without notice. N25Q064 - 1.8V Description ©2010 Micron Technology, Inc. All rights reserved. ...
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... N25Q064 - 1.8V 6.3.1 Dummy clock cycle: VCR bits 7:4 The bits from the Volatile Configuration Register, as the bits from the Volatile Configuration register, set the dummy clock cycles number after the fast read instructions (in all the 3 available protocols). The dummy clock cycles number can be set ...
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... Micron Technology, Inc., reserves the right to change products or specifications without notice. N25Q064 - 1.8V Note Enable command on four input lines Enable command on two input lines Fixed value = 0b Disable Pad Hold/Reset functionality The bit must be considered in case of QIFP, QIEFP, or QIO-SPI protocol “Don’t Care” ...
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... N25Q064 - 1.8V 6.4.2 Dual Input Command VECR<6> The Dual Input Command configuration bit can be used to make the memory start working in DIO-SPI protocol directly after the Write Volatile Enhanced Configuration Register (WVECR) instruction. The default value of this bit is 1, corresponding to Extended SPI protocol, if this bit is set to 0 the memory works in DIO-SPI protocol (unless the Volatile Enhanced Configuration Register bit 7 is also set to 0) ...
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... Flag Status register bit WIP bit of the Status Register. 40/154 Register. Description Status Status Error Error Error Status Error Micron Technology, Inc., reserves the right to change products or specifications without notice. N25Q064 - 1.8V Note ©2010 Micron Technology, Inc. All rights reserved. ...
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... N25Q064 - 1.8V 6.5.2 Erase Suspend Status bit The bit 6 of the Flag Status register represents the Erase Suspend Status bit, It indicates that an Erase operation has been suspended or is going to be suspended. The bit is set (FSR<6>=1) within the Erase Suspend Latency time, that is as soon as the Program/Erase Suspend command (PES) has been issued, therefore the device may still complete the operation before entering the Suspend Mode ...
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... Once set High, the Protection Status bit can only be reset Low (FSR<1>= Clear Flag Status Register command (CLFSR). If set High it should be reset before a new command is issued, otherwise the new command will appear to fail. 42/154 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2010 Micron Technology, Inc. All rights reserved. N25Q064 - 1.8V ...
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... This applies to all three protocols. The environments where non-volatile memory devices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the N25Q064 features the following data protection mechanisms: Power On Reset and an internal timer (tPUW) can provide protection against inadvertent changes while the power supply is outside the operating specification ...
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... None 1 Upper 128th 0 Upper 64th 1 Upper 32nd Micron Technology, Inc., reserves the right to change products or specifications without notice. N25Q064 - 1.8V Memory Content Unprotected Area All sectors Sectors 0 to 126 Sectors 0 to 125 Sectors 0 to 123 ©2010 Micron Technology, Inc. All rights reserved. ...
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... N25Q064 - 1.8V Table 10. Protected area sizes (TB bit = 0) Status Register Content TB bit BP3 Bit BP2 Bit BP1 Bit BP0 Bit Table 11 ...
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... High voltage generator I/O shift register 256 byte data buffer 7FFFFFh 00000h 000FFh 256 bytes (page size) X decoder Micron Technology, Inc., reserves the right to change products or specifications without notice. N25Q064 - 1.8V 64 OTP bytes Status register AI13722b ©2010 Micron Technology, Inc. All rights reserved. ...
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... N25Q064 - 1.8V Table 12. Memory organization Sector Subsector 2047 127 2032 2031 126 2016 2015 125 2000 1999 124 1984 1983 123 1968 1967 122 1952 1951 121 1936 1935 120 1920 1919 119 1904 1903 118 1888 1887 117 1872 Address range ...
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... Micron Technology, Inc., reserves the right to change products or specifications without notice. N25Q064 - 1.8V Subsector Address range 1519 5EF000h 5EFFFFh 1504 5E0000h 5E0FFFh 1503 5DF000h 5DFFFFh 464 5D0000h 5D0FFFh 1487 5CF000h ...
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... N25Q064 - 1.8V Table 12. Memory organization (continued) Sector Subsector 1343 83 1328 1327 82 1312 1311 81 1296 1295 80 1280 1279 79 1264 1263 78 1248 1247 77 1232 1231 76 1216 1215 75 1200 1199 74 1184 1183 73 1168 Address range Sector 53F000h 53FFFFh 72 530000h 530FFFh 52F000h 52FFFFh 71 520000h 520FFFh 51F000h ...
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... Micron Technology, Inc., reserves the right to change products or specifications without notice. N25Q064 - 1.8V Subsector Address range 815 32F000h 32FFFFh 800 320000h 320FFFh 799 31F000h 31FFFFh 784 310000h 310FFFh 783 30F000h ...
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... N25Q064 - 1.8V Table 12. Memory organization (continued) Sector Subsector 639 39 624 623 38 608 607 37 592 591 36 576 575 35 560 559 34 544 543 33 528 527 32 512 511 31 496 495 30 480 479 29 464 Address range Sector 27F000h 27FFFFh 28 270000h 270FFFh 26F000h 26FFFFh 27 260000h 260FFFh 25F000h ...
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... B0000h B0FFFh AF000h AFFFFh A0000h A0FFFh 9F000h 9FFFFh 0 90000h 90FFFh 8F000h 8FFFFh 80000h 80FFFh Micron Technology, Inc., reserves the right to change products or specifications without notice. N25Q064 - 1.8V Subsector Address range 127 7F000h 7FFFFh 112 70000h 70FFFh 111 6F000h 6FFFFh 96 60000h 60FFFh 95 5F000h ...
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... N25Q064 - 1.8V 9 Instructions The device can work in three different protocols: Extended SPI, DIO-SPI and QIO-SPI. Each protocol has a dedicated instruction set, and each instruction set features the same functionality: Read, program and erase the memory and the 64 byte OTP area, Suspend and resume the program or erase operations, ...
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... Status register and on the Flag Status register) are also accepted to allow the application to check the end of the internal modify cycles. Note: These polling instructions don't affect the internal cycles performing. 54/154 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2010 Micron Technology, Inc. All rights reserved. N25Q064 - 1.8V ...
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... N25Q064 - 1.8V Table 13. Instruction set: extended SPI protocol (page Instruction Description RDID Read Identification READ Read Data Bytes FAST_READ Read Data Bytes at Higher Speed RDSFDP Read Serial Flash Discovery Parameter DOFR Dual Output Fast Read DIOFR Dual Input/Output Fast Read QOFR ...
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... B9h 0 1010 1011 ABh 0 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2010 Micron Technology, Inc. All rights reserved. N25Q064 - 1.8V Dummy Data clock bytes cycle ∞ ...
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... N25Q064 - 1.8V Table 14. Read Identification data-out sequence Manufacturer Identification Memory type 20h BBh Table 15. Extended Device ID table (first byte) Bit 7 Bit 6 Bit 5 Reserved Reserved Reserved Figure 10. Read identification instruction and data-out sequence 9.1.2 Read Data Bytes (READ) The device is first selected by driving Chip Select (S) Low. The instruction code for the Read Data Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being latched-in during the rising edge of Serial Clock (C) ...
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... MSB Micron Technology, Inc., reserves the right to change products or specifications without notice. N25Q064 - 1. Data Out 1 Data Out MSB ©2010 Micron Technology, Inc. All rights reserved. ...
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... N25Q064 - 1.8V Figure 12. Read Data Bytes at Higher Speed instruction and data-out sequence Instruction DQ0 High Impedance DQ1 Dummy cycles DQ0 DQ1 *Address bit A23 is “Don’t Care. ” 9.1.4 Read Serial Flash Discovery Parameter The Read Serial Flash Discovery Parameter (RDSFDP) instruction allows reading the Serial Flash Discovery Parameter area (SFDP) ...
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... DATA OUT MSB Micron Technology, Inc., reserves the right to change products or specifications without notice. N25Q064 - 1. DATA OUT MSB MSB ©2010 Micron Technology, Inc. All rights reserved. ...
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... N25Q064 - 1.8V Figure 14. Dual Output Fast Read instruction sequence S Mode Mode 2 DQ0 DQ1 Dummy cycles DQ0 DQ1 *Address bit A23 is “Don’t Care.” 9.1.6 Dual I/O Fast Read The Dual I/O Fast Read (DIOFR) instruction is very similar to the Dual Output Fast Read (DOFR), except that the address bits are shifted in on two pins (pin DQ0 and pin DQ1) instead of only one ...
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... Byte 2 Byte 3 information. Micron Technology, Inc., reserves the right to change products or specifications without notice. N25Q064 - 1. Dummy Cycles Byte 4 ...
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... N25Q064 - 1.8V Figure 16. Quad Output Fast Read instruction sequence S Mode Mode 0 Instruction DQ0 Don’t Care DQ1 Don’t Care DQ2 DQ3 ‘1’ 9.1.8 Quad I/O Fast Read The Quad I/O Fast Read (QIOFR) instruction is very similar to the Quad Output Fast Read (QOFR), except that the address bits are shifted in on four pins (pin DQ0, pin DQ1, pin W/VPP/DQ2 and pin HOLD/DQ3 (1)) instead of only one ...
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... DATA OUT MSB Micron Technology, Inc., reserves the right to change products or specifications without notice. N25Q064 - 1. DATA OUT MSB ©2010 Micron Technology, Inc. All rights reserved. 7 MSB ...
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... N25Q064 - 1.8V 9.1.10 Write Enable (WREN) The Write Enable (WREN) instruction sets the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL) bit must be set prior to every Program, Erase, or Write instructions: Page Program (PP), Dual Input Fast Program (DIFP), Dual Input Extended Fast Program ...
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... Instruction High Impedance Micron Technology, Inc., reserves the right to change products or specifications without notice. N25Q064 - 1.8V 7 AI13732 ©2010 Micron Technology, Inc. All rights reserved. ...
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... N25Q064 - 1.8V same page (from the address whose 8 least significant bits (A7-A0) are all zero). Chip Select (S) must be driven Low for the entire duration of the sequence. If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page ...
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... Block Protect (BP3, BP2, BP1, BP0 and TB) bits is not executed. Dual Input Fast Program cycle can be paused by mean of Program/Erase Suspend (PES) instruction and resumed by mean of Program/Erase Resume (PER) instruction. 68/154 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2010 Micron Technology, Inc. All rights reserved. N25Q064 - 1.8V ...
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... N25Q064 - 1.8V Figure 22. Dual Input Fast Program instruction sequence Instruction DQ0 DQ1 DQ0 DATA DQ1 MSB MSB *Address bit A23 is “Don’t Care. ” 9.1.14 Dual Input Extended Fast Program ...
Page 70
... Data In 2 Data MSB MSB Micron Technology, Inc., reserves the right to change products or specifications without notice. N25Q064 - 1. Data In 256 Data In 4 ...
Page 71
... N25Q064 - 1.8V Chip Select (S) must be driven High after the eighth bit of the last data byte has been latched in, otherwise the Quad Input Fast Program (QIFP) instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose duration is tPP) is initiated. While the Quad Input Fast Program (QIFP) cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit ...
Page 72
... MSB Micron Technology, Inc., reserves the right to change products or specifications without notice. N25Q064 - 1. Data In Data In Data ...
Page 73
... N25Q064 - 1.8V Therefore, as soon as bit 0 of byte 64 (control byte) is set to '0', the 64 bytes of the OTP memory array become read-only in a permanent way. Any Program OTP (POTP) instruction issued while an Erase, Program or Write cycle is in progress is rejected without having any effect on the cycle that is in progress. ...
Page 74
... Program/Erase Resume (PER) instruction. 74/154 Instruction 24 Bit Address MSB Micron Technology, Inc., reserves the right to change products or specifications without notice. N25Q064 - 1. Subsector_Erase ©2010 Micron Technology, Inc. All rights reserved. ...
Page 75
... N25Q064 - 1.8V Figure 29. Sector Erase instruction sequence S C DQ0 *Address bit A23 is “Don’t Care. ” 9.1.20 Bulk Erase (BE) The Bulk Erase (BE) instruction sets all bits to '1' (FFh). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL) ...
Page 76
... Typ Max 700 Table 17.: Operations Allowed / Disallowed During Device Micron Technology, Inc., reserves the right to change products or specifications without notice. N25Q064 - 1.8V Unit Note µs Timing not internally controlled µs Timing not internally controlled µs Timing not internally controlled µs Any Read instruction accepted µ ...
Page 77
... N25Q064 - 1.8V Table 17. Operations Allowed / Disallowed During Device States Device States and Sector (Same/Other) in Which Operation is Allowed/Disallowed (Yes/No) Standby State Program State Operation Sector Same Other Same All Reads except RDSR / Yes Yes RDFSR Array Program DIFP / Yes Yes QIFP / DIEFP / QIEFP ...
Page 78
... Status register out MSB Micron Technology, Inc., reserves the right to change products or specifications without notice. N25Q064 - 1.8V Status register out MSB ©2010 Micron Technology, Inc. All rights reserved ...
Page 79
... N25Q064 - 1.8V Figure 32. Write Status Register instruction sequence S C DQ0 DQ1 The protection features of the device are summarized below. When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial delivery state possible to write to the Status Register provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless of the whether Write Protect (W/VPP) is driven High or Low ...
Page 80
... MSB Micron Technology, Inc., reserves the right to change products or specifications without notice. N25Q064 - 1.8V Memory content (1) Protected area Unprotected area Protected against PP, Ready to accept PP, DIFP, DIEFP, QIFP, DIFP, DIEFP, QIFP, QIEFP, SSE, SE and QIEFP, SSE, and SE BE instructions ...
Page 81
... N25Q064 - 1.8V Table 19. Lock Register out Bit Bit name Value b7-b2 The Write Lock and Lock Down bits cannot be changed. Once a ‘1’ is written to the ‘1’ Sector Lock Lock Down bit it cannot be cleared to ‘0’, except by a power-up. b1 Down ‘0’ The Write Lock and Lock Down bits can be changed by writing new values to them. ...
Page 82
... Section 7: Protection Flag Status Register Out MSB Micron Technology, Inc., reserves the right to change products or specifications without notice. N25Q064 - 1.8V Value ‘0’ Table 19) Table 19) modes. Flag Status Register Out ...
Page 83
... N25Q064 - 1.8V Figure 36. Clear Flag Status Register instruction sequence DQ0 DQ1 9.1.29 Read NV Configuration Register The Read Non Volatile Configuration Register (RDNVCR) instruction allows the Non Volatile Configuration Register to be read. Figure 37. Read NV Configuration Register instruction sequence Instruction DQ0 ...
Page 84
... Instruction Volatile Configuration Register Out MSB Micron Technology, Inc., reserves the right to change products or specifications without notice. N25Q064 - 1. NVCR In Byte Byte Register. Volatile Configuration Register Out 7 ...
Page 85
... N25Q064 - 1.8V When the new data are latched, the write enable latch (WEL) is reset. The Write Volatile Configuration register (WRVCR) instruction allows the user to change the values of all the Volatile Configuration Register bits, described in Configuration Register. The Write Volatile Configuration Register impacts the memory behavior right after the instruction is received by the device ...
Page 86
... Instruction VECR High Impedance MSB Micron Technology, Inc., reserves the right to change products or specifications without notice. N25Q064 - 1. before the supply current is reduced DP ©2010 Micron Technology, Inc. All rights reserved. to CC1 ...
Page 87
... N25Q064 - 1.8V Figure 43. Deep Power-down instruction sequence DQ0 9.1.36 Release from Deep Power-down (RDP) Once the device has entered the Deep Power-down mode, all instructions are ignored except the Release from Deep Power-down (RDP) instruction. Executing this instruction takes the device out of the Deep Power-down mode. ...
Page 88
... Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2010 Micron Technology, Inc. All rights reserved. N25Q064 - 1.8V ...
Page 89
... N25Q064 - 1.8V Table 21. Instruction set: DIO-SPI protocol Instruction Description MIORDID Multiple I/O read identification RDSFDP Read Serial Flash Discovery Parameter 01011010 DCFR Dual Command Fast Read ROTP Read OTP WREN Write Enable WRDI Write Disable DCPP Dual Command Page Program POTP Program OTP ...
Page 90
... DEV. MAN. AFh code code Micron Technology, Inc., reserves the right to change products or specifications without notice. N25Q064 - 1.8V SIZE code ©2010 Micron Technology, Inc. All rights reserved. ...
Page 91
... N25Q064 - 1.8V Figure 46. Dual Read Serial Flash Discovery Parameter Instruction DQ0 DQ1 *Address bit A23 is “Don’t Care. ” The dummy clock cycle depends on the Fast Read configuration in the NVCR/VCR register (default = 8). 9.2.3 Dual Command Fast Read (DCFR) ...
Page 92
... Instruction Section 9.1.11: Write Disable (WRDI Instruction DQ0 DQ1 Dual_Write_Disable Micron Technology, Inc., reserves the right to change products or specifications without notice. N25Q064 - 1.8V Data Out n Data Out MSB MSB for further © ...
Page 93
... N25Q064 - 1.8V 9.2.7 Dual Command Page Program (DCPP) The Dual Command Page Program (DCPP) instruction allows to program the memory content in DIO-SPI protocol, parallelizing the instruction code, the address and the input data on two pins (DQ0 and DQ1). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed ...
Page 94
... Address Section 9.1.18: Subsector Erase (SSE) Micron Technology, Inc., reserves the right to change products or specifications without notice. N25Q064 - 1.8V 1037 1036 Data Byte 1 Data Byte 2 Data Byte 256 ...
Page 95
... N25Q064 - 1.8V Figure 55. Subsector Erase instruction sequence DIO-SPI S C DQ0 DQ1 *Address bit A23 is “Don’t Care.” 9.2.10 Sector Erase (SE) The Sector Erase (SE) instruction sets to '1' (FFh) all bits inside the chosen sector. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. ...
Page 96
... Extended SPI protocol, please refer to Resume for further details. 96/154 Instruction Dual_Bulk_Erase Instruction Dual_Program_Erase_Suspend Section 9.1.22: Program/Erase Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2010 Micron Technology, Inc. All rights reserved. N25Q064 - 1.8V ...
Page 97
... N25Q064 - 1.8V Figure 59. Program/Erase Resume instruction sequence DIO-SPI S C DQ0 DQ1 9.2.14 Read Status Register (RDSR) The Read Status Register (RDSR) instruction allows the Status Register to be read. Apart form the parallelizing of the instruction code and the output data on the two pins DQ0 and ...
Page 98
... Address for further details. Micron Technology, Inc., reserves the right to change products or specifications without notice. N25Q064 - 1. Byte Section 9.1.25 Lock Register Out ...
Page 99
... N25Q064 - 1.8V Figure 63. Write to Lock Register instruction sequence DIO-SPI DQ0 DQ1 *Address bit A23 is “Don’t Care. ” 9.2.18 Read Flag Status Register The Read Flag Status Register (RFSR) instruction allows the Flag Status Register to be read. Apart form the parallelizing of the instruction code and the output data on the two pins DQ0 ...
Page 100
... Byte Instruction Byte Micron Technology, Inc., reserves the right to change products or specifications without notice. N25Q064 - 1. NVCR Out Byte Byte for further details. ©2010 Micron Technology, Inc. All rights reserved. ...
Page 101
... N25Q064 - 1.8V Figure 67. Write NV Configuration Register instruction sequence DIO-SPI S C DQ0 DQ1 9.2.22 Read Volatile Configuration Register The Read Volatile Configuration Register (RDVCR) instruction allows the Volatile Configuration Register to be read. See Figure 68. Read Volatile Configuration Register instruction sequence DIO-SPI S C DQ0 DQ1 9 ...
Page 102
... Volatile Enhanced Configuration Register Out Byte Byte Instruction Micron Technology, Inc., reserves the right to change products or specifications without notice. N25Q064 - 1. for further details. ©2010 Micron Technology, Inc. All rights reserved. ...
Page 103
... N25Q064 - 1.8V Figure 71. Write Volatile Enhanced Configuration Register instruction sequence DIO-SPI S C DQ0 DQ1 9.2.26 Deep Power-down (DP) The Deep-Power-down (DP) instruction sets the device in Deep Power-down mode. Apart form the parallelizing of the instruction code on the two pins DQ0 and DQ1, the instruction functionality is exactly the same as the Deep Power-down (DP) instruction of the Extended SPI protocol ...
Page 104
... Figure 73. Release from Deep Power-down instruction sequence Instruction DQ0 DQ1 104/154 sequence. t RDP 3 High Impedance Deep power-down mode Micron Technology, Inc., reserves the right to change products or specifications without notice. N25Q064 - 1.8V Figure 73: Standby mode Dual_RDP ©2010 Micron Technology, Inc. All rights reserved. ...
Page 105
... N25Q064 - 1.8V 9.3 QIO-SPI Instructions In QIO-SPI protocol, instructions, addresses and Input/Output data always run in parallel on four wires: DQ0, DQ1, DQ2 and DQ3 with the already mentioned exception of the modify instruction (erase and program) performed with the VPP=VPPh. In the case of a Quad Command Fast Read (QCFR), Read OTP (ROTP), Read Lock ...
Page 106
... B9h 0 1010 1011 ABh 0 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2010 Micron Technology, Inc. All rights reserved. N25Q064 - 1.8V Dummy Data clock bytes cycle ∞ ( ∞ (1) ...
Page 107
... N25Q064 - 1.8V 9.3.1 Multiple I/O Read Identification (MIORDID) The Multiple Input/Output Read Identification (MIORDID) instruction allows to read the device identification data in the QIO-SPI protocol: Manufacturer identification (1 byte) Device identification (2 bytes) Unlike the RDID instruction of the Extended SPI protocol, the Multiple Input/Output instruction can not read the Unique ID code (UID) (17 bytes). ...
Page 108
... Dummy (ex.: 10) Section 9.1.8: Quad I/O Fast Read Micron Technology, Inc., reserves the right to change products or specifications without notice. N25Q064 - 1. switches from Input to Output ...
Page 109
... N25Q064 - 1.8V Figure 76. Quad Command Fast Read instruction and data-out sequence QSP, 0Bh S Mode Mode 0 Instruction 4 0 DQ0 DQ1 5 1 DQ2 6 2 DQ3 7* 3 A23-16 A15-8 A7-0 *This bit is “Don’t Care. ” Figure 77. Quad Command Fast Read instruction and data-out sequence QSP, 6Bh ...
Page 110
... Dummy (ex.: 10) Micron Technology, Inc., reserves the right to change products or specifications without notice. N25Q064 - 1. switches from Input to Output ...
Page 111
... N25Q064 - 1.8V Figure 79. Read OTP instruction and data-out sequence QIO-SPI Instruction DQ0 DQ1 DQ2 DQ3 9.3.5 Write Enable (WREN) The Write Enable (WREN) instruction sets the Write Enable Latch (WEL) bit. Apart form the parallelizing of the instruction code on the four pins DQ0, DQ1, DQ2 and DQ3, the ...
Page 112
... Program of the Extended SPI protocol, please refer to Fast Program for further details. 112/154 Instruction DQ0 DQ1 DQ2 DQ3 Quad_Write_Disable Micron Technology, Inc., reserves the right to change products or specifications without notice. N25Q064 - 1.8V Section 9.1.11: Write Disable Section 9.1.16: Quad Input Extended ©2010 Micron Technology, Inc. All rights reserved. ...
Page 113
... N25Q064 - 1.8V Figure 82. Quad Command Page Program instruction sequence QIO-SPI, 02h S Mode Mode 0 DQ0 DQ1 DQ2 DQ3 *Address bit A23 is “Don’t Care.” Figure 83. Quad Command Page Program instruction sequence QIO-SPI, 12h ...
Page 114
... Address byte1 Micron Technology, Inc., reserves the right to change products or specifications without notice. N25Q064 - 1.8V 515 517 15 514 516 518 Data 254 255 ...
Page 115
... N25Q064 - 1.8V 9.3.9 Subsector Erase (SSE) The Subsector Erase (SSE) instruction sets to '1' (FFh) all bits inside the chosen subsector. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. Apart form the parallelizing of the instruction code and the address on the four pins DQ0, ...
Page 116
... Section 9.1.20: Bulk Erase (BE Instruction DQ0 DQ1 DQ2 DQ3 Micron Technology, Inc., reserves the right to change products or specifications without notice. N25Q064 - 1. for further details. ©2010 Micron Technology, Inc. All rights reserved. ...
Page 117
... N25Q064 - 1.8V suspended and erased while that Subsector Erase, Bulk Erase, Write Non Volatile Configuration register and Program OTP can not be suspended. Apart form parallelizing the instruction code on four pins (DQ0, DQ1, DQ2, DQ3) the instruction functionality is the same as the Program/Erase Suspend (PES) instruction of the Extended SPI protocol ...
Page 118
... Micron Technology, Inc., reserves the right to change products or specifications without notice. N25Q064 - 1.8V Section 9.1.23: Read ...
Page 119
... N25Q064 - 1.8V 9.3.15 Write status register (WRSR) The write status register (WRSR) instruction allows new values to be written to the status register. Before it can be accepted, a write enable (WREN) instruction must previously have been executed. The instruction code and the input data are sent on four pins DQ0, DQ1, DQ2 and DQ3. The ...
Page 120
... Micron Technology, Inc., reserves the right to change products or specifications without notice. N25Q064 - 1.8V Lock Register Out ...
Page 121
... N25Q064 - 1.8V Figure 94. Write to Lock Register instruction sequence QIO-SPI S C DQ0 DQ1 DQ2 DQ3 *Address bit A23 is “Don’t Care. ” 9.3.18 Read Flag Status Register The Read Flag Status Register (RFSR) instruction allows the Flag Status Register to be read. Apart form the parallelizing of the instruction code and the output data on the four pins DQ0, ...
Page 122
... Instruction DQ0 DQ1 DQ2 DQ3 Micron Technology, Inc., reserves the right to change products or specifications without notice. N25Q064 - 1. ...
Page 123
... N25Q064 - 1.8V Figure 97. Read NV Configuration Register instruction sequence QIO-SPI DQ0 DQ1 DQ2 DQ3 9.3.21 Write NV Configuration Register The Write Non Volatile Configuration register (WRNVCR) instruction allows new values to be written to the Non Volatile Configuration register. Before it can be accepted, a write enable (WREN) instruction must previously have been executed. ...
Page 124
... Configuration Register to be read. 124/154 Instruction Nonvolatile Configuration Register Byte MS Byte Micron Technology, Inc., reserves the right to change products or specifications without notice. N25Q064 - 1.8V ©2010 Micron Technology, Inc. All rights reserved. ...
Page 125
... N25Q064 - 1.8V Figure 99. Read Volatile Configuration Register instruction sequence QIO-SPI Instruction DQ0 DQ1 DQ2 DQ3 9.3.23 Write Volatile Configuration Register The Write Volatile Configuration register (WRVCR) instruction allows new values to be written to the Volatile Configuration register. Before it can be accepted, a write enable (WREN) instruction must previously have been executed. ...
Page 126
... Micron Technology, Inc., reserves the right to change products or specifications without notice. N25Q064 - 1. ...
Page 127
... N25Q064 - 1.8V 9.3.25 Write Volatile Enhanced Configuration Register The Write Volatile Enhanced Configuration register (WRVECR) instruction allows new values to be written to the Volatile Enhanced Configuration register. Before it can be accepted, a write enable (WREN) instruction must previously have been executed. Apart form the parallelizing of the instruction code and the input data on the four pins DQ0, ...
Page 128
... Extended SPI protocol. Figure 103. Deep Power-down instruction sequence Instruction DQ0 DQ1 DQ2 DQ3 128/154 t DP Standby mode Deep power-down mode Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2010 Micron Technology, Inc. All rights reserved. N25Q064 - 1.8V Quad_DP ...
Page 129
... N25Q064 - 1.8V 9.3.27 Release from Deep Power-down (RDP) Once the device has entered the Deep Power-down mode, all instructions are ignored except the Release from Deep Power-down (RDP) instruction. Executing this instruction takes the device out of the Deep Power-down mode. Apart form the parallelizing of the ...
Page 130
... Volatile Configuration Register bit 3 to enter XIP; rather, enter XiP directly by setting XIP Confirmation bit to 0 during the first dummy clock cycle after a fast read instruction.See 130/154 Section 16: Ordering information. Micron Technology, Inc., reserves the right to change products or specifications without notice. N25Q064 - 1.8V ©2010 Micron Technology, Inc. All rights reserved. ...
Page 131
... N25Q064 - 1.8V Figure 105. N25Q064 Read functionality Flow Chart Yes 10.1 Enter XIP mode: Set the Non Volatile Configuration Register To use the Non Volatile Configuration Register method to enter in XIP mode it is necessary to set the Non Volatile Configuration Register bits from with the pattern corresponding to the required XIP mode by mean of the Write Non Volatile Configuration Register (WRNVCR) instruction ...
Page 132
... A23-16 A15-8 A7-0 Dummy (ex.: 6) must be issued, and after that it is possible to enter, Table 24.: VCR XIP bits setting Section 16: Ordering Micron Technology, Inc., reserves the right to change products or specifications without notice. N25Q064 - 1. switches from Input to Output ...
Page 133
... N25Q064 - 1.8V Table 24. VCR XIP bits setting example 81h (WRVCR opcode) Figure 107. XiP: enter by VCR 2/2 (QIOFR in normal SPI protocol example) S Mode Mode 0 Instruction DQ0 Don’t Care DQ1 Don’t Care DQ2 DQ3 ‘1’ the XIP Confirmation bit and should be set as follows keep XIP state exit XIP mode and return to standard read mode. ...
Page 134
... S low (S becomes high before 26th clock cycle) The global effect is only to exit from XIP without any other reset. 134/154 Section 16: Ordering information. Section 16: Ordering information. Micron Technology, Inc., reserves the right to change products or specifications without notice. N25Q064 - 1.8V ©2010 Micron Technology, Inc. All rights reserved. ...
Page 135
... N25Q064 - 1.8V 11 Power-up and power-down At power-up and power-down, the device must not be selected (that is Chip Select (S) must follow the voltage applied on VCC) until VCC reaches the correct value: VCC(min) at power-up VSS at power-down A safe configuration is provided in To avoid data corruption and inadvertent write operations during power-up, a Power On Reset (POR) circuit is included ...
Page 136
... S low (S becomes high before 9th clock cycle) to force Normal SPI protocol. 136/154 threshold WI Parameter Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2010 Micron Technology, Inc. All rights reserved. N25Q064 - 1.8V Min Max Unit 150 µs 150 µs 1 ...
Page 137
... N25Q064 - 1.8V 12 Initial delivery state The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register contains 00h (all Status Register bits are 0). Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
Page 138
... ECOPACK® 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU. 2. JEDEC Std JESD22-A114A (C1 = 100 pF 1500 Ω 500 Ω). 138/154 Parameter (2) Micron Technology, Inc., reserves the right to change products or specifications without notice. N25Q064 - 1.8V Min Max Unit –65 150 °C ...
Page 139
... N25Q064 - 1. and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics tables that follow are derived from tests performed under the measurement conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters ...
Page 140
... MHz S = VCC S= VCC S = VCC – 0.7VCC IOL = 1.6 mA IOH = –100 uA VCC–0.2 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2010 Micron Technology, Inc. All rights reserved. N25Q064 - 1.8V Min Max Unit ± 2 µA ± 2 µA 100 µA 10 µA ...
Page 141
... N25Q064 - 1.8V Note: The following AC characteristics data is preliminary. Table 31. AC Characteristics (page Symbol Alt. Clock frequency for the all the fC fC instructions (Extended SPI, DIO-SPI and QIO-SPI protocol) but the READ instruction fR Clock frequency for read instructions (1) tCH tCLH Clock High time ...
Page 142
... A. For example int(12/ int(32/ int(15.3) =16. Figure 110. Reset AC waveforms while a program or erase cycle is in progress S Reset 142/154 Parameter Min tSHRH tRLRH Micron Technology, Inc., reserves the right to change products or specifications without notice. N25Q064 - 1.8V (2) Typ Max Unit 0 ...
Page 143
... N25Q064 - 1.8V Table 32. Reset Conditions Symbol Alt. Parameter (1)(2) tRLRH tRST Reset pulse width Reset Recovery (1) tRHSL tREC Time S# deselect to R (1) tSHRV valid 1. All values are guaranteed by characterization and not 100% tested in production. 2. The device reset is possible but not guaranteed if tRLRH < 50 ns. ...
Page 144
... DQ0 DQ1 Figure 113. Hold timing S C DQ1 DQ0 HOLD 144/154 High Impedance tHLCH tCHHL tCHHH tHLQZ Micron Technology, Inc., reserves the right to change products or specifications without notice. N25Q064 - 1.8V tSHWL AI07439c tHHCH tHHQX AI13746 ©2010 Micron Technology, Inc. All rights reserved. ...
Page 145
... N25Q064 - 1.8V Figure 114. Output timing S C tCLQV tCLQX DQ1 ADDR. DQ0 LSB IN Figure 115. VPP S C DQ0 V PPH V PP tCLQV tCLQX timing H tVPPHSL Micron Technology, Inc., reserves the right to change products or specifications without notice. DC and AC parameters tCH tCL LSB OUT End of command (identified by WIP polling) © ...
Page 146
... 5.75 3.40 5 4.75 — — 3.20 — — 3.80 — — 3.60 — — 4.30 Micron Technology, Inc., reserves the right to change products or specifications without notice. N25Q064 - 1. ddd aaa bbb ddd 4 1.27 0.10 0.60 — — — 0 0.50 — — — — 0.75 12° 0.15 0.10 0.05 ©2010 Micron Technology, Inc. All rights reserved. ...
Page 147
... N25Q064 - 1.8V Figure 117. VDFPN8 (MLP8) Very Thin Dual Flat Package No Leads, 8×6x1 mm Drawing A B Ø0 Drawing is not to scale. 2. The circle in the top view of the package indicates the position of pin 1. Table 34. VDFPN8 (MLP8) Very Thin Dual Flat Package No Leads 8×6x1 mm Dimensions ...
Page 148
... Symbol — — — 1.27 0.23 10.10 7.40 — 0.32 10.50 7.60 — Micron Technology, Inc., reserves the right to change products or specifications without notice. N25Q064 - 1. — — 1.27 — 5.02 7.62 — 0° 6.22 8.89 — 10° 45˚ ddd — — — ...
Page 149
... N25Q064 - 1.8V Figure 120. TBGA - mm, 24-Ball, Drawing 1. Drawing is not to scale. Package mechanical Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2010 Micron Technology, Inc. All rights reserved. 149/154 ...
Page 150
... Symbol aaa balls — balls — balls 0.15 Micron Technology, Inc., reserves the right to change products or specifications without notice. N25Q064 - 1. 7.90 — — 8.10 — — bbb ddd eee — — — — — — ...
Page 151
... N25Q064 - 1.8V 16 Ordering information Table 39. Ordering information scheme Example: Device type N25Q = serial Flash memory, Quad I/O, XiP Device density 064 = 064 Mbit Technology Feature set 1 = Byte addressability, Hold pin, Numonyx XiP 2 = Byte addressability, Hold pin, Basic XiP 3 = Byte addressability, Reset pin, Numonyx XiP ...
Page 152
... Block Features Structure Uniform SO8W Micron Technology, Inc., reserves the right to change products or specifications without notice. N25Q064 - 1.8V Temperature and Package Test Flow Industrial temp; Standard test flow ©2010 Micron Technology, Inc. All rights reserved. Security Standard ...
Page 153
... N25Q064 - 1.8V 17 Revision history Table 41. Document revision history Date Revision 24-Nov- 2010 1 Initial release. Micron Technology, Inc., reserves the right to change products or specifications without notice. Revision history Changes ©2010 Micron Technology, Inc. All rights reserved. 153/154 ...
Page 154
... This data sheet contains minimum and maximum limits specified over the power supply and temperature range set Although considered final, these specifications are subject to change, as further product development and data 154/154 forth herein. characterization sometimes occur. Micron Technology, Inc., reserves the right to change products or specifications without notice. N25Q064 - 1.8V ©2010 Micron Technology, Inc. All rights reserved. ...