NAND512W3A STMicroelectronics, NAND512W3A Datasheet
NAND512W3A
Manufacturer Part Number
NAND512W3A
Description
Manufacturer
STMicroelectronics
Specifications of NAND512W3A
Case
TSOP48
Date_code
2006+
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FEATURES SUMMARY
August 2005
HIGH DENSITY NAND FLASH MEMORIES
–
–
–
NAND INTERFACE
–
–
–
SUPPLY VOLTAGE
–
–
PAGE SIZE
–
–
BLOCK SIZE
–
–
PAGE READ / PROGRAM
–
–
–
COPY BACK PROGRAM MODE
–
FAST BLOCK ERASE
–
STATUS REGISTER
ELECTRONIC SIGNATURE
CHIP ENABLE ‘DON’T CARE’
–
SERIAL NUMBER OPTION
Up to 1 Gbit memory array
Up to 32 Mbit spare area
Cost effective solutions for mass storage
applications
x8 or x16 bus width
Multiplexed Address/ Data
Pinout compatibility for all densities
1.8V device: V
3.0V device: V
x8 device: (512 + 16 spare) Bytes
x16 device: (256 + 8 spare) Words
x8 device: (16K + 512 spare) Bytes
x16 device: (8K + 256 spare) Words
Random access: 12µs (3V)/15us (1.8V)
(max)
Sequential access: 50ns (min)
Page program time: 200µs (typ)
Fast page copy without external buffering
Block erase time: 2ms (Typ)
Simple interface with microcontroller
528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories
DD
DD
= 1.7 to 1.95V
= 2.7 to 3.6V
128 Mbit, 256 Mbit, 512 Mbit, 1 Gbit (x8/x16)
NAND512-A, NAND01G-A
NAND128-A, NAND256-A
Figure 1. Packages
HARDWARE DATA PROTECTION
–
DATA INTEGRITY
–
–
RoHS COMPLIANCE
–
DEVELOPMENT TOOLS
–
–
–
–
Program/Erase locked during Power
transitions
100,000 Program/Erase cycles
10 years Data Retention
Lead-Free Components are Compliant
with the RoHS Directive
Error Correction Code software and
hardware models
Bad Blocks Management and Wear
Leveling algorithms
File System OS Native reference software
Hardware simulation models
VFBGA55 8 x 10 x 1mm
VFBGA63 9 x 11 x 1mm
USOP48 12 x 17 x 0.65mm
TSOP48 12 x 20mm
FBGA
1/56
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