nb100ep223 ON Semiconductor, nb100ep223 Datasheet

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nb100ep223

Manufacturer Part Number
nb100ep223
Description
3.3v1 22 Differential Hstl/pecl To Hstl Clock Driver With Lvttl Clock Select And Output Enable
Manufacturer
ON Semiconductor
Datasheet

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NB100EP223
3.3V 1:22 Differential
HSTL/PECL to HSTL Clock
Driver with LVTTL Clock
Select and Output Enable
Description
designed with clock distribution in mind, accepting two clock sources
into an input multiplexer. The part is designed for use in low voltage
applications which require a large number of outputs to drive precisely
aligned low skew signals to their destination. The two clock inputs are
differential HSTL or LVPECL and they are selected by the CLK_SEL
pin which is LVTTL. To avoid generation of a runt clock pulse when
the device is enabled/disabled, the Output Enable (OE), which is
LVTTL, is synchronous ensuring the outputs will only be
enabled/disabled when they are already in LOW state (See Figure 7).
optimal design, layout, and processing minimize skew within a device
and from lot to lot. In any differential output pair, the same bias and
termination scheme is required. Unused output pairs should be left
unterminated (open) to “reduce power and switching noise as much as
possible.” Any unused single line of a differential pair should be
terminated the same as the used line to maintain balanced loads on the
differential driver outputs. The output structure uses an open emitter
architecture and will be terminated with 50 W to ground instead of a
standard HSTL configuration (See Figure 6). The wide VIHCMR
specification allows both pair of CLOCK inputs to accept LVDS
levels.
Features
*For additional information on our Pb−Free strategy and soldering details, please
© Semiconductor Components Industries, LLC, 2006
November, 2006 − Rev. 7
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
The NB100EP223 is a low skew 1−to−22 differential clock driver,
The NB100EP223 guarantees low output−to−output skew. The
Offset Voltage
with GND = 0 V, V
LVDS Termination Resistor
100 ps Typical Device−to−Device Skew
25 ps Typical Within Device Skew
HSTL Compatible Outputs Drive 50 W to Ground With No
Maximum Frequency >500 MHz
1 ns Typical Propagation Delay
LVPECL and HSTL Mode Operating Range: V
Q Output will Default Low with Inputs Open
Thermally Enhanced 64−Lead LQFP
CLOCK Inputs are LVDS−Compatible; Requires External 100 W
Pb−Free Packages are Available*
CCO
= 1.6 V to 2.0 V
CC
= 3 V to 3.6 V
1
*For additional marking information, refer to
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
Application Note AND8002/D.
CASE 848G
FA SUFFIX
LQFP−64
A
WL
YY
WW
G
ORDERING INFORMATION
http://onsemi.com
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
Publication Order Number:
64
DIAGRAM*
1
MARKING
AWLYYWWG
NB100
EP223
NB100EP223/D

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nb100ep223 Summary of contents

Page 1

... Driver with LVTTL Clock Select and Output Enable Description The NB100EP223 is a low skew 1−to−22 differential clock driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The part is designed for use in low voltage applications which require a large number of outputs to drive precisely aligned low skew signals to their destination ...

Page 2

... Pins will default LOW when left open. ** Pins will default HIGH when left open. *** The thermally conductive exposed pad on the bottom of the package is electrically connected to GND internally NB100EP223 Figure 1. 64−Lead LQFP Pinout (Top View) Table 2. FUNCTION TABLE ...

Page 3

LVPECL_CLK LVPECL_CLK V CC GND Table 3. ATTRIBUTES Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Moisture Sensitivity (Note 1) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, refer ...

Page 4

Table 5. LVPECL DC CHARACTERISTICS Symbol Characteristic I Power Supply Current CC V Input HIGH Voltage (Single−Ended Input LOW Voltage (Single−Ended Input HIGH Voltage Common Mode IHCMR Range (Differential) (Note 2) (Figure 4) LVPECL_CLK/LVPECL_CLK HSTL_CLK/HSTL_CLK I ...

Page 5

Table 8. AC CHARACTERISTICS V Symbol Characteristic V Differential Output Voltage Opp (Figure 3) t Propagation Delay (Differential) PLH t LVPECL_CLK to Q PHL t Within−Device Skew (Note 5) skew Device−to−Device Skew (Note 6) t Random Clock Jitter (Figure 3) ...

Page 6

V V IHCMR PP Figure 4. LVPECL Differential Input Levels HSTL OUTPUT Q Figure 6. HSTL Output Termination and AC Test Reference CLK CLK Figure 7. Output Enable (OE) Timing Diagram V (LVPECL (DIFF) IH ...

Page 7

... NB100EP223. The size of the land pattern can be larger, smaller, or even take on a different shape than the exposed pad on the package. However, the solderable area should be at least the same size and shape as the exposed pad on the package ...

Page 8

... ORDERING INFORMATION Device NB100EP223FA NB100EP223FAG NB100EP223FAR2 NB100EP223FAR2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D AN1406/D AN1503/D AN1504/D AN1568/D AN1672/D AND8001/D − Odd Number Counters Design AND8002/D − ...

Page 9

M M/2 AJ −Z− −X− A/2 A DETAIL AH −T− AG G/2 SEATING 4 PL PLANE 0.08 (0.003) T X− EXPOSED PAD ...

Page 10

... N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 http://onsemi.com 10 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NB100EP223/D ...

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