nb100lvep17 ON Semiconductor, nb100lvep17 Datasheet

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nb100lvep17

Manufacturer Part Number
nb100lvep17
Description
2.5v / 3.3v Quad Differential Driver/receiver
Manufacturer
ON Semiconductor
Datasheet

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NB100LVEP17
2.5V / 3.3V Quad Differential
Driver/Receiver
Description
incorporates two stages of gain, internal to the device, making it an
excellent choice for use in high bandwidth amplifier applications.
this device only. For single-ended input conditions, the unused
differential input is connected to V
V
and V
to 0.5 mA. When not used, V
operation of the rest of the device.
Features
© Semiconductor Components Industries, LLC, 2006
November, 2006 − Rev. 7
BB
The NB100LVEP17 is a 4-bit differential line receiver. The design
The V
Inputs of unused gates can be left open and will not affect the
with V
with V
Maximum Input Clock Frequency > 2.5 GHz Typical
Maximum Input Data Rate > 2.5 Gb/s Typical
250 ps Typical Propagation Delay
Low Profile QFN Package
PECL Mode Operating Range: V
NECL Mode Operating Range: V
Q Output Will Default LOW with Inputs Open or at V
V
Pb−Free Packages are Available
BB
may also rebias AC coupled inputs. When used, decouple V
CC
Output
BB
via a 0.01 mF capacitor and limit current sourcing or sinking
EE
EE
pin, an internally generated voltage supply, is available to
= −2.375 V to −3.8 V
= 0 V
BB
should be left open.
BB
CC
CC
as a switching reference voltage.
= 2.375 V to 3.8 V
= 0 V
EE
1
BB
*For additional marking information, refer to
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
Application Note AND8002/D.
(Note: Microdot may be in either location)
CASE 948E
24 PIN QFN
MN SUFFIX
CASE 485L
DT SUFFIX
TSSOP−20
24
ORDERING INFORMATION
A
L
Y
W
G
1
http://onsemi.com
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
Publication Order Number:
1
DIAGRAMS*
NB100LVEP17/D
MARKING
24
ALYWG
VP17
N100
ALYWG
VP17
N100
G
G

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nb100lvep17 Summary of contents

Page 1

... NB100LVEP17 2.5V / 3.3V Quad Differential Driver/Receiver Description The NB100LVEP17 is a 4-bit differential line receiver. The design incorporates two stages of gain, internal to the device, making it an excellent choice for use in high bandwidth amplifier applications. The V pin, an internally generated voltage supply, is available to BB this device only. For single-ended input conditions, the unused ...

Page 2

Table 1. PIN DESCRIPTION Pin Á Á Á Á Á Á Á Á Á TSSOP QFN Name Á Á Á Á Á Á Á Á Á 1,20 13,18,21 22, 2,4,6,8 ...

Page 3

... Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/ NB100LVEP17 Figure 3. QFN−24 Lead Pinout (Top View) Value (R1) ...

Page 4

Table 3. MAXIMUM RATINGS Symbol Parameter V Positive Mode Power Supply CC V Negative Mode Power Supply EE V Positive Mode Input Voltage I Negative Mode Input Voltage I Output Current out I V Sink/Source Operating Temperature ...

Page 5

Table 5. DC CHARACTERISTICS, PECL Symbol Characteristic I Negative Power Supply Current EE V Output HIGH Voltage (Note Output LOW Voltage (Note Input HIGH Voltage (Single−Ended Input LOW Voltage (Single−Ended ...

Page 6

Table 7. AC CHARACTERISTICS V Symbol Characteristic V Output Voltage Amplitude OUTPP (See Figures Propagation Delay to Output Differential PLH t PHL t Pulse Skew (Note 15) Skew Within Device Skew (Note 17) Device−to−Device Skew (Note ...

Page 7

Q AMP (mV) 650 550 450 350 RMS JITTER (ps) 250 0.5 1.0 1.5 INPUT FREQUENCY (GHz) Figure 4. Output Voltage Amplitude (V Input Frequency ( 2.5 V, Ambient Temperature in CC 850 750 ...

Page 8

... ORDERING INFORMATION Device NB100LVEP17DT NB100LVEP17DTG NB100LVEP17DTR2 NB100LVEP17DTR2G NB100LVEP17MN NB100LVEP17MNG NB100LVEP17MNR2 NB100LVEP17MNR2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. *This package is inherently Pb−Free. Resource Reference of Application Notes ...

Page 9

... 0.100 (0.004) −T− SEATING PLANE 16X 0.36 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. PACKAGE DIMENSIONS TSSOP−20 CASE 948E−02 ISSUE ...

Page 10

... FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MILLIMETERS DIM MIN MAX A 0.80 1.00 A1 0.00 0.05 A2 0.60 0.80 A3 0.20 REF b 0.23 0.28 D 4.00 BSC D2 2.70 2.90 E 4.00 BSC E2 2.70 2.90 e 0.50 BSC L 0.35 0.45 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NB100LVEP17/D ...

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