nb6n14s ON Semiconductor, nb6n14s Datasheet

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nb6n14s

Manufacturer Part Number
nb6n14s
Description
3.3 V 1 4 Anylevel Differential Input To Lvds Fanout Buffer/translator
Manufacturer
ON Semiconductor
Datasheet

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NB6N14S
3.3 V 1:4 AnyLevelt
Differential Input to LVDS
Fanout Buffer/Translator
accept AnyLevelt differential input signals: LVPECL, CML or
LVDS. These signals will be translated to LVDS and four identical
copies of Clock or Data will be distributed, operating up to 2.0 GHz or
2.5 Gb/s, respectively. As such, the NB6N14S is ideal for SONET,
GigE, Fiber Channel, Backplane and other Clock or Data distribution
applications.
GND + 50 mV to V
termination resistors at the inputs, the NB6N14S is ideal for
translating a variety of differential or single−ended Clock or Data
signals to 350 mV typical LVDS output levels.
package. Application notes, models, and support documentation are
available at www.onsemi.com.
performance products.
Features
© Semiconductor Components Industries, LLC, 2007
April, 2007 − Rev. 4
The NB6N14S is a differential 1:4 Clock or Data Receiver and will
The NB6N14S has a wide input common mode range from
The NB6N14S is offered in a small 3 mm x 3 mm 16−QFN
The NB6N14S is a member of the ECLinPS MAXt family of high
SG Devices
Maximum Input Clock Frequency > 2.0 GHz
Maximum Input Data Rate > 2.5 Gb/s
1 ps Maximum RMS Clock Jitter
Typically 10 ps Data Dependent Jitter
380 ps Typical Propagation Delay
120 ps Typical Rise and Fall Times
V
TIA/EIA − 644 Compliant
Functionally Compatible with Existing 3.3 V LVEL, LVEP, EP, and
These are Pb−Free Devices
REF_AC
PRBS 2
Figure 2. Typical Output Waveform at 2.488 Gb/s with
Reference Output
23−1
(V
CC
INPP
− 50 mV. Combined with the 50 W internal
Device DDJ = 10 ps
= 400 mV; Input Signal DDJ = 14 ps)
TIME (58 ps/div)
1
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
VT
/IN
IN
(LVTTL/CMOS)
EN
*For additional marking information, refer to
CASE 485G
MN SUFFIX
(Note: Microdot may be in either location)
Application Note AND8002/D.
50
50
QFN−16
1
W
W
V
ORDERING INFORMATION
REF_AC
Figure 1. Logic Diagram
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
http://onsemi.com
D
Publication Order Number:
1
Q
DIAGRAM*
16
MARKING
ALYW G
NB6N
14S
G
NB6N14S/D
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3

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nb6n14s Summary of contents

Page 1

... NB6N14S is ideal for translating a variety of differential or single−ended Clock or Data signals to 350 mV typical LVDS output levels. The NB6N14S is offered in a small 16−QFN package. Application notes, models, and support documentation are available at www.onsemi.com. The NB6N14S is a member of the ECLinPS MAXt family of high performance products ...

Page 2

... V GND NB6N14S Figure 3. NB6N14S Pinout, 16−pin QFN Table 2. PIN DESCRIPTION Pin Name I LVDS Output 2 Q1 LVDS Output 3 Q2 LVDS Output 4 Q2 LVDS Output 5 Q3 LVDS Output 6 Q3 LVDS Output 7 V − ...

Page 3

... Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 4. JEDEC standard multilayer board − 1S2P (1 signal, 2 power) with 8 filled thermal vias under exposed pad. NB6N14S Characteristics Oxygen Index Human Body Model ...

Page 4

... Input termination pins open, D/D at the DC level within V 10. Parameter guaranteed by design verification not tested in production. 11. V used to rebias capacitor−coupled inputs only (see Figures 10 and 11). REF_AC NB6N14S = 3 3.6 V, GND = −40°C to +85° − ...

Page 5

... The worst case condition between Q0/Q0 and Q1/Q1 from either D0/D0 or D1/D1, when both outputs have the same transition. 400 350 300 250 200 150 100 Figure 4. Output Voltage Amplitude (V Input Clock Frequency (f NB6N14S = 3 3.6 V, GND = 0 V; (Note 12) −40°C Min Typ Max 2.0 ≤ 1.0 GHz ) f 220 350 INPPmin ...

Page 6

... Device DDJ = 10 ps TIME (58 ps/div) Figure 5. Typical Output Waveform at 2.488 Gb/s with PRBS 100 mV; Input Signal DDJ = 14 ps) INPP http://onsemi.com NB6N14S 23−1 and OC48 mask 6 ...

Page 7

... NB6N14S = 50 W CLK OPEN CLK Figure 7. LVDS Interface NB6N14S = 50 W CLK CLK NB6N14S = 50 W CLK ...

Page 8

... Figure 15. Differential Input Driven Single−Ended IHmax V thmax V ILmax IHmin V thmin V IN ILmin GND Figure 17. V Diagram th NB6N14S D V INPP OUTPP Q t PHL t PLH Figure 12. AC Reference Measurement = 100 Figure 14. LVDS Output Figure 16 ...

Page 9

... Device NB6N14SMNG QFN−16 NB6N14SMNR2G QFN−16 †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. NB6N14S Figure 19. EN Timing Diagram Package (Pb− ...

Page 10

... AND FLAG MILLIMETERS DIM MIN MAX A 0.80 1.00 A1 0.00 0.05 A3 0.20 REF b 0.18 0.30 D 3.00 BSC D2 1.65 1.85 E 3.00 BSC E2 1.65 1.85 e 0.50 BSC K 0.18 TYP L 0.30 0.50 SOLDERING FOOTPRINT* 3.25 0.128 0.30 EXPOSED PAD 0.012 1.50 0.059 0.30 0.012 0.50 0.02 mm SCALE 10:1 inches ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NB6N14S/D ...

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