NJU26203 New Japan Radio Co.,Ltd, NJU26203 Datasheet
NJU26203
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NJU26203 Summary of contents
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... DDIO Input Terminal : +5.0V Input tolerant Package : SSOP44 (Pb-Free) * The detail hardware specification of the NJU26203 is described in the “ NJU26200 Series Hardware Data Sheet”. Ver.2007-02-28 Dolby Pro Logic II Decoder : 12.288MHz(Standard), built-in PLL Circuit : 4 Input ports / 4 Output ports 24bit, left-justified ...
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... GENERATION DATA DATA DATA DATA FIRMWARE FIRMWARE FIRMWARE FIRMWARE RAM RAM ROM ROM RAM RAM ROM ROM Fig. 1 NJU26203 Hardware Block Diagram SERIAL SERIAL SERIAL AUDIO SERIAL AUDIO AUDIO AUDIO INTERFACE INTERFACE INTERFACE INTERFACE L/R L/Rｏｕｔ ｏｕｔ L/R L/R ｏｕｔ ...
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... Function Block Diagram SDI0 SDI1 SDI2 SDI3 L/R Fig. 2 NJU26203 Function Block Diagram (Firmware) SDI0 SDI1 L/R Fig. 3 NJU26203 Function Block Diagram (Stereo Input) Ver.2007-02-28 4 Stereo L/R->LS/RS 6 Stereo L/R->C/SW L/R->LS/RS Pro Logic II SW LFE Generator Noise Generator Smooth Control 4 Stereo L/R->LS/RS Pro Logic II SW LFE Generator Noise Generator ...
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... NJU26203 SDI0 SDI1 SDI2 LFE Output Trim SDI3 Fig. 4 NJU26203 Function Block Diagram (Multi channel input) SDI0 SDI1 Fig. 5 NJU26203 Function Block Diagram (Stereo Input, NON-FADER (6ch Stereo L/R C/SW LS/RS Noise Generator Smooth Control 6 Stereo L/R->C/SW L/R->LS/RS Noise Generator Smooth Control L 5 Band PEQ SDO1 ...
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... BCKI 7 VSS 8 VDD 9 TEST 10 MUTEb 11 WDC 12 PROC 13 VSSIO 14 VDDIO 15 SEL 16 VDDPLL 17 VSSPLL 18 VSS 19 VDD 20 CLKOUT 21 CLK 22 Ver.2007-02-28 NJU26203 SSOP44 Fig. 6 NJU26203 Pin Configuration NJU26203 44 VDD 43 VSS 42 VSSIO 41 VDDIO 40 SDO0 39 SDO1 38 SDO2 37 SDO3 36 LRO 35 BCLO 34 MCK 33 VDDIO 32 SDA/SDOUT 31 SCL/SCK 30 AD2/SSb 29 AD1/SDIN 28 TEST ...
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... NJU26203 Pin Description Table 1 Pin Description Pin No. Symbol 1 SDI3 2 SDI2 3 SDI1 4 SDI0 5 LRI 6 VDDIO 7 BCKI 8 VSS 9 VDD 10 TEST * 11 MUTEb * 12 WDC * 13 PROC * 14 VSSIO 15 VDDIO 16 SEL 17 VDDPLL 18 VSSPLL 19 VSS 20 VDD 21 CLKOUT 22 CLK 23 VSSIO 24 VDDIO 25 RESETb 26 TEST 27 TEST 28 TEST 29 AD1/SDIN 30 AD2/SSb 31 SCL/SCK 32 SDA/SDOUT 33 VDDIO ...
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... SDO3 Host Interface The NJU26203 can be controlled via Serial Host Interface (SHI) using either of two serial bus formats : I 4-Wire serial bus. Data transfers are in 8 bits packets (1 byte) when using either format. The SHI operates only in a SLAVE fashion. A host controller connected to the interface always drives the clock (SCL / SCK) line and initiates data transfers, regardless of the chosen communication protocol ...
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... I C Bus When the NJU26203 is configured for I data on the SDA pin and clocks data on the SCL pin. The SDA is an open drain pin requiring a pull-up resistance. Pins AD1 and AD2 are used to configure the seven-bit SLAVE address of the serial host interface. (Table 6) ...
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... NJU26203 operation. For example, a microcomputer monitors the WDC clock and checks the status of the NJU26203. When the WDC clock pulse is lost or not normal clock cycle, the NJU26203 does not operate correctly. Then reset the NJU26203 and set up the NJU26203 again. The WDC clock is able to be variable for 0msec to 100msec by command ...
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... Nop Command Notes : In respect to detail command information, request New Japan Radio Co., Ltd. and permission of a licenser (Dolby) is required. Response of status NJU26203 returns the response of 4 types to the host controller. Table 10 Response of status Response Status : Command Accepted Status : Command Error Status : Command Process ...
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... License Information The Word “DOLBY”, “Pro Logic II” and the double D mark are trademarks of Dolby Laboratories. The NJU26203 can only be delivered to licensees of Dolby Laboratories. Please refer to the licensing application manual issued by Dolby Laboratories. Ver.2007-02-28 NJU26203 [CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions ...