NJU6676 New Japan Radio Co., Ltd., NJU6676 Datasheet
NJU6676
Related parts for NJU6676
NJU6676 Summary of contents
Page 1
... X 132-Segment plus 1-Icon Bit Map Type LCD Controller and Driver GENERAL DESCRIPTION The NJU6676 is a bit map LCD driver to display graphics or characters. It contains 8,580 bits display data RAM, microprocessor interface decoder, 132-segment drivers, 64-common drivers and 1- icon drivers. The bit image display data is transferred to the display data RAM by serial or 8-bit parallel interface ...
Page 2
... VDD VDD M/S CLS VSS C86 P/S VDD VSS VDD DUMMY2 DUMMY4 S131 S130 Y X Chip Center : X=0um, Y=0um Chip Size Chip Thickness : 675um Bump Size Pad Pitch Bump Height : 15um(Typ.) Bump Material : DUMMY3 NJU6676 PRELIMINARY :X=8.72mm,Y=2.37mm 30um : 45um x 83um : 60um(Min.) ...
Page 3
... C16 -1025 93 C15 -1025 94 C14 -1025 95 C13 -1025 96 C12 -1025 97 C11 -1025 98 C10 -1025 99 C9 -1025 100 C8 NJU6676 PRELIMINARY X(um) Y(um) 1655 -1025 1715 -1025 1775 -1025 1835 -1025 1895 -1025 1955 -1025 2015 -1025 2075 -1025 2135 -1025 2195 -1025 2255 -1025 ...
Page 4
... S83 1025 195 S84 1025 196 S85 1025 197 S86 1025 198 S87 1025 199 S88 1025 200 S89 NJU6676 PRELIMINARY X(um) Y(um) 1533 1025 1473 1025 1413 1025 1353 1025 1293 1025 1233 1025 1173 1025 1113 1025 1053 1025 ...
Page 5
... NJU6676 PRELIMINARY X(um) Y(um) -4200 565 -4200 505 -4200 445 -4200 385 -4200 325 -4200 265 -4200 205 -4200 145 -4200 85 ...
Page 6
... Display Data Latch Display Data RAM 65 X 132 = 8,580-bit Colum Address Recoder Colum Address Counter Colum Address Register Multiplexer Status Busy Flag MPU Interface CS1 CS2 NJU6676 PRELIMINARY C63 - - - - C32 COMM Common Drivers Shift Register Common Timing Display Timing Ocsailator Bus Holder P/S ...
Page 7
... Chip select terminal. Data Input/Output are available during CS1=”L” and 10 CS2 CS2=”H”. Description V1 V2 Description Description terminal. Data from SI is loaded at the rising edge of SCL and latched as the parallel data at 8th rising edge of SCL Display Data Instruction NJU6676 PRELIMINARY V3 V4 (VLCD=VDD-V5) ...
Page 8
... When CLS=”L”, input the display clock through the CL terminal. 68 M/S This terminal selects the master/slave operation for the NJU6676. Master operation outputs the timing signals that are required for the LCD display, while slave operation inputs the timing signals required for the LCD, synchronizing the LCD system. M/S = ” ...
Page 9
... Dummy Pad) Description CLS CL “H” Output “L” Input * Input *:Don’t Care DOF Off Off Off Description S131 C63 Output Voltage FR Normal Reverse H VDD VDD Output Voltage VDD NJU6676 PRELIMINARY ...
Page 10
... The DDRAM contains 8,580-bit, and stores display data which is 1 -to-1 correspondents to LCD panel pixels. When normal display mode, the display data “1” turns on and “0” turns off LCD pixels. When inverse display mode, “1” turns off and “0” turns on. NJU6676 PRELIMINARY ...
Page 11
... Display Pattern Page Page Page Page 7 Page NJU6676 PRELIMINARY Line Common Addres Driver s (00)H COM0 01 COM1 02 COM2 03 COM3 04 COM4 05 COM5 06 COM6 07 COM7 Initial 08 COM8 09 COM9 0A COM10 0B COM11 0C COM12 ...
Page 12
... LCD drivers consist of 64-common drivers, 132-segment divers and 1-icon-common driver. As shown in Fig.7, LCD driving waveforms are generated by the combination of display data, common timing signal and internal FR timing signal. Common drivers 77 C0 ------------------------------ C31 COM0 ------------------ COM31 COM63 ----------------- COM32 : (00)H : Normal mode (D3=0) : (20)H NJU6676 PRELIMINARY 275 244 C63 ---------------------------- C32 COM63 ----------------- COM32 COM0 ------------------ COM31 ...
Page 13
... LCD driving waveform on the two frame alternative driving method. e) Common timing generation The common timing is generated by display clock CL (refer to Fig.2) Fig.2 Display Timing COM0 COM1 RAM data SEG Fig.2 Waveform of Display Timing NJU6676 PRELIMINARY ...
Page 14
... Status 1 :On 1 : Voltage Voltage converter regulator Off Off Off NJU6676 PRELIMINARY 0: Off 0: Off 0: Off Voltage External followers voltage On On Vss2 On On Vout, Vss2 Off On V5, Vss2 Off Off Capacito r terminals Use Open ...
Page 15
...
Page 16
... NJU6676 PRELIMINARY :Off Specify DDRAM line address for COM0 DDRAM page address DDRAM column address of upper 4-bits 0 ...
Page 17
... NJU6676 PRELIMINARY D0 Display On or Off 0 0 :Off 1 1 :On D0 Line address for COM0 Page address ...
Page 18
... When D4 is “1”, the LSI is during reset operation ADC On/Off RESET 0 NJU6676 PRELIMINARY D0 A4 Upper 4-bit A0 Lower 4-bit A0 Column address 130 1 131 ...
Page 19
... Write Data Read Data NJU6676 PRELIMINARY Segment driver direction 0 Normal 1 Inverse D0 Display status 0 Normal 1 Inverse D0 Entire display on/off 0 Normal 1 Entire display on ...
Page 20
... Page address set Column address set Read modi f y write Dummy read Data read Data write Dummy read Data read Data write Repeat End No Finish? Yes NJU6676 PRELIMINARY D0 LCD bias 0 1 Set address for cursor line Start “read modify Inverse data in MPU End “ ...
Page 21
... Please refer to (1-7) common driver direction for more detail Return N+1 N+2 N+3 : (00)H : (00)H : (0) page : Normal mode (D3= NJU6676 PRELIMINARY D0 0 N+m N End Common driver direction * Normal Inverse ...
Page 22
... This instruction controls LCD driving waveform output through the COM/SEG terminals The NJU6676 contains low power LCD driving voltage generator circuit reducing own operating current. Therefore , it requires the following sequence procedures at power on for power source stabilized operation ...
Page 23
... NJU6676 PRELIMINARY Turn OFF sequence Display OFF Entire Display OFF Internal Power Supply OFF Or External Power Supply OFF LCD Drivier OFF V5 Minimum ： ： ： Maximum Static indicator Off On ...
Page 24
... Fig.5 The sequence of power save mode Release Sleep mode Static indicator off Power save on (Dual instructions) Sleep mode Power save off Entire display off + Static indicator on NJU6676 PRELIMINARY D1 D0 Status 0 0 Off (Blink at 1.0 s intervals (Blink at 0.5s intervals (Turn on at all time) ...
Page 25
... The voltage converter requires external capacitors for boosting as shown in Fig.7. Fig.7 The capacitors connection for the voltage regulator: 4x boost Vss2 + Vout C3- + C1+ C1- C2- + C2+ VDD Vss2 Vout= 4x (VDD-Vss2) 3x boost Vss2 + Vout C3- + C1+ C1- C2- + C2+ VDD Vss2 Vout= 3x (VDD-Vss2) NJU6676 PRELIMINARY 2x boost Vss2 + Vout C3- + C1+ C1- C2- C2+ VDD Vss2 Vout= 2x (VDD-Vss2) ...
Page 26
... Voltage regulator VREG + - Vout ---[ 100 101 : : : : 160 161 162 NJU6676 PRELIMINARY VDD VLCD V5 VREG (99/162) x (VDD-Vss2) Minimum (100/162) x (VDD-Vss2) : (101/162) x (VDD-Vss2 (160/162) x (VDD-Vss2) (161/162) x (VDD-Vss2) : (162/162) x (VDD-Vss2) Maximum ...
Page 27
... VLCD setting example We recommend the total value of Ra and Rb is between 1M Rb=4M and VDD=3V, the VLCD is calculated as follows: The minimum VLCD: VLCD =(1+Rb/Ra) X VREG =(1+4/1) X [(99/162) X 3.0] =9.15V The maximum VLCD: VLCD =(1+Rb/Ra) X VREG =(1+4/1) X [(162/162) X 3.0] =15.0V NJU6676 PRELIMINARY and 5M . When using Ra=1M , ...
Page 28
... When VSS < V5 --- VOUT=VSS And it is supplied to the LCD driving circuits after the Using the external Power Supply ＊2 External Voltage Generator Reference set up value VLCD=VDD-V5=9.0 to 10.5V NJU6676 PRELIMINARY VSS C1- C1+ C3- C2+ C2- VOUT NJU6676 V5 VR VDD 1.0ｕF COUT C1/C2/C3 1.0ｕ 0.1 0.47ｕF R1 2MΩ ...
Page 29
... MPU interface (5-1) Interface type selection NJU6676 interfaces with MPU by 8-bit bidirectional data bus (D7 to D0) or serial (SI:D7). The 8 bit parallel or serial interface is determined by a condition of the P/S terminal connecting to "H" or "L" level as shown in Table 4. In case of the serial interface, status and RAM data read out operation is impossible ...
Page 30
... A0="H" is display data and A0="L" is instruction. When RES terminal becomes "L" or CS1 terminal becomes "H" before 8th serial clock rise edge, NJU6676 recognizes them as a instruction data incorrectly. Therefore a unit of serial data must be structured by 8-bit. The time chart for the serial interface is shown in Fig ...
Page 31
... Access to the Display Data RAM and Internal Register. The NJU6676 is operating as one of pipeline processor by the bus-holder connecting to the internal data bus to adjust the operation frequency between MPU and the Display Data RAM or Internal Register. For example, when the MPU reads out the data from the Display Data RAM, the read out data in the data read cycle (dummy read) is held in the bus-holder, then it is read out from the bus-holder to the system bus at the next data read cycle ...
Page 32
... In case of CS1=”H” or CS2=”L”, the are high impedance and A0, RD, WR, D7(SI) and D6(SCL) inputs are ignored. If the serial interface is selected when CS1= ”H” or CS2= ”L”, the shift register and the counter are reset. However, the reset is always operated in any conditions of CS1 and CS2. NJU6676 PRELIMINARY ...
Page 33
... Note4) The decoupling capacitor between VDD terminal and Vss terminal is required in order to stabilize the LSI operation. Ratings -0.3 to +7.0 -7.0 to+0.3 -6.0 to +0.3 (When using 3x voltage converter) -4.5 to +0.3 (When using 4x voltage converter) -18 +0.3 -0.3 to VDD+0.3 -30 to +80 -55 to +100 (TCP) -55 to +125 (Chip) , the external power should be turn on at NJU6676 PRELIMINARY Ta=25 C Unit ...
Page 34
... C1 to C3, Cout=1.0uF - Using x4 booster Voltage converter off VDD -18.0V Voltage regulator off VDD -18.0V When sleep mode - When standby mode - VDD=3V, V5=-11V - Checker flag display - Without MPU access - All COM/SEG open - VDD=3V, Ta=25 C NJU6676 PRELIMINARY Typ. Max. Unit Note - 3 5 VDD-2 VDD VDD ...
Page 35
... Vss Operating Condition Voltage Voltage converter regulator On On Off On Off Off Off Off C2- C1- C1+ C3 C2+ C2- C1- C1+ C3 C2+ C2- C1- C1+ C3- NJU6676 PRELIMINARY External Voltage Supply Voltage (Input Terminal) followers On Use(VSS2) On Use(VOUT,VSS2) On Use(V5,VSS2) Off Use(V1 V5) Vout Vout Vout ...
Page 36
... IDD4 VDD A Vss C2+ C2- C1- C1+ C3- NJU6676 PRELIMINARY Vout ...
Page 37
... VDD=4.5 to 5.5V, Ta=- Terminal Symbol A0,CS1, tAH8 CS2 tAW8 tcyc8 tCCHR WR,RD tCCHW tCCLR tCCLW tDS8 tDH8 D7 D0 tACC8 tOH8 CS1,CS2 RW,RD,A0, tr, NJU6676 PRELIMINARY tAH8 tCCL tDS8 tDH8 tr tOH8 Condition Min. Max 166 - ...
Page 38
... CS1,CS2 RW,RD,A0, tr, (Vss=0V, VDD=2.2 to 2.7V, Ta=- Terminal Symbol Condition A0,CS1, tAH8 CS2 tAW8 tcyc8 tCCHR WR,RD tCCHW tCCLR tCCLW tDS8 tDH8 D7 D0 tACC8 CL=100pF tOH8 CS1,CS2 RW,RD,A0, tr, NJU6676 PRELIMINARY Min. Max. Unit 300 - 120 - ...
Page 39
... VDD=4.5 to 5.5V, Ta=- Terminal Symbol Condition tAH6 A0,CS1, tAW6 CS2 tcyc6 tCCHR tCCHW E tCCLR tCCLW tDS6 tDH6 D7 D0 tACC6 CL=100pF tOH6 E,R/W,A0, tr, NJU6676 PRELIMINARY tf tAH6 tDH6 tOH6 Min. Max. Unit 166 - ...
Page 40
... CL=100pF tOH6 E,R/W,A0, tr, (Vss=0V, VDD=2.2 to 2.7V, Ta=- Terminal Symbol Condition tAH6 A0,CS1, tAW6 CS2 tcyc6 tCCHR tCCHW E tCCLR tCCLW tDS6 tDH6 D7 D0 tACC6 CL=100pF tOH6 E,R/W,A0, tr, NJU6676 PRELIMINARY Min. Max. Unit 300 - ns 120 - ...
Page 41
... VDD=4.5 to 5.5V, Ta=- Terminal Symbol Condition tscyc SCL tSHW tSLW tSAS A0 tSAH tSDS SI tSDH tCSS CS1,CS2 tCSH SCL,A0, tr,tf CS1,CS2,SI NJU6676 PRELIMINARY tCSH tSAH tSHW tSDH Min. Max. 200 - 100 - 100 - 100 - 15 Unit ...
Page 42
... SI tSDH tCSS CS1,CS2 tCSH SCL,A0, tr,tf CS1,CS2,SI (Vss=0V, VDD=2.2 to 2.7V, Ta=- Terminal Symbol Condition tscyc SCL tSHW tSLW tSAS A0 tSAH tSDS SI tSDH tCSS CS1,CS2 tCSH SCL,A0, tr,tf CS1,CS2,SI NJU6676 PRELIMINARY Min. Max. Unit 250 - ns 100 - ns 100 - ns 150 - ns 150 - ns 100 - ns 100 - ns 150 - ns 150 ...
Page 43
... CL=50pF DFR tRW During reset (V Symbol Condition t R RES Symbol Condition t R RES Symbol Condition t R RES t RW NJU6676 PRELIMINARY =0V, V =4.5~5.5V, Ta=-30~80° Min. Typ. Max. Unit - =0V, V =2.7~4.5V, Ta=-30~80° Min. Typ. Max. Unit - =0V, V =2.2~2.7V, Ta=-30~80° Min ...
Page 44
... COM -SEG NJU6676 PRELIMINARY ...
Page 45
... CIRCUIT - Microprocessor Interface Example The NJU6676 interfaces to 80 type or 68 type MPU directly. And the serial interface also communicates with MPU C86 terminal must be fixed VDD or VSS Type MPU VCC MPU GND l 68 Type MPU VCC MPU GND l Serial Interface ...
Page 46
... Driving Application Circuits Example (Common and Segment Drivers Extension by using two of NJU6676) SEG COM NJU6676 Master [CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are ...