P87C552 NXP Semiconductors, P87C552 Datasheet
P87C552
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P87C552 Summary of contents
Page 1
... P87C552 80C51 8-bit microcontroller 8K/256 OTP, 8 channel 10 bit A/D, I capture/compare, high I/O, low voltage (2 5.5 V), low power Product data Supersedes data of 1999 Mar 30 hilips Semiconductors INTEGRATED CIRCUITS 2 C, PWM, 2003 Apr 01 ...
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... Idle mode – Power down mode Second DPTR register ALE inhibit for EMI reduction Programmable I/O pins Wake-up from power-down by external interrupts Software reset Power-on detect reset ADC charge pump disable ONCE mode ADC active in Idle mode 2 Product data P87C552 853-2410 29338 ...
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... Philips Semiconductors 80C51 8-bit microcontroller 8K/256 OTP, 8 channel 10 bit A/D, I capture/compare, high I/O, low voltage (2 5.5 V), low power ORDERING INFORMATION OTP/EPROM P87C552SBAA PART NUMBER DERIVATION DEVICE NUMBER (P87C552) FREQUENCY MAX (S) P87C552 OTP P87C552 OTP BLOCK DIAGRAM T0 T1 INT0 INT1 XTAL1 T0, T1 TWO 16-BIT ...
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... CMT1 P5.7/ADC7 RST EW 63 P5.6/ADC6 64 P5.5/ADC5 65 P5.4/ADC4 66 P5.3/ADC3 67 P5.2/ADC2 68 P5.1/ADC1 SU00208 4 Product data P87C552 LOW ORDER ADDRESS AND DATA BUS SS DD CT0I CT1I CT2I CT3I T2 RT2 SCL SDA HIGH ORDER ADDRESS AND DATA BUS RxD/DATA TxD/CLOCK INT0 INT1 ...
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... RD (P3.7): External data memory read strobe. Port 3 has four modes selected on a per bit basis by writing to the P3M1 and P3M2 registers as follows: P3M1.x P3M2.x Mode Description 0 0 Pseudo–bidirectional (standard c51 configuration; default Push–Pull 1 0 High impedance 1 1 Open drain 5 Product data P87C552 ...
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... CPU executes out of external program memory not allowed to float. This pin also receives the 12.75V programming supply voltage (V programming. Analog to Digital Conversion Reference Resistor: Low-end. Analog to Digital Conversion Reference Resistor: High-end. Analog Ground Analog Power Supply 6 Product data P87C552 ) during EPROM – 0.5V ...
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... A15 A14 A13 A12 A11 SDA SCL RT2 T2 CT3I AD7 AD6 AD5 AD4 AD3 7 Product data P87C552 RESET LSB VALUE 00H xxxxxxxxB AADR2 AADR1 AADR0 xx000000B LVADC – A0 xxxxx110B O – DPS 000000x0B 00H CTP1 CTN0 ...
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... TF1 TR1 TF0 TR0 IE1 T2IS1 T2IS0 T2ER T2B0 T2P1 T20V CMI2 CMI1 CMI0 CTI3 8 Product data P87C552 RESET LSB VALUE xx000000B xx000000B 00H 00H 00H 00H 00H 00H GFO PD IDL 00x00000B 00H 00H 00H 00H RP42 ...
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... RAM to retain their values. To properly terminate Power Down the reset or external interrupt should not be executed before V operating level and must be held active long enough for the oscillator to restart and stabilize (normally less than 10ms). 9 Product data P87C552 8XC552 RST R ...
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... OFF state after completing the external memory access POF WLE GF1 GF0 Figure 3. Power Control Register (PCON) 10 Product data P87C552 PWM0/ PORT 2 PORT 3 PORT 4 PWM1 Data Data Data High Address Data Data High Data ...
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... MEMORY SU00745A The data pointer can be accessed on a byte-by-byte basis by specifying the low or high byte in an instruction which accesses the SFRs. See application note AN458 for more details. 11 Product data P87C552 Reset Value = xxxx x110B – SU01115 Increments the data pointer by 1 ...
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... The value read from a reserved bit is indeterminate. 2003 Apr PWM, SRST GF2 WUPD Figure 6. AUXR1: DPTR Control Register 12 Product data P87C552 Reset Value = 0000 00x0B — DSP 1 0 SU01081 ...
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... SM2 REN TB8 RB8 Description Baud Rate** shift register f /12 OSC 8-bit UART variable 9-bit UART f / /32 OSC OSC 9-bit UART variable Figure 7. S0CON: Serial Port Control Register 13 Product data P87C552 Reset Value = 0000 0000B SU00981 ...
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... Both slaves can be selected at the same time by an address which has bit (for slave 0) and bit (for slave 1). Thus, both could be addressed with 1100 0000. 14 Product data P87C552 D7 D8 ONLY IN STOP MODE 2, 3 ...
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... The combination of Timer T2 and the capture and compare logic is very powerful in applications involving rotating machinery, automotive injection systems, etc. Timer T2 and the capture and compare logic are shown in Figure 12. 15 Product data P87C552 ;save accumulator ;save status ;of extended timer ;jump to INTEX if ;there is no overflow ;jump to INTEX if there is no overflow ...
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... Timer T2 halted (off clock source = f OSC 1 0 Test mode; do not use clock source = pin T2 Figure 11. T2 Control Register (TM2CON) 16 Product data P87C552 Reset Value = 00H 1 0 ECT1 ECT0 (LSB) SU01083 Reset Value = 00H 1 0 T2MS1 T2MS0 (LSB) /12 SU01084 ...
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... TM2IR is set at the end of the following cycle. When a match with CM0 occurs, the controller sets bits 0-5 of port 4 if the corresponding bits of the set enable register STE are at logic 1. 17 Product data P87C552 INT CT3I INT CTI2 CTI3 ...
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... If “1” then P4.2 is reset on a match between CM1 and Timer T2 If “1” then P4.1 is reset on a match between CM1 and Timer T2 If “1” then P4.0 is reset on a match between CM1 and Timer T2 Figure 14. Reset/Toggle Enable Register (RTE) 18 Product data P87C552 Reset Value = 00H 1 0 CTN1 CTP0 (LSB) ...
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... Timer T2 comparator 0 interrupt priority level Timer T2 capture register 3 interrupt priority level Timer T2 capture register 2 interrupt priority level Timer T2 capture register 1 interrupt priority level Timer T2 capture register 0 interrupt priority level Timer 2 Interrupt Priority Register (IP1) 19 Product data P87C552 1 0 Reset Value = C0H SP41 SP40 (LSB) SU01087 ...
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... PCON.1 will remain at logic 0. INTERNAL BUS OVERFLOW TIMER T3 (8-BIT) LOAD LOADEN INTERNAL RESET CLEAR WLE LOADEN PCON.4 INTERNAL BUS Figure 17. Watchdog Timer 20 Product data P87C552 RST R RST PD PCON.1 SU00955 ...
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... This option is selected by the AIDL bit of AUXR1 register (AUXR1.6). With the AIDL bit set, the ADC is active in the idle mode, and with the AIDL bit cleared, the ADC is powered off in idle mode. 21 Product data P87C552 , at the PWMn outputs is PWM f OSC 255 ...
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... ADCON.3 as above or by applying a rising edge to external pin STADC. When a conversion is started by applying a rising edge, a low level must be applied to STADC for at least one machine cycle followed by a high level for at least one machine cycle. 22 Product data P87C552 OUTPUT PWM0 BUFFER OUTPUT PWM1 ...
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... ADC start. The result of a completed conversion remains unaffected provided ADCI = logic 1; a new ADC conversion already in progress is aborted when the idle or power-down mode is entered. The result of a completed conversion (ADCI = logic 1) remains unaffected when entering the idle mode. 23 Product data P87C552 STOP 6 SU00958 ...
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... I/O, low voltage (2 5.5 V), low power 2003 Apr PWM, Start of Conversion SOC RESET SAR [BIT POINTER] = MSB [BIT CONVERSION TIME 1 0 TEST COMPLETE [BIT [BIT POINTER END TEST BIT POINTER END EOC END OF CONVERSION Figure 21. A/D Conversion Flowchart 24 Product data P87C552 SU00959 ...
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... Conversion completed; start of a new conversion requires ADCI=0 AADR1 AADR0 Selected Analog Channel 0 0 ADC0 (P5. ADC1 (P5. ADC2 (P5. ADC3 (P5. ADC4 (P5. ADC5 (P5. ADC6 (P5. ADC7 (P5.7) Figure 22. ADC Control Register (ADCON) 25 Product data P87C552 0 Reset Value = xx00 0000B AADR0 (LSB) SU00960 ...
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... LSB) ref– ref– is output for voltages (V – 3/2 LSB ref+ Figure 23. ADC Realization 26 Product data P87C552 (halted) (halted and reset) (reset; outputs are high) (may be enabled for operation in Idle mode by setting bit AIDC (AUXR1.6) ). START SUCCESSIVE APPROXIMATION CONTROL LOGIC ...
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... MULTIPLEXER C S Figure 24. A/D Input: Equivalent Circuit 101 100 011 010 001 000 QUANTIZATION ERROR q = LSB = q/2 – q/2 SYMMETRICAL QUANTIZATION ERROR Figure 25. Effective Conversion Characteristic 27 Product data P87C552 TO COMPARATOR charged SU00962 SU00963 ...
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... Enable SIO1 (I C) interrupt Enable SIO0 (UART) interrupt Enable Timer 1 interrupt Enable External interrupt 1 Enable Timer 0 interrupt Enable External interrupt 0 Figure 26. Interrupt Enable Register (IEN0) 28 Product data P87C552 INTERRUPT PRIORITY LEVEL INTERRUPT PRIORITY LEVEL IPx.x 0 Level 0 (lowest priority) 1 Level 1 0 Level 2 ...
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... C) interrupt priority level high SIO0 (UART) interrupt priority level high Timer 1 interrupt priority level high External interrupt 1 priority level high Timer 0 interrupt priority level high External interrupt 0 priority level high Figure 29. Interrupt Priority Register High (IP0H) 29 Product data P87C552 1 0 ECT1 ECT0 (LSB) SU00755 1 0 ...
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... External interrupt 1 Timer 1 overflow SIO0 (UART) 2 SIO1 ( capture 0 T2 capture 1 T2 capture 2 T2 capture 3 ADC completion T2 compare 0 T2 compare 1 T2 compare 2 (lowest) T2 overflow 30 Product data P87C552 1 0 PCT1 PCT0 (LSB) SU00764 1 0 PCT0H (LSB) SU00984 NAME VECTOR ADDRESS X0 0003H T0 000BH ...
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... If bus arbitration is lost in the master mode, SIO1 switches to the slave mode immediately and can detect its own slave address in the same serial transfer. 31 Product data P87C552 ...
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... S1DAT always contains the last byte present on the bus. Thus, in the event of lost arbitration, the transition from master transmitter to slave receiver is made with the correct data in S1DAT. 32 Product data P87C552 SDA SCL INTERFACE ...
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... S1DAT SHIFT REGISTER ARBITRATION & SYNC LOGIC TIMING & CONTROL LOGIC SERIAL CLOCK GENERATOR TIMER 1 OVERFLOW S1CON CONTROL REGISTER STATUS BITS STATUS DECODER S1STA STATUS REGISTER 2 C Bus Serial Interface Block Diagram 33 Product data P87C552 8 ACK OSC INTERRUPT 8 8 su00966 ...
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... The serial interrupt flag (SI) is set, and the stretching continues until the serial interrupt flag is cleared. (1) ( Figure 35. Arbitration Procedure (1) (3) (2) SPACE DURATION Figure 36. Serial Clock Synchronization 34 Product data P87C552 ( ACK SU00967 (1) SU00968 ...
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... ENS1 should not be used to temporarily release SIO1 from the I2C bus since, when ENS1 is reset, the I2C bus status is lost. The AA flag should be used instead (see description of the AA flag in the following text). 35 Product data P87C552 ...
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... In this case, no STOP condition is transmitted to the bus. However, the SIO1 hardware behaves STOP condition has been received and switches to the defined “not addressed” slave receiver mode. The STO flag is automatically cleared by hardware. 36 Product data P87C552 ACK SU00969 D0 A SHIFT IN (2) (2) A ...
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... C-bus specification and cannot be used Product data P87C552 2 C bus while the THE LOCK ATE ITS f DIVIDED BY OSC 256 224 192 160 960 120 60 96 (256 – ...
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... While AA is reset, SIO1 does not respond to its own slave address or a general call address. However, the I and address recognition may be resumed at any time by setting AA. This means that the AA bit may be used to temporarily isolate SIO1 2 from the I C bus. 38 Product data P87C552 ...
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... CONTINUES 38H OTHER MST A CONTINUES 68H 78H 80H 39 Product data P87C552 Ç Ç Ç Ç Ç Ç 28H Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç S SLA W Ç Ç Ç Ç Ç Ç Ç ...
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... TO CORRESPONDING 68H 78H 80H STATES IN SLAVE MODE 2 C BUS. SEE TABLE 7. 40 Product data P87C552 Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç 58H Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç ...
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... CALL Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç 70H A 78H 2 C BUS. SEE TABLE 8. 41 Product data P87C552 Ç Ç Ç Ç Ç Ç A DATA SLA Ç Ç Ç Ç Ç Ç 80H 80H A0H Ç ...
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... B0H LAST DATA BYTE TRANSMITTED. SWITCHED TO NOT ADDRESSED SLAVE (AA BIT IN S1CON = “0” BUS. SEE TABLE 9. 42 Product data P87C552 Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç ...
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... STO flag will be reset STOP condition followed by a START condition will be transmitted; STO flag will be reset bus will be released; not addressed slave will be entered START condition will be transmitted when the bus becomes free 43 Product data P87C552 ...
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... Data byte will be received; ACK bit will be returned Repeated START condition will be transmitted STOP condition will be transmitted; STO flag will be reset STOP condition followed by a START condition will be transmitted; STO flag will be reset 44 Product data P87C552 ...
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... SLA or General call address. A START condition will be transmitted when the bus becomes free Switched to not addressed SLV mode; Own SLA will be recognized; General call address will be recognized if S1ADR.0 = logic 1. A START condition will be transmitted when the bus becomes free. 45 Product data P87C552 ...
Page 46
... SLA or General call address. A START condition will be transmitted when the bus becomes free Switched to not addressed SLV mode; Own SLA will be recognized; General call address will be recognized if S1ADR.0 = logic 1. A START condition will be transmitted when the bus becomes free. 46 Product data P87C552 ...
Page 47
... STO flag while the STA flag is still set. No STOP condition is transmitted. The SIO1 hardware behaves STOP condition was received and is able to transmit a START condition. The STO flag is cleared by hardware (see Figure 44). 47 Product data P87C552 OSS OF ...
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... SDA and SCL lines, sets the interrupt flag, and loads the status register with 00H. This status code may be used to vector to a service routine which either attempts the aborted serial transfer again or simply recovers from the error condition as shown in Table 10. 48 Product data P87C552 SU00975 SU00976 ...
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... C bus for its own locations to obtain more bytes of code. Each state routine is part of the SIO1 interrupt routine and handles one of the 26 states. It ends with a RETI instruction which causes a return to the main program. 49 Product data P87C552 (3) SU00977 OUTINE Save PSW Push status code ...
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... NUMBER OF BYTES AS MASTER SLA+R TRANSMITTED TO SLA HIGHER ADDRESS BYTE INTERRUPT ROUTINE SLAVE TRANSMITTER DATA RAM SLAVE RECEIVER DATA RAM MASTER RECEIVER DATA RAM MASTER TRANSMITTER DATA RAM R1 R0 Figure 46. SIO1 Data Memory Map 50 Product data P87C552 CR0 ...
Page 51
... SIO1 behaves essentially as a passive device. In the master modes, an internal timer may be used to cause a time-out if a serial transfer is not complete after a defined period of time. This time period is 2 defined by the system connected to the I C bus. 2003 Apr PWM, ODES C bus and branches 51 Product data P87C552 ...
Page 52
... Number of bytes to transmit ! or receive as MST. –0x51 ! Contains SLA+R transmitted. –0x50 ! High Address byte for STATE 0 ! till STATE 25. 52 Product data P87C552 ! Generates STOP ! (CR0 = 100kHz) ! Releases BUS and ! ACK ! Releases BUS and ! NOT ACK ! Releases BUS and ! set STA ...
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... Bus error. st0 0x100 mov S1CON,#ENS1_NOTSTA_STO_NOTSI_AA_CR0 ! clr SI pop psw reti 53 Product data P87C552 ! RESET ! Load own SLA + enable ! general call recognition ! P1.6 High level. ! P1.7 High level. ! Enable SI01 interrupt ! SI01 interrupt low priority ! Initialize SLV funct. ! Transmit 4 bytes. ! SLA+W, Transmit funct. ...
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... BACKUP,NUMBYTMST pop psw reti : 18, Previous state was STATE 8 or STATE 10, SLA+W have been transmitted, ACK has been received. mts18 0x118 mov psw,#SELRB3 mov S1DAT,@r1 ajmp CON 54 Product data P87C552 ! Load SLA+R/W ! clr SI ! Load SLA+R/W ! clr SI ! Save initial value ...
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... Arbitration lost in SLA+W or DATA. A new START condition is transmitted when the IIC bus is free again. mts38 0x138 mov S1CON,#ENS1_STA_NOTSTO_NOTSI_AA_CR0 mov NUMBYTMST,BACKUP ajmp RETmt 55 Product data P87C552 ! set STO, clr SI ! JMP if NOT last DATA ! clr SI, set AA ! clr SI, set AA ! set STO, clr SI ...
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... RETmr mov S1CON,#ENS1_NOTSTA_NOTSTO_NOTSI_AA_CR0 inc r0 pop psw reti : 58, DATA have been received, NOT ACK returned. mrs58 0x158 mov psw,#SELRB3 mov @R0,S1DAT sjmp STOP 56 Product data P87C552 ! clr STA, STO, SI set AA ! set STO, clr SI ! Read received DATA ! clr SI,AA ! clr SI, set AA ...
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... Arbitration lost in SLA+R/W as MST. General call has been received, ACK returned. STA is set to restart MST mode after the bus is free again. srs78 0x178 mov S1CON,#ENS1_STA_NOTSTO_NOTSI_AA_CR0 mov psw,#SELRB3 ajmp INITSRD 57 Product data P87C552 ! clr SI, set AA ! clr SI, set AA ! Initialize SRD counter ! Initialize SRD counter ...
Page 58
... DATA has been received, NOT ACK has been returned. Recognition of own SLA. General call recognized, if S1ADR. 0–1. srs98 0x198 mov S1CON,#ENS1_NOTSTA_NOTSTO_NOTSI_AA_CR0 pop psw reti 58 Product data P87C552 ! Read received DATA ! clr SI,AA ! clr SI, set AA ! clr SI, set AA ! Read received DATA ! clr SI, set AA ...
Page 59
... B0, Arbitration lost in SLA and R/W as MST. Own SLA+R received, ACK returned. STA is set to restart MST mode after the bus is free again. stsb0 0x1b0 mov S1DAT,STD mov S1CON,#ENS1_STA_NOTSTO_NOTSI_AA_CR0 ajmp INITBASE2 59 Product data P87C552 ! clr SI, set AA ! load DATA in S1DAT ! clr SI, set AA ! load DATA in S1DAT ...
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... C0, DATA has been transmitted, NOT ACK received. stsc0 0x1c0 mov S1CON,#ENS1_NOTSTA_NOTSTO_NOTSI_AA_CR0 pop psw reti : C8, Last DATA has been transmitted (AA=0), ACK received. stsc8 0x1c8 mov S1CON,#ENS1_NOTSTA_NOTSTO_NOTSI_AA_CR0 pop psw reti 60 Product data P87C552 ! clr SI, set AA ! clr SI, set AA ! clr SI, set AA ...
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... Nonetheless suggested that conventional precautions be taken to avoid applying greater than the rated maxima. 3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V noted. DEVICE SPECIFICATIONS TYPE TYPE P87C552 SBxx versions P87C552 SFxx versions 2003 Apr PWM, SUPPLY VOLTAGE (V) ...
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... –3.2mA OH –I = 400 A OH –I = 120 A OH Test freq = 1MHz amb Port < AV < Product data P87C552 LIMITS UNIT UNIT MIN MAX max DD –0.5 0.2V –0 –0.5 0.2V –0 –0.5 ...
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... C specification input voltage below 1.5V will be recognized as a logic is approximately 2V ALE and PSEN to momentarily fall below the 0.9V OH – 0.2V < AV < 0.2V –20mV to 5.12V in steps of 0.5mV, derivating IN = 4.977V. ADC is monotonic with no missing codes. REF+ 63 Product data P87C552 LIMITS MIN MAX UNIT AV –0 –0 ...
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... Center of a step of the actual transfer curve. 2003 Apr PWM, (2) (1) (5) (4) (3) 1 LSB (ideal 1018 1019 1020 1 LSB = Figure 47. ADC Conversion Characteristic 64 Product data P87C552 Offset Gain error error 1021 1022 1023 1024 AV (LSB ) IN ideal – REF+ REF– ...
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... Product data P87C552 VARIABLE CLOCK MIN MAX UNIT 3.5 16 MHz 2t –40 ns CLCL t –40 ns CLCL t –30 ns CLCL 4t –100 ns CLCL t –30 ns CLCL 3t –45 ns ...
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... CLCL 14 t CLCL 14 t CLCL 1 s 0.3 s will be filtered out. Maximum capacitance on bus-lines SDA and CLCL < 285ns (16MHz > f CLCL 66 Product data P87C552 OUTPUT 1 > 4 > 4 > 4 – 3 < 0.3 s > – t CLCL RD 1 > > ...
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... RHDX DATA IN t AVDV P2.0–P2.7 OR A8–A15 FROM DPH Figure 49. External Data Memory Read Cycle 67 Product data P87C552 = Time for address valid to ALE low. = Time for ALE low to PSEN low. A0–A7 A8–A15 SU00006 A0–A7 FROM PCL INSTR IN A0–A15 FROM PCH ...
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... Figure 51. External Clock Drive XTAL1 XHQX XHDX VALID VALID VALID Figure 52. Shift Register Mode Timing 68 Product data P87C552 A0–A7 FROM PCL INSTR IN A8–A15 FROM PCH SU00213 SU00009 SET TI VALID VALID VALID VALID SET RI ...
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... Figure 53. AC Testing Input/Output Float 2.0V 2.0V 0.8V 0.8V Figure 54. AC Testing Input, Float Waveform repeated START condition STOP condition SU;DAT1 HD;DAT 2 Figure 55. Timing SIO1 (I C) Interface 69 Product data P87C552 SU00215 2.4V 0.45V SU00216 START condition t SU;STA 0 0 BUF t SU;STO 0 0 SU;DAT3 t SU ...
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... EA, RST, Port 0, and EW. : STADC and ref– through resistors of sufficiently high value such that the sink current into these pins DD 70 Product data P87C552 MAXIMUM ACTIVE MODE TYPICAL ACTIVE MODE MAXIMUM IDLE MODE TYPICAL IDLE MODE 16 SU01116 ) OSC SU00218 ...
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... Figure 60. I Test Condition, Power Down Mode 5. Port 0 and EW. : RST, STADC, XTAL1 and EA. ss ref– through resistors of sufficiently high value such that the sink current into these pins DD 71 Product data P87C552 DD DD SU00219 SU00220 SU00221 3 ...
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... EA is latched on Reset and all further programming of the EPROM is disabled. When security bits 1 and 2 are programmed, in addition to the above, verify mode is disabled. When all three security bits are programmed, all of the conditions above apply and all external program memory execution is disabled. 72 Product data P87C552 ...
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... I/O, low voltage (2 5.5 V), low power REVISION HISTORY Rev Date Description _3 20030325 Product data (9397 750 11302); ECN 853-2410 29338 dated 2003 Jan 07 Modifications: Corrected EPROM Characteristics _2 19990330 Preliminary data (9397 750 05504) 2003 Apr PWM, 73 Product data P87C552 ...
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... Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Fax: + 24825 Document order number: 74 Product data P87C552 2 C patent Koninklijke Philips Electronics N.V. 2003 All rights reserved. Printed in U.S.A. Date of release: 04-03 ...