P87LPC760 NXP Semiconductors, P87LPC760 Datasheet

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P87LPC760

Manufacturer Part Number
P87LPC760
Description
The P87LPC760 is a 14-pin single-chip microcontroller designed forlow pin count applications demanding high-integration, low costsolutions over a wide range of performance requirements
Manufacturer
NXP Semiconductors
Datasheet

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Semiconductors
Preliminary data
IC28 Data Handbook
hilips
P87LPC760
Low power, low price, low pin count
(14 pin) microcontroller with 1 kbyte OTP
INTEGRATED CIRCUITS
2002 Mar 07

Related parts for P87LPC760

P87LPC760 Summary of contents

Page 1

... P87LPC760 Low power, low price, low pin count (14 pin) microcontroller with 1 kbyte OTP Preliminary data IC28 Data Handbook hilips Semiconductors INTEGRATED CIRCUITS 2002 Mar 07 ...

Page 2

... Preliminary data P87LPC760 ...

Page 3

... Preliminary data P87LPC760 ...

Page 4

... The P87LPC760 is a 14-pin single-chip microcontroller designed for low pin count applications demanding high-integration, low cost solutions over a wide range of performance requirements. A member of the Philips low pin count family, the P87LPC760 offers programmable oscillator configurations for high and low speed crystals or RC operation, wide operating voltage range, programmable port output configurations, selectable Schmitt trigger inputs, LED drive outputs, and a built-in watchdog timer ...

Page 5

... PIN CONFIGURATION, 14-PIN TSSOP AND 14-PIN DIP PACKAGES LOGIC SYMBOL CIN1B CIN1A CMPREF CMP1 CLKOUT/X2 X1 2002 Mar P0.3/CIN1B P1 P0.4/CIN1A RST/P1 P0.5/CMPREF X1/P2 P0.6/CMP1 X2/CLKOUT/P2 P1.0/TxD SDA/INT0/P1 P1.1/RxD SCL/T0/P1.2 SU01527 Preliminary data P87LPC760 TxD RxD T0/SCL INT0/SDA RST SU01528 ...

Page 6

... PORT 2 CONFIGURABLE I/OS PORT 1 CONFIGURABLE I/OS PORT 0 CONFIGURABLE I/OS KEYPAD INTERRUPT CONFIGURABLE CRYSTAL OR OSCILLATOR RESONATOR 2002 Mar 07 ACCELERATED 80C51 CPU INTERNAL BUS TIMER 0, 1 WATCHDOG TIMER AND OSCILLATOR ANALOG COMPARATOR POWER MONITOR (POWER-ON RESET, BROWNOUT RESET) ON-CHIP RC OSCILLATOR 3 Preliminary data P87LPC760 UART SU01529 ...

Page 7

... INTERRUPT VECTORS 0000h ON-CHIP CODE MEMORY SPACE 1. The P87LPC760 does not support access to external data memory. However, the User Configuration Bytes are accessed via the MOVX instruction as if they were in external data memory. Figure 1. P87LPC760 Program and Data Memory Map 2002 Mar 07 ...

Page 8

... Input to the oscillator circuit and internal clock generator circuits (when selected via the EPROM configuration). Ground reference. Power Supply: This is the power supply voltage for normal operation as well as Idle and Power Down modes. 5 Preliminary data P87LPC760 2 C specifications specifications. ...

Page 9

... A4h P2S P1S P0S ENCLK 6 Preliminary data P87LPC760 Reset Value LSB 00h 1 SRST 0 – DPS 02h 00h 1 CN1 OE1 CO1 ...

Page 10

... TF1 TR1 TF0 TR0 8Ch 8Dh 8Ah 8Bh 89h – – A7h – – WDOVF WDRUN A6h 7 Preliminary data P87LPC760 Reset Value LSB 1 – – (P2M2.1) (P2M2.0) 00h GF1 GF0 PD IDL Note RS0 00h 00h ...

Page 11

... Details of P87LPC760 functions will be described in the following sections. Enhanced CPU The P87LPC760 uses an enhanced 80C51 CPU which runs at twice the speed of standard 80C51 devices. This means that the performance of the P87LPC760 running at 5 MHz is exactly the same as that of a standard 80C51 running at 10 MHz. A machine cycle consists of 6 oscillator cycles, and most instructions execute clocks ...

Page 12

... CMPREF CIN1A CO1 V (1.23V) ref CIN1B CO1 CMPREF CIN1B CO1 V (1.23V) ref Figure 4. Comparator Configurations 9 Preliminary data P87LPC760 CMP1 (P0.6) CMF1 INTERRUPT SU01532 CP1, CN1, OE1 = CO1 CMP1 – CP1, CN1, OE1 = CO1 CMP1 – CP1, CN1, OE1 = CO1 CMP1 – ...

Page 13

... Negative input from CMPREF pin. ; – Output to CMP1 pin enabled. ; The comparator has to start up for at ; least 10 microseconds before use. ; Clear comparator 1 interrupt flag. ; Enable the comparator 1 interrupt. The ; priority is left at the current value. ; Enable the interrupt system (if needed). ; Return to caller. 10 Preliminary data P87LPC760 SU01189 ...

Page 14

... The first five of these times are 4.7 ms (see I are covered by the low order three bits of timer I. Timer I is clocked by the P87LPC760 CPU clock. Timer I can be pre-loaded with one of four values to optimize timing for different oscillator frequencies. At lower frequencies, software response time is increased and will degrade maximum performance of the I register I2CFG description for prescale values (CT0, CT1) ...

Page 15

... Figure Data Register (I2DAT) 12 Preliminary data P87LPC760 Reset Value: 81h 1 0 MASTER — XSTR XSTP 2 C hardware to ignore the bus until it SU01155 Reset Value: xxh 1 0 — — — ...

Page 16

... XDAT = 0; it sets Transmit Active and drives SDA low during the SCL low time. After SCL goes high, the I hardware waits for the suitable minimum time and then releases SDA to high to make the stop condition. 13 Preliminary data P87LPC760 2 C interface will only drive 2 C hardware to 2 ...

Page 17

... SCL when this device is a master on the I controls both of these parameters, and also the timing for stop and start conditions. Regarding Software Response Time Because the P87LPC760 can run at 20 MHz, and because the I interface is optimized for high-speed operation quite likely that 2 ...

Page 18

... Interrupts The P87LPC760 uses a four priority level interrupt structure. This allows great flexibility in controlling the handling of the P87LPC760’s many interrupt sources. The P87LPC760 supports interrupt sources. Each interrupt source can be individually enabled or disabled by setting or clearing a bit in registers IEN0 or IEN1. The IEN0 register also contains a global disable bit, EA, which disables all interrupts at once ...

Page 19

... IE0 when the interrupt is level sensitive, it simply tracks the input pin level. If the external interrupt is enabled when the P87LPC760 is put into Power Down or Idle mode, the interrupt will cause the processor to wake up and resume operation. Refer to the section on Power Reduction Modes for details ...

Page 20

... Low power, low price, low pin count (14 pin) microcontroller with 1 kbyte OTP I/O Ports The P87LPC760 has 3 I/O ports, port 0, port 1, and port 2. The exact number of I/O pins available depend upon the oscillator and reset options chosen. At least 9 pins of the P87LPC760 may be used as I/Os when a two-pin external oscillator and an external reset circuit are used ...

Page 21

... The last two functions are described in the Timer/Counters and Oscillator sections respectively. The enable bits for all of these functions are shown in Figure 13. Each I/O port of the P87LPC760 may be selected to use TTL level inputs or Schmitt inputs with hysteresis. A single configuration bit determines this selection for the entire port. Port pins P1.2, P1.3, and P1 ...

Page 22

... The P87LPC760 allows any pin of port enabled to cause this interrupt. Port pins are enabled by the setting of bits in the KBI register, as shown in Figure 15. The Keyboard Interrupt Flag (KBF) in the AUXR1 register is set when any enabled pin is pulled low while the KBI interrupt function is active ...

Page 23

... Note: the Keyboard Interrupt must be enabled in order for the settings of the KBI register to be effective. The interrupt flag (KBF) is located at bit 7 of AUXR1. 2002 Mar 07 EKB (FROM IEN1 REGISTER) Figure 14. Keyboard Interrupt KBI.5 KBI.4 KBI.3 – Figure 15. Keyboard Interrupt Register (KBI) 20 Preliminary data P87LPC760 KBF (KBI INTERRUPT) SU01536 Reset Value: 00h 1 0 – – SU01537 ...

Page 24

... X2/P2.0 pin may be enabled when the external clock input is used. Clock Output The P87LPC760 supports a clock output function when either the on-chip RC oscillator or external clock input options are selected. This allows external devices to synchronize to the P87LPC760. When enabled, via the ENCLK bit in the P2M1 register, the clock output appears on the X2/CLKOUT pin whenever the on-chip oscillator is running, including in Idle mode ...

Page 25

... A CLOCK OUTPUT MAY BE OBTAINED ON THE X2 PIN BY SETTING THE ENCLK BIT IN THE P2M1 REGISTER. 2002 Mar 07 QUARTZ CRYSTAL OR CERAMIC RESONATOR Figure 16. Using the Crystal Oscillator CMOS COMPATIBLE EXTERNAL OSCILLATOR SIGNAL Figure 17. Using an External Clock Input 22 Preliminary data P87LPC760 87LPC760 SU01538 87LPC760 X1 X2 SU01539 ...

Page 26

... The default operation is for a brownout detection to cause a processor reset, however it may alternatively be configured to generate an interrupt by setting the BOI bit in the AUXR1 register (AUXR1.5). The P87LPC760 allows selection of two Brownout levels: 2 3.8 V. When V DD detector triggers and remains active until V above the Brownout Detect voltage ...

Page 27

... When this feature is activated, the POF flag in the PCON register is set to indicate an initial power up condition. The POF flag will remain set until cleared by software. Power Reduction Modes The P87LPC760 supports Idle and Power Down modes of power reduction. Idle Mode The Idle mode leaves peripherals running in order to allow them to activate the processor when an interrupt is generated ...

Page 28

... Brownout Detect Interrupt The BOD bit in AUXR1 must not be set (brownout detect not disabled). The BOI bit in AUXR1 must be set (brownout interrupt enabled). The corresponding interrupt must be enabled. Reset Input The external reset input must be enabled. 2002 Mar 07 25 Preliminary data P87LPC760 ...

Page 29

... While the signal on the RST pin is less than low, the P87LPC760 is held in reset until the signal goes high. The watchdog timer on the P87LPC760 can act as an oscillator fail detect because it uses an independent, fully on-chip oscillator. UCFG1 is described in the System Configuration Bytes section of this datasheet. ...

Page 30

... Low power, low price, low pin count (14 pin) microcontroller with 1 kbyte OTP Timer/Counters The P87LPC760 has two general purpose counter/timers which are upward compatible with the standard 80C51 Timer 0 and Timer 1. Both can be configured to operate as timers or can be configured event counter (see Figure 22). An option to automatically toggle the T0 pin upon timer overflow has been added. In the “ ...

Page 31

... Setting the run flag (TRn) does not clear the registers. Mode 0 operation is slightly different for Timer 0 and Timer 1. See Figures 24 and 25 TF0 TR0 – – IE0 TL0 TH0 (5 BITS) (8 BITS) CONTROL TOGGLE 28 Preliminary data P87LPC760 Reset Value: 00h 0 IT0 SU01543 OVERFLOW TF0 INTERRUPT T0 PIN T0OE SU01544 ...

Page 32

... Thus, TH0 now controls the “Timer 1” interrupt. Mode 3 is provided for applications that require an extra 8-bit timer. With Timer 0 in Mode 3, an P87LPC760 can look like it has three Timer/Counters. When Timer Mode 3, Timer 1 can be turned on and off by switching it into and out of its own Mode 3. It can still be used by the serial port as a baud rate generator any application not requiring an interrupt ...

Page 33

... BITS) TL1 (8 BITS) CONTROL RELOAD TR1 TH1 (8 BITS) Figure 29. Timer 1 in Mode 2 (8-Bit Auto-Reload) TL0 (8 BITS) CONTROL TH0 (8 BITS) CONTROL TR1 30 Preliminary data P87LPC760 OVERFLOW TF0 INTERRUPT TOGGLE T0 PIN T0OE SU01547 OVERFLOW TF1 INTERRUPT SU01548 OVERFLOW TF0 INTERRUPT TOGGLE T0 PIN T0OE ...

Page 34

... The port outputs will be a logic 1 prior to the first timer overflow when this mode is turned on. UART The P87LPC760 includes an enhanced 80C51 UART. The baud rate source for the UART is timer 1 for modes 1 and 3, while the rate is fixed in modes 0 and 2. Because CPU clocking is different on the P87LPC760 than on the standard 80C51, baud rate calculation is somewhat different ...

Page 35

... TMOD = 0010b). In that case the baud rate is given by the formula: Mode 1, 3 Baud Rate + Tables 6 and 7 list various commonly used baud rates and how they can be obtained using Timer 1 as the baud rate generator. 32 Preliminary data P87LPC760 Reset Value: 00h SU01550 ...

Page 36

... Preliminary data P87LPC760 38.4k 57.6k * 7.3728 * 11.0592 * 14.7456 – – – – – – – – – – – – – – – – ...

Page 37

... Ten bits are transmitted (through TxD), or received (through RxD): a start bit (0), 8 data bits (LSB first), and a stop bit (1). On receive, the stop bit goes into RB8 in SCON. In the P87LPC760 the baud rate is determined by the Timer 1 overflow rate. Figure 33 shows a simplified functional diagram of the serial port in Mode 1, and associated timings for transmit receive ...

Page 38

... INTERNAL BUS S1 ... S6 S1 ... S6 S1 ... S6 S1 ... S6 S1 ... S6 S1 ... Figure 32. Serial Port Mode 0 35 Preliminary data P87LPC760 RxD P1.1 ALT OUTPUT FUNCTION TxD P1.0 ALT OUTPUT FUNCTION SHIFT CLOCK RXD P1.1 ALT INPUT FUNCTION S1 ... S6 S1 ... S6 S1 ... S6 TRANSMIT D7 RECEIVE D6 ...

Page 39

... INPUT SHIFT REGISTER DETECTOR LOAD SBUF SBUF READ SBUF 80C51 INTERNAL BUS Figure 33. Serial Port Mode 1 36 Preliminary data P87LPC760 TxD P1.0 ALT OUTPUT FUNCTION SERIAL PORT INTERRUPT TRANSMIT D6 D7 STOP BIT D6 D7 STOP BIT RECEIVE SU01179 ...

Page 40

... SM2 has no effect in Mode 0, and in Mode 1 can be used to check the validity of the stop bit, although this is better done with the Framing Error flag Mode 1 reception, if SM2 = 1, the receive interrupt will not be activated unless a valid stop bit is received. 37 Preliminary data P87LPC760 ...

Page 41

... INPUT SHIFT REGISTER LOAD SBUF SBUF READ SBUF 80C51 INTERNAL BUS Figure 34. Serial Port Mode 2 38 Preliminary data P87LPC760 TxD P1.0 ALT OUTPUT FUNCTION SERIAL PORT INTERRUPT TRANSMIT D6 D7 TB8 STOP BIT D6 D7 RB8 STOP BIT RECEIVE SU01180 ...

Page 42

... INPUT SHIFT REGISTER DETECTOR LOAD SBUF SBUF READ SBUF 80C51 INTERNAL BUS Figure 35. Serial Port Mode 3 39 Preliminary data P87LPC760 TxD P1.0 ALT OUTPUT FUNCTION SERIAL PORT INTERRUPT TRANSMIT D6 D7 TB8 STOP BIT D6 D7 RB8 STOP BIT RECEIVE SU01181 ...

Page 43

... After a chip reset, the user program has a limited time in which to either feed the watchdog timer or change the timeout period. When a low CPU clock frequency is used in the application, the number of 40 Preliminary data P87LPC760 ...

Page 44

... Minimum Time Nominal Time 131 ms 165 ms 262 ms 330 ms 524 ms 660 ms 1.05 sec 1.3 sec 2.1 sec 41 Preliminary data P87LPC760 WATCHDOG RESET WATCHDOG INTERRUPT WDTE (UCFG1.7) S WDOVF Q (WDCON.5) R SU01633 1 0 WDS0 Maximum Time 180 ms 360 ms 719 ms 1 ...

Page 45

... DPTR) will be affected by the setting of DPS. The MOVX instructions have limited application for the P87LPC760 since the part does not have an external data bus. However, they may be used to access EPROM configuration information (see EPROM Characteristics section). ...

Page 46

... UCFG bytes are programmed. System Configuration Bytes A number of user configurable features of the P87LPC760 must be defined at power up and therefore cannot be set by the program after start of execution. Those features are configured through the use of two EPROM bytes that are programmed in the same manner as the EPROM program space ...

Page 47

... Mar — — — — — further programming of the EPROM is disabled. At that point, only security bit 2 may still be programmed. When both security bits are programmed, EPROM verify is also disabled. Protection Description 44 Preliminary data P87LPC760 Unprogrammed Value: FFh 0 — SU01186 ...

Page 48

... Nonetheless suggested that conventional precautions be taken to avoid applying greater than the rated maximum. 3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. 2002 Mar 07 RATING –55 to +125 –65 to +150 0 to +11.0 –0 1.5 45 Preliminary data P87LPC760 UNIT +0. ...

Page 49

... MHz or less, are guaranteed to continue to execute instructions OSC = 2 not guaranteed MHz or less are guaranteed to continue to execute instructions correctly OSC = 4.0 V and f > 10 MHz is not guaranteed. DD OSC 46 Preliminary data P87LPC760 LIMITS UNIT UNIT 1,2 MIN TYP MAX – – 4 ...

Page 50

... MHz OSC MHz OSC MHz OSC MHz RCOSC 3,4 tol MHz RCOSC 3 tol MHz RCOSC 47 Preliminary data P87LPC760 LIMITS UNIT UNIT MIN TYP MAX – – – V –0 – – –50 dB – 250 500 ns – ...

Page 51

... DD – 0 CHCL CLCX t C Figure 42. External Clock Timing 1000 6.0 V 5.0 V 100 4.0 V 3 100 100 SU01202 Figure 44. Typical Idd versus frequency (medium frequency 48 Preliminary data P87LPC760 SET TI VALID VALID VALID SET RI SU01187 t CHCX t CLCH SU01188 6.0 V 6.0 V 5.0 V 5.0 V 4.0 V 3.3 V 2.7 V 2.7 V 1,000 ...

Page 52

... Figure 48. Typical Idle Idd versus frequency (external clock, 10,000 5.0 V 4.0 V 3.3 V 1,000 2.7 V 100 10 10,000 100,000 10 SU01205 Figure 49. Typical Idle Idd versus frequency (external clock, 4.0 V 3.3 V 2.7 V 10,000 SU01206 49 Preliminary data P87LPC760 4.0 V 3.3 V 2.7 V 100 1,000 10,000 Frequency (kHz) SU01207 25 C, LPEP=1) 5.0 V 4.0 V 6.0 V 3.3 V 2.7 V 100 1,000 10,000 100,000 Frequency (kHz) SU01208 ...

Page 53

... Philips Semiconductors Low power, low price, low pin count (14 pin) microcontroller with 1 kbyte OTP TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm 2002 Mar 07 50 Preliminary data P87LPC760 SOT402-1 ...

Page 54

... Philips Semiconductors Low power, low price, low pin count (14 pin) microcontroller with 1 kbyte OTP DIP14: plastic dual in-line package; 14 leads (300 mil) 2002 Mar 07 51 Preliminary data P87LPC760 SOT27-1 ...

Page 55

... Philips Semiconductors Low power, low price, low pin count (14 pin) microcontroller with 1 kbyte OTP REVISION HISTORY Date CPCN 2002 Mar 07 9397 750 09532 2002 Mar 07 Description Initial release 52 Preliminary data P87LPC760 ...

Page 56

... Mar components conveys a license under the Philips’ system provided the system conforms to the Fax: + 24825 Document order number: 53 Preliminary data P87LPC760 2 C patent Koninklijke Philips Electronics N.V. 2002 All rights reserved. Printed in U.S.A. Date of release: 03-02 9397 750 09532 ...

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