P89LPC9321 NXP Semiconductors, P89LPC9321 Datasheet
P89LPC9321
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P89LPC9321 Summary of contents
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... The P89LPC9321 is a single-chip microcontroller, available in low cost packages, based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80C51 devices. Many system-level functions have been incorporated into the P89LPC9321 in order to reduce component count, board space, and system cost. 2. Features and benefits 2 ...
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... Controlled slew rate port outputs to reduce EMI. Outputs have approximately 10 ns minimum ramp times. Only power and ground connections are required to operate the P89LPC9321 when internal reset option is selected. Four interrupt priority levels. ...
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... Ordering information Table 1. Type number P89LPC9321FA P89LPC9321FDH P89LPC9321FN 3.1 Ordering options Table 2. Type number P89LPC9321FA P89LPC9321FDH P89LPC9321FN P89LPC9321 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core Ordering information Package Name Description PLCC28 plastic leaded chip carrier; 28 leads TSSOP28 plastic thin shrink small outline package; 28 leads ...
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... WATCHDOG TIMER AND OSCILLATOR PROGRAMMABLE CPU OSCILLATOR DIVIDER clock ON-CHIP RC CONFIGURABLE OSCILLATOR OSCILLATOR WITH CLOCK DOUBLER All information provided in this document is subject to legal disclaimers. Rev. 2 — 16 November 2010 P89LPC9321 TXD UART RXD SCL 2 I C-BUS SDA SPICLK MOSI SPI MISO SS REAL-TIME CLOCK/ ...
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... DD CMP2 CIN2B CIN2A CIN1B PORT 0 CIN1A CMPREF CMP1 T1 P89LPC9321 XTAL2 PORT 3 XTAL1 002aae103 All information provided in this document is subject to legal disclaimers. Rev. 2 — 16 November 2010 P89LPC9321 SS TXD RXD SCL T0 SDA INT0 PORT 1 INT1 RST OCB OCC ICB OCD MOSI MISO PORT 2 ...
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... P2.2/MOSI 14 P2.3/MISO P89LPC9321 TSSOP28 pin configuration P1.6/OCB 5 6 P1.5/RST P3.1/XTAL1 8 P89LPC9321FA P3.0/XTAL2/CLKOUT 9 P1.4/INT1 10 11 P1.3/INT0/SDA P89LPC9321 PLCC28 pin configuration All information provided in this document is subject to legal disclaimers. Rev. 2 — 16 November 2010 P89LPC9321 28 P2.7/ICA 27 P2.6/OCA 26 P0.1/CIN2B/KBI1 25 P0.2/CIN2A/KBI2 24 P0.3/CIN1B/KBI3 23 P0.4/CIN1A/KBI4 22 P0.5/CMPREF/KBI5 ...
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... P1.7/OCC 4 P1.6/OCB 5 P1.5/RST P89LPC9321FN 8 P3.1/XTAL1 9 P3.0/XTAL2/CLKOUT P1.4/INT1 10 P1.3/INT0/SDA 11 12 P1.2/T0/SCL 13 P2.2/MOSI 14 P2.3/MISO P89LPC9321 DIP28 pin configuration All information provided in this document is subject to legal disclaimers. Rev. 2 — 16 November 2010 P89LPC9321 28 P2.7/ICA 27 P2.6/OCA 26 P0.1/CIN2B/KBI1 25 P0.2/CIN2A/KBI2 24 P0.3/CIN1B/KBI3 23 P0.4/CIN1A/KBI4 22 P0.5/CMPREF/KBI5 P0.6/CMP1/KBI6 19 P0 ...
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... P0.5 — Port 0 bit 5. High current source. I CMPREF — Comparator reference (negative) input. I KBI5 — Keyboard input 5. All information provided in this document is subject to legal disclaimers. Rev. 2 — 16 November 2010 P89LPC9321 and Table 10 “Static characteristics” Section for details. © NXP B.V. 2010. All rights reserved ...
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... All pins have Schmitt trigger inputs. Port 2 also provides various special functions as described below: All information provided in this document is subject to legal disclaimers. Rev. 2 — 16 November 2010 P89LPC9321 and Table 10 “Static characteristics” and Table 10 “Static characteristics” for Section for details ...
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... I Power supply: This is the power supply voltage for normal operation as well as Idle and Power-down modes. All information provided in this document is subject to legal disclaimers. Rev. 2 — 16 November 2010 P89LPC9321 and Table 10 “Static characteristics” Section for details. © NXP B.V. 2010. All rights reserved. ...
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... NXP Semiconductors 7. Functional description Remark: Please refer to the P89LPC9321 User manual for a more detailed functional description. 7.1 Special function registers Remark: SFR accesses are restricted in the following ways: • User must not attempt to access any SFR locations not defined. • Accesses to any defined SFR locations must be strictly for the functions for the SFRs. ...
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Table 4. Special function registers * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB Bit address E7 ACC* Accumulator E0H AUXR1 Auxiliary A2H CLKLP function register Bit address register F0H ...
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Table 4. Special function registers …continued * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB DEEDAT Data EEPROM F2H data register DEEADR Data EEPROM F3H address register DIVM CPU clock 95H divide-by-M control ...
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Table 4. Special function registers …continued * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB I2SCLH Serial clock DDH generator/SCL duty cycle register high I2SCLL Serial clock DCH generator/SCL duty cycle register low ...
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Table 4. Special function registers …continued * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB KBCON Keypad control 94H - register KBMASK Keypad 86H interrupt mask register KBPATN Keypad pattern 93H register OCRAH ...
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Table 4. Special function registers …continued * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB P1* Port 1 90H OCC Bit address A7 P2* Port 2 A0H ICA Bit address B7 P3* Port ...
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Table 4. Special function registers …continued * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB RTCH RTC register D2H high RTCL RTC register D3H low SADDR Serial port A9H address register SADEN Serial ...
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Table 4. Special function registers …continued * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB TH0 Timer 0 high 8CH TH1 Timer 1 high 8DH TH2 CCU timer high CDH TICR2 CCU interrupt ...
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... BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable. [3] The RSTSRC register reflects the cause of the P89LPC9321 reset except BOIF bit. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset value is x011 0000. ...
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Table 5. Extended special function registers Name Description SFR Bit functions and addresses addr. BODCFG BOD FFC8H configuration register CLKCON CLOCK Control FFDEH CLKOK register PGACON1 PGA1 control FFE1H ENPGA1 register PGACON1B PGA1 control FFE4H register B PGA1TRIM8X16X PGA1 trim ...
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... NXP Semiconductors 7.2 Enhanced CPU The P89LPC9321 uses an enhanced 80C51 CPU which runs at six times the speed of standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and most instructions execute in one or two machine cycles. 7.3 Clocks 7.3.1 Clock definitions The P89LPC9321 device has several internal clocks as defined below: OSCCLK — ...
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... Idle mode, it may be turned off prior to entering Idle, saving additional power. 7.6 On-chip RC oscillator option The P89LPC9321 has a 6-bit TRIM register that can be used to tune the frequency of the RC oscillator. During reset, the TRIM value is initialized to a factory preprogrammed value to adjust the oscillator frequency to 7.373 MHz ± room temperature. End-user applications can write to the TRIM register to adjust the on-chip RC oscillator to other frequencies ...
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... Low power select The P89LPC9321 is designed to run at 18 MHz (CCLK) maximum. However, if CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to logic 1 to lower the power consumption further. On any reset, CLKLP is logic 0 allowing highest performance access ...
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... CODE Code memory space, accessed as part of program execution and via the MOVC instruction. The P89LPC9321 has on-chip Code memory. The P89LPC9321 also has 512 bytes of on-chip data EEPROM that is accessed via SFRs (see Section 7.14 Data RAM arrangement The 768 bytes of on-chip RAM are organized as shown in Table 6 ...
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... LOW in the next cycle, the interrupt request flag IEn in TCON is set, causing an interrupt request external interrupt is enabled when the P89LPC9321 is put into Power-down or Idle mode, the interrupt will cause the processor to wake-up and resume operation. Refer to Section 7.18 “Power reduction modes” ...
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... EC EA (IE0.7) TF0 ET0 TF1 ET1 TI and RI/RI ES/ESR TI EST SI EI2C SPIF ESPI ECCU EEIF EIEE All information provided in this document is subject to legal disclaimers. Rev. 2 — 16 November 2010 P89LPC9321 wake-up (if in power-down) interrupt to CPU 002aae160 © NXP B.V. 2010. All rights reserved ...
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... NXP Semiconductors 7.16 I/O ports The P89LPC9321 has four I/O ports: Port 0, Port 1, Port 2 and Port 3. Ports 0, 1, and 2 are 8-bit ports, and Port 2-bit port. The exact number of I/O pins available depends upon the clock and reset options chosen, as shown in Table 7. Clock source ...
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... Pin P1.5 is input only. Pins P1.2 and P1.3 are configurable for either input-only or open-drain. Every output on the P89LPC9321 has been designed to sink typical LED drive current. However, there is a maximum total output current for all ports which must not be exceeded. Please refer to All ports pins that can function as an output have slew rate controlled outputs to limit noise generated by quickly switching output signals ...
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... BOD reset voltage should be lower than BOD interrupt trip point. BOD EEPROM/FLASH is used for flash/Data EEPROM programming/erase protection and has only 1 trip voltage of 2.4 V. Please refer to P89LPC9321 User manual for detail configurations. If brownout detection is enabled the brownout condition occurs when V ...
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... Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core must fall below V DD Table 10 “Static All information provided in this document is subject to legal disclaimers. Rev. 2 — 16 November 2010 P89LPC9321 before power is reapplied, in order POR characteristics”). © NXP B.V. 2010. All rights reserved ...
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... NXP Semiconductors 7.19.1 Reset vector Following reset, the P89LPC9321 will fetch instructions from either address 0000H or the Boot address. The Boot address is formed by using the boot vector as the high byte of the address and the low byte of the address = 00H. The boot address will be used if a UART break reset occurs, or the non-volatile boot status bit (BOOTSTAT ...
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... RTC/system timer The P89LPC9321 has a simple RTC that allows a user to continue running an accurate timer while the rest of the device is powered down. The RTC can be a wake- interrupt source. The RTC is a 23-bit down counter comprised of a 7-bit prescaler and a 16-bit loadable down counter ...
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... Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core TOR2 compare value timer value 0x0000 non-inverted inverted Asymmetrical PWM, down-counting All information provided in this document is subject to legal disclaimers. Rev. 2 — 16 November 2010 P89LPC9321 002aaa893 © NXP B.V. 2010. All rights reserved ...
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... Equation 1: PCLK = ----------------- - ( ) All information provided in this document is subject to legal disclaimers. Rev. 2 — 16 November 2010 P89LPC9321 002aaa894 TOR2 COMPARE VALUE A (or C) COMPARE VALUE B (or D) TIMER VALUE 0 PWM OUTPUT (OCA or OCC) PWM OUTPUT (OCB or OCD) 002aaa895 © NXP B.V. 2010. All rights reserved. (1) ...
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... TOCF2D (TIFR2.6) Fig 11. Capture/compare unit interrupts 7.23 UART The P89LPC9321 has an enhanced UART that is compatible with the conventional 80C51 UART except that Timer 2 overflow cannot be used as a baud rate source. The P89LPC9321 does include an independent baud rate generator. The baud rate can be selected from the oscillator (divided by a constant), Timer 1 overflow, or the independent baud rate generator ...
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... Section 7.23.5 “Baud rate generator and 7.23.5 Baud rate generator and selection The P89LPC9321 enhanced UART has an independent baud rate generator. The baud rate is determined by a baud-rate preprogrammed into the BRGR1 and BRGR0 SFRs which together form a 16-bit baud rate divisor value that works in a similar manner as Timer 1 but is much more accurate ...
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... C-bus may be used for test and diagnostic purposes. 2 C-bus configuration is shown in 2 C-bus interface that supports data transfers up to 400 kHz. All information provided in this document is subject to legal disclaimers. Rev. 2 — 16 November 2010 P89LPC9321 Figure 13. The P89LPC9321 device provides a © NXP B.V. 2010. All rights reserved ...
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... Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core 2 I C-bus P1.3/SDA P1.2/SCL P89LPC9321 2 C-bus configuration All information provided in this document is subject to legal disclaimers. Rev. 2 — 16 November 2010 P89LPC9321 OTHER DEVICE OTHER DEVICE 2 2 WITH I C-BUS WITH I C-BUS INTERFACE ...
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... P1.2 I2CON I2SCLH I2SCLL status bus I2STAT 2 C-bus serial interface block diagram All information provided in this document is subject to legal disclaimers. Rev. 2 — 16 November 2010 P89LPC9321 8 I2ADR ADDRESS REGISTER COMPARATOR SHIFT REGISTER ACK I2DAT 8 BIT COUNTER / ARBITRATION TIMING AND SYNC LOGIC ...
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... NXP Semiconductors 7.25 SPI The P89LPC9321 provides another high-speed serial communication interface: the SPI interface. SPI is a full-duplex, high-speed, synchronous communication bus with two operation modes: Master mode and Slave mode Mbit/s can be supported in either Master mode or Slave mode. It has a Transfer Completion Flag and Write Collision Flag Protection ...
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... SPI CLOCK PORT GENERATOR master MISO 8-BIT SHIFT MOSI REGISTER SPICLK SPI CLOCK SS GENERATOR All information provided in this document is subject to legal disclaimers. Rev. 2 — 16 November 2010 P89LPC9321 slave MISO 8-BIT SHIFT MOSI REGISTER SPICLK SS 002aaa901 slave MISO 8-BIT SHIFT MOSI REGISTER ...
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... Fig 18. SPI single master multiple slaves configuration 7.26 Analog comparators Two analog comparators are provided on the P89LPC9321. Input and output options allow use of the comparators in a number of different configurations. Comparator operation is such that the output is a logical one (which may be read in a register and/or routed to a pin) when the positive input (one of two selectable inputs) is greater than the negative input (selectable from a pin or an internal reference voltage) ...
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... CP1 comparator 1 CO1 V change detect ref(bg) CN1 change detect CP2 comparator 2 CO2 CN2 All information provided in this document is subject to legal disclaimers. Rev. 2 — 16 November 2010 P89LPC9321 OE1 CMP1 (P0.6) CMF1 EC CMF2 CMP2 (P0.0) OE2 002aad561 © NXP B.V. 2010. All rights reserved. interrupt ...
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... Watchdog mode. Feeding the watchdog requires a two-byte sequence. If PCLK is selected as the watchdog clock and the CPU is powered down, the watchdog is disabled. The watchdog timer has a time-out period that ranges from a few μ few seconds. Please refer to the P89LPC9321 User manual for more details. P89LPC9321 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core All information provided in this document is subject to legal disclaimers ...
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... Data EEPROM The P89LPC9321 has 512 bytes of on-chip Data EEPROM. The Data EEPROM is SFR based, byte readable, byte writable, and erasable (via row fill and sector fill). The user can read, write and fill the memory via SFRs and one interrupt. This Data EEPROM provides 100,000 minimum erase/program cycles for each byte. • ...
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... Flash organization The program memory consists of eight 1 kB sectors on the P89LPC9321 devices. Each sector can be further divided into 64-byte pages. In addition to sector erase, page erase, and byte erase, a 64-byte page register is included which allows from bytes of a given page to be programmed at the same time, substantially reducing overall programming time ...
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... ICP is performed without removing the microcontroller from the system. The ICP facility consists of internal hardware resources to facilitate remote programming of the P89LPC9321 through a two-wire serial interface. The NXP ICP facility has made in-circuit programming in an embedded application - using commercially available programmers - possible with a minimum of additional expense in components and circuit board area. The ICP function uses five pins ...
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... Power-on reset code execution The P89LPC9321 contains two special flash elements: the Boot Vector and the Boot Status bit. Following reset, the P89LPC9321 examines the contents of the Boot Status bit. If the Boot Status bit is set to zero, power-up execution starts at location 0000H, which is the normal start address of the user’ ...
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... NXP Semiconductors 7.32 User sector security bytes There are eight User Sector Security Bytes on the P89LPC9321. Each byte corresponds to one sector. Please see the P89LPC9321 User manual for additional details. 7.33 PGA Additional PGA module is integrated. The gain of PGA can be programmable and 16. Please refer to Register PGACON1 and PGACON1B are used to for PGA1 configuration ...
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... XTAL1, XTAL2 to V based on package heat transfer, not device power consumption human body model; all pins charged device model; all pins All information provided in this document is subject to legal disclaimers. Rev. 2 — 16 November 2010 P89LPC9321 Min Max −55 +125 −65 +150 - 20 ...
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... XTAL1, XTAL2 pins; with respect except XTAL1, XTAL2 with respect 0 th(HL) All information provided in this document is subject to legal disclaimers. Rev. 2 — 16 November 2010 P89LPC9321 [1] Min Typ Max [ [ [2] - 3. [2] ...
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... BOE1, BOE0 = 01 BOE1, BOE0 = 10 BOE1, BOE0 = 11 falling stage rising stage specifications are measured using an external clock with the following functions disabled: comparators, All information provided in this document is subject to legal disclaimers. Rev. 2 — 16 November 2010 P89LPC9321 [1] Min Typ −30 [ ...
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... Port pins source a transition current when used in quasi-bidirectional mode and externally driven from logic 1 to logic 0. This current is highest when V is approximately P89LPC9321 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core All information provided in this document is subject to legal disclaimers. Rev. 2 — 16 November 2010 P89LPC9321 © NXP B.V. 2010. All rights reserved ...
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... Figure 21 16T see Figure 21 13T see Figure 21 see Figure 21 see Figure 21 All information provided in this document is subject to legal disclaimers. Rev. 2 — 16 November 2010 P89LPC9321 [1][2] Variable clock MHz osc Min Max Min 7.557 7.189 15.114 14.378 15.114 MHz 380 420 ...
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... Figure 23, 24, 25, 26 see Figure 23, 24, 25, 26 see Figure 23, 24, 25, 26 All information provided in this document is subject to legal disclaimers. Rev. 2 — 16 November 2010 P89LPC9321 [1][2] Variable clock MHz osc Min Max Min ⁄ - 500 CCLK ⁄ - 333 CCLK ...
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... Figure 21 see Figure 21 see Figure 21 see Figure 21 see Figure 21 see Figure 23, 24, 25, 26 All information provided in this document is subject to legal disclaimers. Rev. 2 — 16 November 2010 P89LPC9321 [1][2] Variable clock f osc Min Max Min 7.189 7.557 7.189 14.378 15.114 14.378 15.114 MHz 380 ...
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... Figure 23, 24, 25, 26 see Figure 23, 24, 25, 26 see Figure 23, 24, 25, 26 see Figure 23, 24, 25, 26 All information provided in this document is subject to legal disclaimers. Rev. 2 — 16 November 2010 P89LPC9321 [1][2] Variable clock f osc Min Max Min 250 - 250 250 - 250 ⁄ 167 CCLK ⁄ ...
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... SPIF SPIR t SPICLKL t SPICLKH t t SPIDSU SPIDH MSB/LSB SPIDV SPIOH master MSB/LSB out All information provided in this document is subject to legal disclaimers. Rev. 2 — 16 November 2010 P89LPC9321 valid valid valid t CHCX t CLCH T cy(clk) 002aaa907 t SPIR LSB/MSB in t SPIDV master LSB/MSB out ...
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... SPIOH SPIOH t t SPIDV SPIDV slave MSB/LSB out t t SPIDH SPIDSU MSB/LSB in All information provided in this document is subject to legal disclaimers. Rev. 2 — 16 November 2010 P89LPC9321 t SPIR LSB/MSB SPIOH SPIDV master LSB/MSB out 002aaa909 t SPILAG t SPIOH slave LSB/MSB out not defined ...
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... SPIDH MSB/LSB in Conditions pin RST pin RST pin RST RST t RL All information provided in this document is subject to legal disclaimers. Rev. 2 — 16 November 2010 P89LPC9321 t SPIR t SPILAG t SPIDIS slave LSB/MSB out t t SPIDSU SPIDH LSB/MSB in 002aaa911 Min Typ Max ...
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... This parameter is characterized, but not tested in production. P89LPC9321 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core Conditions 0 V < V < All information provided in this document is subject to legal disclaimers. Rev. 2 — 16 November 2010 P89LPC9321 Min Typ Max ± − 0 − ...
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... P89LPC9321 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core Ω . Conditions within accuracy of ADC All information provided in this document is subject to legal disclaimers. Rev. 2 — 16 November 2010 P89LPC9321 Min Typ Max - - 1 0.95 1.00 1.05 1.87 1.97 2.07 3.70 3.89 4.08 7.22 7 ...
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... REFERENCES JEDEC JEITA MS-018 EDR-7319 All information provided in this document is subject to legal disclaimers. Rev. 2 — 16 November 2010 P89LPC9321 detail ( max ...
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... 2.5 scale (1) ( 0.30 0.2 9.8 4.5 0.65 0.19 0.1 9.6 4.3 REFERENCES JEDEC JEITA MO-153 All information provided in this document is subject to legal disclaimers. Rev. 2 — 16 November 2010 P89LPC9321 detail 6.6 0.75 0.4 1 0.2 0.13 6.2 0.50 0.3 EUROPEAN PROJECTION ...
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... 1.7 0.53 0.32 36 14.1 1.3 0.38 0.23 35 13.7 0.013 0.066 0.020 1.41 0.56 0.051 0.014 0.009 1.34 0.54 REFERENCES JEDEC JEITA MO-015 SC-510-28 All information provided in this document is subject to legal disclaimers. Rev. 2 — 16 November 2010 P89LPC9321 3.9 15.80 17.15 2.54 15.24 3.4 15.24 15.90 0.15 0.62 0.68 0.1 0.6 ...
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... Random Access Memory Resistance-Capacitance Real-Time Clock Serial Clock Line Serial DAta Line Special Function Register Serial Peripheral Interface Universal Asynchronous Receiver/Transmitter All information provided in this document is subject to legal disclaimers. Rev. 2 — 16 November 2010 P89LPC9321 © NXP B.V. 2010. All rights reserved ...
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... NXP Semiconductors 14. Revision history Table 17. Revision history Document ID Release date P89LPC9321 v.2 20101116 • Modifications: Table • Table • Section • Section • Changed data sheet status to Product. P89LPC9321 v.1 20081209 P89LPC9321 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core Data sheet status Product data sheet 9: Updated table ...
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... Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. All information provided in this document is subject to legal disclaimers. Rev. 2 — 16 November 2010 P89LPC9321 © NXP B.V. 2010. All rights reserved ...
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... Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners C-bus — logo is a trademark of NXP B.V. http://www.nxp.com salesaddresses@nxp.com All information provided in this document is subject to legal disclaimers. Rev. 2 — 16 November 2010 P89LPC9321 © NXP B.V. 2010. All rights reserved ...
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... Additional features . . . . . . . . . . . . . . . . . . . . . 45 7.29.1 Software reset . . . . . . . . . . . . . . . . . . . . . . . . 45 7.29.2 Dual data pointers . . . . . . . . . . . . . . . . . . . . . 45 7.29.3 Data EEPROM . . . . . . . . . . . . . . . . . . . . . . . . 45 7.30 Flash program memory . . . . . . . . . . . . . . . . . 46 All information provided in this document is subject to legal disclaimers. Rev. 2 — 16 November 2010 P89LPC9321 th bit (bit 8) in double buffering 2 C-bus serial interface © NXP B.V. 2010. All rights reserved. continued >> ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com P89LPC9321 All rights reserved. Date of release: 16 November 2010 Document identifier: P89LPC9321 ...